Revision 99a0949b target-mips/cpu.h
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struct CPUMIPSState; |
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typedef struct r4k_tlb_t r4k_tlb_t;
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struct r4k_tlb_t {
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typedef struct r4k_tlb a_r4k_tlb;
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struct r4k_tlb {
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target_ulong VPN; |
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uint32_t PageMask; |
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uint_fast8_t ASID; |
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void (*helper_tlbr) (void); |
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union {
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struct {
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r4k_tlb_t tlb[MIPS_TLB_MAX];
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a_r4k_tlb tlb[MIPS_TLB_MAX];
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} r4k; |
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} mmu; |
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}; |
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typedef union fpr_t fpr_t; |
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union fpr_t {
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union fpr {
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float64 fd; /* ieee double precision */ |
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float32 fs[2];/* ieee single precision */ |
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uint64_t d; /* binary double fixed-point */ |
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typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; |
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struct CPUMIPSFPUContext {
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/* Floating point registers */ |
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fpr_t fpr[32];
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union fpr fpr[32];
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float_status fp_status; |
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/* fpu implementation/revision register (fir) */ |
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uint32_t fcr0; |
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#define CP0MVPC1_PCP1 0 |
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}; |
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typedef struct mips_def_t mips_def_t;
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typedef struct mips_def a_mips_def;
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#define MIPS_SHADOW_SET_MAX 16 |
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#define MIPS_TC_MAX 5 |
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CPU_COMMON |
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const mips_def_t *cpu_model;
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const a_mips_def *cpu_model;
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void *irq[8]; |
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struct QEMUTimer *timer; /* Internal timer */ |
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}; |
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void r4k_helper_tlbr (void); |
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void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
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void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
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void do_unassigned_access(a_target_phys_addr addr, int is_write, int is_exec,
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int unused, int size); |
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#define cpu_init cpu_mips_init |
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