Revision 99a0949b target-ppc/cpu.h
b/target-ppc/cpu.h | ||
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70 | 70 |
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71 | 71 |
/*****************************************************************************/ |
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/* MMU model */ |
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typedef enum powerpc_mmu_t powerpc_mmu_t;
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enum powerpc_mmu_t {
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typedef enum powerpc_mmu e_powerpc_mmu;
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enum powerpc_mmu { |
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POWERPC_MMU_UNKNOWN = 0x00000000, |
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/* Standard 32 bits PowerPC MMU */ |
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POWERPC_MMU_32B = 0x00000001, |
... | ... | |
104 | 104 |
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105 | 105 |
/*****************************************************************************/ |
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/* Exception model */ |
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typedef enum powerpc_excp_t powerpc_excp_t;
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enum powerpc_excp_t {
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typedef enum powerpc_excp e_powerpc_excp;
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enum powerpc_excp { |
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POWERPC_EXCP_UNKNOWN = 0, |
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/* Standard PowerPC exception model */ |
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POWERPC_EXCP_STD, |
... | ... | |
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/*****************************************************************************/ |
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/* Input pins model */ |
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typedef enum powerpc_input_t powerpc_input_t;
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enum powerpc_input_t {
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typedef enum powerpc_input e_powerpc_input;
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enum powerpc_input { |
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PPC_FLAGS_INPUT_UNKNOWN = 0, |
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/* PowerPC 6xx bus */ |
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PPC_FLAGS_INPUT_6xx, |
... | ... | |
278 | 278 |
#define PPC_INPUT(env) (env->bus_model) |
279 | 279 |
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280 | 280 |
/*****************************************************************************/ |
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typedef struct ppc_def_t ppc_def_t;
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typedef struct opc_handler_t opc_handler_t;
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typedef struct ppc_def a_ppc_def;
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typedef struct opc_handler an_opc_handler;
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283 | 283 |
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284 | 284 |
/*****************************************************************************/ |
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/* Types used to describe some PowerPC registers */ |
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typedef struct CPUPPCState CPUPPCState; |
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typedef struct ppc_tb_t ppc_tb_t; |
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typedef struct ppc_spr_t ppc_spr_t; |
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typedef struct ppc_dcr_t ppc_dcr_t; |
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typedef union ppc_avr_t ppc_avr_t; |
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typedef union ppc_tlb_t ppc_tlb_t; |
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typedef struct ppc_tb a_ppc_tb; |
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typedef struct ppc_spr a_ppc_spr; |
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typedef struct ppc_dcr a_ppc_dcr; |
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292 | 290 |
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293 | 291 |
/* SPR access micro-ops generations callbacks */ |
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struct ppc_spr_t {
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struct ppc_spr { |
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295 | 293 |
void (*uea_read)(void *opaque, int gpr_num, int spr_num); |
296 | 294 |
void (*uea_write)(void *opaque, int spr_num, int gpr_num); |
297 | 295 |
#if !defined(CONFIG_USER_ONLY) |
... | ... | |
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}; |
305 | 303 |
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306 | 304 |
/* Altivec registers (128 bits) */ |
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union ppc_avr_t {
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union ppc_avr { |
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308 | 306 |
float32 f[4]; |
309 | 307 |
uint8_t u8[16]; |
310 | 308 |
uint16_t u16[8]; |
... | ... | |
316 | 314 |
}; |
317 | 315 |
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318 | 316 |
/* Software TLB cache */ |
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typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
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struct ppc6xx_tlb_t {
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typedef struct ppc6xx_tlb a_ppc6xx_tlb;
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struct ppc6xx_tlb { |
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321 | 319 |
target_ulong pte0; |
322 | 320 |
target_ulong pte1; |
323 | 321 |
target_ulong EPN; |
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}; |
325 | 323 |
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typedef struct ppcemb_tlb_t ppcemb_tlb_t;
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struct ppcemb_tlb_t {
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target_phys_addr_t RPN;
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typedef struct ppcemb_tlb a_ppcemb_tlb;
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struct ppcemb_tlb { |
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a_target_phys_addr RPN;
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329 | 327 |
target_ulong EPN; |
330 | 328 |
target_ulong PID; |
331 | 329 |
target_ulong size; |
... | ... | |
333 | 331 |
uint32_t attr; /* Storage attributes */ |
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}; |
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union ppc_tlb_t {
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ppc6xx_tlb_t tlb6;
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ppcemb_tlb_t tlbe;
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union ppc_tlb { |
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a_ppc6xx_tlb tlb6;
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a_ppcemb_tlb tlbe;
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}; |
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typedef struct ppc_slb_t ppc_slb_t;
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struct ppc_slb_t {
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typedef struct ppc_slb a_ppc_slb;
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struct ppc_slb { |
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343 | 341 |
uint64_t tmp64; |
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uint32_t tmp; |
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}; |
... | ... | |
590 | 588 |
/* Address space register */ |
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target_ulong asr; |
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/* PowerPC 64 SLB area */ |
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ppc_slb_t slb[64];
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a_ppc_slb slb[64];
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int slb_nr; |
595 | 593 |
#endif |
596 | 594 |
/* segment registers */ |
... | ... | |
607 | 605 |
int last_way; /* Last used way used to allocate TLB in a LRU way */ |
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int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ |
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int nb_pids; /* Number of available PID registers */ |
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ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
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union ppc_tlb *tlb; /* TLB is optional. Allocate them only if needed */
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611 | 609 |
/* 403 dedicated access protection registers */ |
612 | 610 |
target_ulong pb[4]; |
613 | 611 |
#endif |
... | ... | |
615 | 613 |
/* Other registers */ |
616 | 614 |
/* Special purpose registers */ |
617 | 615 |
target_ulong spr[1024]; |
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ppc_spr_t spr_cb[1024];
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a_ppc_spr spr_cb[1024];
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619 | 617 |
/* Altivec registers */ |
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ppc_avr_t avr[32];
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union ppc_avr avr[32];
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621 | 619 |
uint32_t vscr; |
622 | 620 |
/* SPE registers */ |
623 | 621 |
uint64_t spe_acc; |
... | ... | |
628 | 626 |
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629 | 627 |
/* Internal devices resources */ |
630 | 628 |
/* Time base and decrementer */ |
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ppc_tb_t *tb_env;
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a_ppc_tb *tb_env;
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632 | 630 |
/* Device control registers */ |
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ppc_dcr_t *dcr_env;
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a_ppc_dcr *dcr_env;
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634 | 632 |
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635 | 633 |
int dcache_line_size; |
636 | 634 |
int icache_line_size; |
... | ... | |
638 | 636 |
/* Those resources are used during exception processing */ |
639 | 637 |
/* CPU model definition */ |
640 | 638 |
target_ulong msr_mask; |
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powerpc_mmu_t mmu_model;
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powerpc_excp_t excp_model;
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powerpc_input_t bus_model;
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e_powerpc_mmu mmu_model;
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e_powerpc_excp excp_model;
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e_powerpc_input bus_model;
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644 | 642 |
int bfd_mach; |
645 | 643 |
uint32_t flags; |
646 | 644 |
uint64_t insns_flags; |
... | ... | |
667 | 665 |
target_ulong nip; |
668 | 666 |
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669 | 667 |
/* opcode handlers */ |
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opc_handler_t *opcodes[0x40];
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an_opc_handler *opcodes[0x40];
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671 | 669 |
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672 | 670 |
/* Those resources are used only in Qemu core */ |
673 | 671 |
target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */ |
... | ... | |
683 | 681 |
}; |
684 | 682 |
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685 | 683 |
/* Context used internally during MMU translations */ |
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typedef struct mmu_ctx_t mmu_ctx_t;
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struct mmu_ctx_t {
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target_phys_addr_t raddr; /* Real address */
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target_phys_addr_t eaddr; /* Effective address */
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typedef struct mmu_ctx a_mmu_ctx;
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struct mmu_ctx { |
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a_target_phys_addr raddr; /* Real address */
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a_target_phys_addr eaddr; /* Effective address */
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int prot; /* Protection bits */ |
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target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
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a_target_phys_addr pg_addr[2]; /* PTE tables base addresses */
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692 | 690 |
target_ulong ptem; /* Virtual segment ID | API */ |
693 | 691 |
int key; /* Access key */ |
694 | 692 |
int nx; /* Non-execute area */ |
... | ... | |
707 | 705 |
int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw, |
708 | 706 |
int mmu_idx, int is_softmmu); |
709 | 707 |
#define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault |
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int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
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int get_physical_address (CPUPPCState *env, a_mmu_ctx *ctx, target_ulong vaddr,
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711 | 709 |
int rw, int access_type); |
712 | 710 |
void do_interrupt (CPUPPCState *env); |
713 | 711 |
void ppc_hw_interrupt (CPUPPCState *env); |
... | ... | |
738 | 736 |
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739 | 737 |
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
740 | 738 |
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const ppc_def_t *cpu_ppc_find_by_name (const char *name);
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int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
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const a_ppc_def *cpu_ppc_find_by_name (const char *name);
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int cpu_ppc_register_internal (CPUPPCState *env, const a_ppc_def *def);
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743 | 741 |
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744 | 742 |
/* Time-base and decrementer management */ |
745 | 743 |
#ifndef NO_CPU_IO_DEFS |
... | ... | |
797 | 795 |
} |
798 | 796 |
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799 | 797 |
/* Device control registers */ |
800 |
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
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int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
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int ppc_dcr_read (a_ppc_dcr *dcr_env, int dcrn, target_ulong *valp);
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int ppc_dcr_write (a_ppc_dcr *dcr_env, int dcrn, target_ulong val);
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802 | 800 |
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803 | 801 |
#define cpu_init cpu_ppc_init |
804 | 802 |
#define cpu_exec cpu_ppc_exec |
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