Archipelago » qemu

    return 1;

}

{

    return addr;

}

    return ret;

}

                             target_ulong pte1, int h, int rw, int type)

{

    target_ulong ptem, mmask;

            pp = pte1 & 0x00000003;

        }

        if (ptem == ctx->ptem) {

                /* all matches should have equal RPN, WIMG & PP */

                if ((ctx->raddr & mmask) != (pte1 & mmask)) {

                    qemu_log("Bad RPN/WIMG/PP\n");

    return ret;

}

                              target_ulong pte1, int h, int rw, int type)

{

    return _pte_check(ctx, 0, pte0, pte1, h, rw, type);

}

#if defined(TARGET_PPC64)

                              target_ulong pte1, int h, int rw, int type)

{

    return _pte_check(ctx, 1, pte0, pte1, h, rw, type);

}

#endif

                                   int ret, int rw)

{

    int store = 0;

static inline void ppc6xx_tlb_invalidate_all(CPUState *env)

{

    int nr, max;

    //LOG_SWTLB("Invalidate all TLBs\n");

                                                int is_code, int match_epn)

{

#if !defined(FLUSH_ALL_TLBS)

    int way, nr;

    /* Invalidate ITLB + DTLB, all ways */

void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,

                       target_ulong pte0, target_ulong pte1)

{

    int nr;

    nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);

    env->last_way = way;

}

                                   target_ulong eaddr, int rw, int access_type)

{

    int nr, best, way;

    int ret;

    *protp = prot;

}

                          int rw, int type)

{

    target_ulong *BATlt, *BATut, *BATu, *BATl;

}

/* PTE table lookup */

                            int type, int target_page_bits)

{

    target_ulong base, pte0, pte1;

    return ret;

}

                             int target_page_bits)

{

    return _find_pte(ctx, 0, h, rw, type, target_page_bits);

}

#if defined(TARGET_PPC64)

                             int target_page_bits)

{

    return _find_pte(ctx, 1, h, rw, type, target_page_bits);

}

#endif

                           int type, int target_page_bits)

{

#if defined(TARGET_PPC64)

}

#if defined(TARGET_PPC64)

{

#if 0 // XXX implement bridge mode?

    if (env->spr[SPR_ASR] & 1) {

        sr_base = env->spr[SPR_ASR] & 0xfffffffffffff000;

        sr_base += (12 * nr);

    return retval;

}

{

    if (slb == entry)

        return;

    entry->tmp = slb->tmp;

}

{

    return (int)(slb->tmp64 & 0x0000000008000000ULL);

}

{

    slb->tmp64 &= ~0x0000000008000000ULL;

}

    LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);

    mask = 0x0000000000000000ULL; /* Avoid gcc warning */

    for (n = 0; n < env->slb_nr; n++) {

        LOG_SLB("%s: seg %d %016" PRIx64 " %08"

                    PRIx32 "\n", __func__, n, slb->tmp64, slb->tmp);

    do_invalidate = 0;

    /* XXX: Warning: slbia never invalidates the first segment */

    for (n = 1; n < env->slb_nr; n++) {

        if (slb_is_valid(slb)) {

            slb_invalidate(slb);

    n = slb_lookup(env, T0, &vsid, &page_mask, &attr, NULL);

    if (n >= 0) {

        if (slb_is_valid(slb)) {

            slb_invalidate(slb);

target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)

{

    target_ulong rt;

    if (slb_is_valid(slb)) {

        /* SLB entry is valid */

void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs)

{

    uint64_t vsid;

    uint64_t esid;

#endif /* defined(TARGET_PPC64) */

/* Perform segment based translation */

                                            int sdr_sh,

{

}

                              target_ulong eaddr, int rw, int type)

{

    target_ulong sr, vsid, vsid_mask, pgidx, page_mask;

#if defined(TARGET_PPC64)

    int attr;

                ctx->ptem = (vsid << 7) | (pgidx >> 10);

            }

            /* Initialize real address with an invalid value */

            if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||

                         env->mmu_model == POWERPC_MMU_SOFT_74xx)) {

                /* Software TLB search */

            }

#if defined (DUMP_PAGE_TABLES)

            if (qemu_log_enabled()) {

                uint32_t a0, a1, a2, a3;

                qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx

                         "\n", sdr, mask + 0x80);

}

/* Generic TLB check function for embedded PowerPC implementations */

                                   target_ulong address, uint32_t pid, int ext,

                                   int i)

{

#if (TARGET_PHYS_ADDR_BITS >= 36)

    if (ext) {

        /* Extend the physical address to 36 bits */

    }

#endif

/* Generic TLB search function for PowerPC embedded implementations */

int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)

{

    int i, ret;

    /* Default return value is no match */

/* Helpers specific to PowerPC 40x implementations */

static inline void ppc4xx_tlb_invalidate_all(CPUState *env)

{

    int i;

    for (i = 0; i < env->nb_tlb; i++) {

                                              target_ulong eaddr, uint32_t pid)

{

#if !defined(FLUSH_ALL_TLBS)

    target_ulong page, end;

    int i;

#endif

}

                                 target_ulong address, int rw, int access_type)

{

    int i, ret, zsel, zpr, pr;

    ret = -1;

    pr = msr_pr;

    for (i = 0; i < env->nb_tlb; i++) {

        tlb = &env->tlb[i].tlbe;

    env->spr[SPR_405_SLER] = val;

}

                                          target_ulong address, int rw,

                                          int access_type)

{

    int i, prot, ret;

    ret = -1;

    for (i = 0; i < env->nb_tlb; i++) {

        tlb = &env->tlb[i].tlbe;

        if (ppcemb_tlb_check(env, tlb, &raddr, address,

    return ret;

}

                                 target_ulong eaddr, int rw)

{

    int in_plb, ret;

    return ret;

}

                          int rw, int access_type)

{

    int ret;

    return ret;

}

{

    if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0))

        return -1;

int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,

                              int mmu_idx, int is_softmmu)

{

    int access_type;

    int ret = 0;

CPUPPCState *cpu_ppc_init (const char *cpu_model)

{

    CPUPPCState *env;

    def = cpu_ppc_find_by_name(cpu_model);

    if (!def)