Revision 99a0949b target-sparc/op_helper.c
| b/target-sparc/op_helper.c | ||
|---|---|---|
| 1514 | 1514 |
case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ |
| 1515 | 1515 |
switch(size) {
|
| 1516 | 1516 |
case 1: |
| 1517 |
ret = ldub_phys((target_phys_addr_t)addr
|
|
| 1518 |
| ((target_phys_addr_t)(asi & 0xf) << 32));
|
|
| 1517 |
ret = ldub_phys((a_target_phys_addr)addr
|
|
| 1518 |
| ((a_target_phys_addr)(asi & 0xf) << 32));
|
|
| 1519 | 1519 |
break; |
| 1520 | 1520 |
case 2: |
| 1521 |
ret = lduw_phys((target_phys_addr_t)addr
|
|
| 1522 |
| ((target_phys_addr_t)(asi & 0xf) << 32));
|
|
| 1521 |
ret = lduw_phys((a_target_phys_addr)addr
|
|
| 1522 |
| ((a_target_phys_addr)(asi & 0xf) << 32));
|
|
| 1523 | 1523 |
break; |
| 1524 | 1524 |
default: |
| 1525 | 1525 |
case 4: |
| 1526 |
ret = ldl_phys((target_phys_addr_t)addr
|
|
| 1527 |
| ((target_phys_addr_t)(asi & 0xf) << 32));
|
|
| 1526 |
ret = ldl_phys((a_target_phys_addr)addr
|
|
| 1527 |
| ((a_target_phys_addr)(asi & 0xf) << 32));
|
|
| 1528 | 1528 |
break; |
| 1529 | 1529 |
case 8: |
| 1530 |
ret = ldq_phys((target_phys_addr_t)addr
|
|
| 1531 |
| ((target_phys_addr_t)(asi & 0xf) << 32));
|
|
| 1530 |
ret = ldq_phys((a_target_phys_addr)addr
|
|
| 1531 |
| ((a_target_phys_addr)(asi & 0xf) << 32));
|
|
| 1532 | 1532 |
break; |
| 1533 | 1533 |
} |
| 1534 | 1534 |
break; |
| ... | ... | |
| 1865 | 1865 |
{
|
| 1866 | 1866 |
switch(size) {
|
| 1867 | 1867 |
case 1: |
| 1868 |
stb_phys((target_phys_addr_t)addr
|
|
| 1869 |
| ((target_phys_addr_t)(asi & 0xf) << 32), val);
|
|
| 1868 |
stb_phys((a_target_phys_addr)addr
|
|
| 1869 |
| ((a_target_phys_addr)(asi & 0xf) << 32), val);
|
|
| 1870 | 1870 |
break; |
| 1871 | 1871 |
case 2: |
| 1872 |
stw_phys((target_phys_addr_t)addr
|
|
| 1873 |
| ((target_phys_addr_t)(asi & 0xf) << 32), val);
|
|
| 1872 |
stw_phys((a_target_phys_addr)addr
|
|
| 1873 |
| ((a_target_phys_addr)(asi & 0xf) << 32), val);
|
|
| 1874 | 1874 |
break; |
| 1875 | 1875 |
case 4: |
| 1876 | 1876 |
default: |
| 1877 |
stl_phys((target_phys_addr_t)addr
|
|
| 1878 |
| ((target_phys_addr_t)(asi & 0xf) << 32), val);
|
|
| 1877 |
stl_phys((a_target_phys_addr)addr
|
|
| 1878 |
| ((a_target_phys_addr)(asi & 0xf) << 32), val);
|
|
| 1879 | 1879 |
break; |
| 1880 | 1880 |
case 8: |
| 1881 |
stq_phys((target_phys_addr_t)addr
|
|
| 1882 |
| ((target_phys_addr_t)(asi & 0xf) << 32), val);
|
|
| 1881 |
stq_phys((a_target_phys_addr)addr
|
|
| 1882 |
| ((a_target_phys_addr)(asi & 0xf) << 32), val);
|
|
| 1883 | 1883 |
break; |
| 1884 | 1884 |
} |
| 1885 | 1885 |
} |
| ... | ... | |
| 3672 | 3672 |
#endif |
| 3673 | 3673 |
|
| 3674 | 3674 |
#ifndef TARGET_SPARC64 |
| 3675 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
|
|
| 3675 |
void do_unassigned_access(a_target_phys_addr addr, int is_write, int is_exec,
|
|
| 3676 | 3676 |
int is_asi, int size) |
| 3677 | 3677 |
{
|
| 3678 | 3678 |
CPUState *saved_env; |
| ... | ... | |
| 3714 | 3714 |
env = saved_env; |
| 3715 | 3715 |
} |
| 3716 | 3716 |
#else |
| 3717 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
|
|
| 3717 |
void do_unassigned_access(a_target_phys_addr addr, int is_write, int is_exec,
|
|
| 3718 | 3718 |
int is_asi, int size) |
| 3719 | 3719 |
{
|
| 3720 | 3720 |
#ifdef DEBUG_UNASSIGNED |
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