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/*
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* TI OMAP on-chip I2C controller. Only "new I2C" mode supported.
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*
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* Copyright (C) 2007 Andrzej Zaborowski <balrog@zabor.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h" |
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#include "i2c.h" |
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#include "omap.h" |
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|
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struct omap_i2c_s {
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qemu_irq irq; |
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qemu_irq drq[2];
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i2c_bus *bus; |
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|
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uint8_t revision; |
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uint8_t mask; |
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uint16_t stat; |
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uint16_t dma; |
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uint16_t count; |
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int count_cur;
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uint32_t fifo; |
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int rxlen;
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int txlen;
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uint16_t control; |
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uint16_t addr[2];
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uint8_t divider; |
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uint8_t times[2];
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uint16_t test; |
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}; |
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|
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#define OMAP2_INTR_REV 0x34 |
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#define OMAP2_GC_REV 0x34 |
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|
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static void omap_i2c_interrupts_update(struct omap_i2c_s *s) |
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{
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qemu_set_irq(s->irq, s->stat & s->mask); |
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if ((s->dma >> 15) & 1) /* RDMA_EN */ |
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qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */ |
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if ((s->dma >> 7) & 1) /* XDMA_EN */ |
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qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */ |
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} |
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|
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static void omap_i2c_fifo_run(struct omap_i2c_s *s) |
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{
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int ack = 1; |
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if (!i2c_bus_busy(s->bus))
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return;
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if ((s->control >> 2) & 1) { /* RM */ |
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if ((s->control >> 1) & 1) { /* STP */ |
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i2c_end_transfer(s->bus); |
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s->control &= ~(1 << 1); /* STP */ |
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s->count_cur = s->count; |
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s->txlen = 0;
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} else if ((s->control >> 9) & 1) { /* TRX */ |
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while (ack && s->txlen)
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ack = (i2c_send(s->bus, |
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(s->fifo >> ((-- s->txlen) << 3)) &
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0xff) >= 0); |
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s->stat |= 1 << 4; /* XRDY */ |
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} else {
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while (s->rxlen < 4) |
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s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
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s->stat |= 1 << 3; /* RRDY */ |
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} |
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} else {
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if ((s->control >> 9) & 1) { /* TRX */ |
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while (ack && s->count_cur && s->txlen) {
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ack = (i2c_send(s->bus, |
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(s->fifo >> ((-- s->txlen) << 3)) &
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0xff) >= 0); |
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s->count_cur --; |
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} |
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if (ack && s->count_cur)
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s->stat |= 1 << 4; /* XRDY */ |
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else
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s->stat &= ~(1 << 4); /* XRDY */ |
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if (!s->count_cur) {
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s->stat |= 1 << 2; /* ARDY */ |
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s->control &= ~(1 << 10); /* MST */ |
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} |
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} else {
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while (s->count_cur && s->rxlen < 4) { |
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s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
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s->count_cur --; |
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} |
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if (s->rxlen)
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s->stat |= 1 << 3; /* RRDY */ |
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else
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s->stat &= ~(1 << 3); /* RRDY */ |
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} |
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if (!s->count_cur) {
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if ((s->control >> 1) & 1) { /* STP */ |
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i2c_end_transfer(s->bus); |
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s->control &= ~(1 << 1); /* STP */ |
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s->count_cur = s->count; |
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s->txlen = 0;
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} else {
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s->stat |= 1 << 2; /* ARDY */ |
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s->control &= ~(1 << 10); /* MST */ |
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} |
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} |
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} |
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s->stat |= (!ack) << 1; /* NACK */ |
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if (!ack)
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s->control &= ~(1 << 1); /* STP */ |
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} |
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void omap_i2c_reset(struct omap_i2c_s *s) |
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{
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s->mask = 0;
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s->stat = 0;
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s->dma = 0;
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s->count = 0;
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s->count_cur = 0;
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s->fifo = 0;
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s->rxlen = 0;
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s->txlen = 0;
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s->control = 0;
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s->addr[0] = 0; |
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s->addr[1] = 0; |
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s->divider = 0;
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s->times[0] = 0; |
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s->times[1] = 0; |
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s->test = 0;
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} |
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static uint32_t omap_i2c_read(void *opaque, a_target_phys_addr addr) |
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{
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struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; |
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int offset = addr & OMAP_MPUI_REG_MASK;
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uint16_t ret; |
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switch (offset) {
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case 0x00: /* I2C_REV */ |
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return s->revision; /* REV */ |
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case 0x04: /* I2C_IE */ |
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return s->mask;
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case 0x08: /* I2C_STAT */ |
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return s->stat | (i2c_bus_busy(s->bus) << 12); |
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case 0x0c: /* I2C_IV */ |
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if (s->revision >= OMAP2_INTR_REV)
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break;
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ret = ffs(s->stat & s->mask); |
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if (ret)
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s->stat ^= 1 << (ret - 1); |
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omap_i2c_interrupts_update(s); |
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return ret;
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case 0x10: /* I2C_SYSS */ |
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return (s->control >> 15) & 1; /* I2C_EN */ |
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case 0x14: /* I2C_BUF */ |
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return s->dma;
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case 0x18: /* I2C_CNT */ |
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return s->count_cur; /* DCOUNT */ |
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case 0x1c: /* I2C_DATA */ |
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ret = 0;
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if (s->control & (1 << 14)) { /* BE */ |
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ret |= ((s->fifo >> 0) & 0xff) << 8; |
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ret |= ((s->fifo >> 8) & 0xff) << 0; |
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} else {
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ret |= ((s->fifo >> 8) & 0xff) << 8; |
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ret |= ((s->fifo >> 0) & 0xff) << 0; |
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} |
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if (s->rxlen == 1) { |
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s->stat |= 1 << 15; /* SBD */ |
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s->rxlen = 0;
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} else if (s->rxlen > 1) { |
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if (s->rxlen > 2) |
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s->fifo >>= 16;
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s->rxlen -= 2;
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} else
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/* XXX: remote access (qualifier) error - what's that? */;
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if (!s->rxlen) {
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s->stat &= ~(1 << 3); /* RRDY */ |
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if (((s->control >> 10) & 1) && /* MST */ |
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((~s->control >> 9) & 1)) { /* TRX */ |
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s->stat |= 1 << 2; /* ARDY */ |
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s->control &= ~(1 << 10); /* MST */ |
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} |
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} |
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s->stat &= ~(1 << 11); /* ROVR */ |
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omap_i2c_fifo_run(s); |
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omap_i2c_interrupts_update(s); |
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return ret;
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case 0x20: /* I2C_SYSC */ |
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return 0; |
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case 0x24: /* I2C_CON */ |
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return s->control;
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case 0x28: /* I2C_OA */ |
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return s->addr[0]; |
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case 0x2c: /* I2C_SA */ |
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return s->addr[1]; |
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case 0x30: /* I2C_PSC */ |
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return s->divider;
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case 0x34: /* I2C_SCLL */ |
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return s->times[0]; |
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case 0x38: /* I2C_SCLH */ |
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return s->times[1]; |
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case 0x3c: /* I2C_SYSTEST */ |
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if (s->test & (1 << 15)) { /* ST_EN */ |
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s->test ^= 0xa;
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return s->test;
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} else
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return s->test & ~0x300f; |
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} |
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OMAP_BAD_REG(addr); |
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return 0; |
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} |
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|
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static void omap_i2c_write(void *opaque, a_target_phys_addr addr, |
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uint32_t value) |
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{
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struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; |
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int offset = addr & OMAP_MPUI_REG_MASK;
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int nack;
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switch (offset) {
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case 0x00: /* I2C_REV */ |
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case 0x0c: /* I2C_IV */ |
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case 0x10: /* I2C_SYSS */ |
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OMAP_RO_REG(addr); |
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return;
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case 0x04: /* I2C_IE */ |
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s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f); |
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break;
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|
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case 0x08: /* I2C_STAT */ |
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if (s->revision < OMAP2_INTR_REV) {
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OMAP_RO_REG(addr); |
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return;
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} |
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/* RRDY and XRDY are reset by hardware. (in all versions???) */
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s->stat &= ~(value & 0x27);
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omap_i2c_interrupts_update(s); |
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break;
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|
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case 0x14: /* I2C_BUF */ |
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s->dma = value & 0x8080;
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if (value & (1 << 15)) /* RDMA_EN */ |
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s->mask &= ~(1 << 3); /* RRDY_IE */ |
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if (value & (1 << 7)) /* XDMA_EN */ |
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s->mask &= ~(1 << 4); /* XRDY_IE */ |
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break;
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|
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case 0x18: /* I2C_CNT */ |
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s->count = value; /* DCOUNT */
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break;
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|
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case 0x1c: /* I2C_DATA */ |
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if (s->txlen > 2) { |
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/* XXX: remote access (qualifier) error - what's that? */
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break;
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} |
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s->fifo <<= 16;
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s->txlen += 2;
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if (s->control & (1 << 14)) { /* BE */ |
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s->fifo |= ((value >> 8) & 0xff) << 8; |
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s->fifo |= ((value >> 0) & 0xff) << 0; |
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} else {
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s->fifo |= ((value >> 0) & 0xff) << 8; |
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s->fifo |= ((value >> 8) & 0xff) << 0; |
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} |
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s->stat &= ~(1 << 10); /* XUDF */ |
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if (s->txlen > 2) |
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s->stat &= ~(1 << 4); /* XRDY */ |
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omap_i2c_fifo_run(s); |
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omap_i2c_interrupts_update(s); |
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break;
|
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|
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case 0x20: /* I2C_SYSC */ |
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if (s->revision < OMAP2_INTR_REV) {
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OMAP_BAD_REG(addr); |
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return;
|
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} |
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|
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if (value & 2) |
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omap_i2c_reset(s); |
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break;
|
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|
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case 0x24: /* I2C_CON */ |
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s->control = value & 0xcf87;
|
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if (~value & (1 << 15)) { /* I2C_EN */ |
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if (s->revision < OMAP2_INTR_REV)
|
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omap_i2c_reset(s); |
| 318 |
break;
|
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} |
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if ((value & (1 << 15)) && !(value & (1 << 10))) { /* MST */ |
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fprintf(stderr, "%s: I^2C slave mode not supported\n",
|
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__FUNCTION__); |
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break;
|
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} |
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if ((value & (1 << 15)) && value & (1 << 8)) { /* XA */ |
| 326 |
fprintf(stderr, "%s: 10-bit addressing mode not supported\n",
|
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__FUNCTION__); |
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break;
|
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} |
| 330 |
if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */ |
| 331 |
nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */ |
| 332 |
(~value >> 9) & 1); /* TRX */ |
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s->stat |= nack << 1; /* NACK */ |
| 334 |
s->control &= ~(1 << 0); /* STT */ |
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s->fifo = 0;
|
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if (nack)
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s->control &= ~(1 << 1); /* STP */ |
| 338 |
else {
|
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s->count_cur = s->count; |
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omap_i2c_fifo_run(s); |
| 341 |
} |
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omap_i2c_interrupts_update(s); |
| 343 |
} |
| 344 |
break;
|
| 345 |
|
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case 0x28: /* I2C_OA */ |
| 347 |
s->addr[0] = value & 0x3ff; |
| 348 |
break;
|
| 349 |
|
| 350 |
case 0x2c: /* I2C_SA */ |
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s->addr[1] = value & 0x3ff; |
| 352 |
break;
|
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|
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case 0x30: /* I2C_PSC */ |
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s->divider = value; |
| 356 |
break;
|
| 357 |
|
| 358 |
case 0x34: /* I2C_SCLL */ |
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s->times[0] = value;
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break;
|
| 361 |
|
| 362 |
case 0x38: /* I2C_SCLH */ |
| 363 |
s->times[1] = value;
|
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break;
|
| 365 |
|
| 366 |
case 0x3c: /* I2C_SYSTEST */ |
| 367 |
s->test = value & 0xf80f;
|
| 368 |
if (value & (1 << 11)) /* SBB */ |
| 369 |
if (s->revision >= OMAP2_INTR_REV) {
|
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s->stat |= 0x3f;
|
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omap_i2c_interrupts_update(s); |
| 372 |
} |
| 373 |
if (value & (1 << 15)) /* ST_EN */ |
| 374 |
fprintf(stderr, "%s: System Test not supported\n", __FUNCTION__);
|
| 375 |
break;
|
| 376 |
|
| 377 |
default:
|
| 378 |
OMAP_BAD_REG(addr); |
| 379 |
return;
|
| 380 |
} |
| 381 |
} |
| 382 |
|
| 383 |
static void omap_i2c_writeb(void *opaque, a_target_phys_addr addr, |
| 384 |
uint32_t value) |
| 385 |
{
|
| 386 |
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; |
| 387 |
int offset = addr & OMAP_MPUI_REG_MASK;
|
| 388 |
|
| 389 |
switch (offset) {
|
| 390 |
case 0x1c: /* I2C_DATA */ |
| 391 |
if (s->txlen > 2) { |
| 392 |
/* XXX: remote access (qualifier) error - what's that? */
|
| 393 |
break;
|
| 394 |
} |
| 395 |
s->fifo <<= 8;
|
| 396 |
s->txlen += 1;
|
| 397 |
s->fifo |= value & 0xff;
|
| 398 |
s->stat &= ~(1 << 10); /* XUDF */ |
| 399 |
if (s->txlen > 2) |
| 400 |
s->stat &= ~(1 << 4); /* XRDY */ |
| 401 |
omap_i2c_fifo_run(s); |
| 402 |
omap_i2c_interrupts_update(s); |
| 403 |
break;
|
| 404 |
|
| 405 |
default:
|
| 406 |
OMAP_BAD_REG(addr); |
| 407 |
return;
|
| 408 |
} |
| 409 |
} |
| 410 |
|
| 411 |
static CPUReadMemoryFunc * const omap_i2c_readfn[] = { |
| 412 |
omap_badwidth_read16, |
| 413 |
omap_i2c_read, |
| 414 |
omap_badwidth_read16, |
| 415 |
}; |
| 416 |
|
| 417 |
static CPUWriteMemoryFunc * const omap_i2c_writefn[] = { |
| 418 |
omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
|
| 419 |
omap_i2c_write, |
| 420 |
omap_badwidth_write16, |
| 421 |
}; |
| 422 |
|
| 423 |
struct omap_i2c_s *omap_i2c_init(a_target_phys_addr base,
|
| 424 |
qemu_irq irq, qemu_irq *dma, omap_clk clk) |
| 425 |
{
|
| 426 |
int iomemtype;
|
| 427 |
struct omap_i2c_s *s = (struct omap_i2c_s *) |
| 428 |
qemu_mallocz(sizeof(struct omap_i2c_s)); |
| 429 |
|
| 430 |
/* TODO: set a value greater or equal to real hardware */
|
| 431 |
s->revision = 0x11;
|
| 432 |
s->irq = irq; |
| 433 |
s->drq[0] = dma[0]; |
| 434 |
s->drq[1] = dma[1]; |
| 435 |
s->bus = i2c_init_bus(NULL, "i2c"); |
| 436 |
omap_i2c_reset(s); |
| 437 |
|
| 438 |
iomemtype = cpu_register_io_memory(omap_i2c_readfn, |
| 439 |
omap_i2c_writefn, s); |
| 440 |
cpu_register_physical_memory(base, 0x800, iomemtype);
|
| 441 |
|
| 442 |
return s;
|
| 443 |
} |
| 444 |
|
| 445 |
struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta, |
| 446 |
qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk) |
| 447 |
{
|
| 448 |
int iomemtype;
|
| 449 |
struct omap_i2c_s *s = (struct omap_i2c_s *) |
| 450 |
qemu_mallocz(sizeof(struct omap_i2c_s)); |
| 451 |
|
| 452 |
s->revision = 0x34;
|
| 453 |
s->irq = irq; |
| 454 |
s->drq[0] = dma[0]; |
| 455 |
s->drq[1] = dma[1]; |
| 456 |
s->bus = i2c_init_bus(NULL, "i2c"); |
| 457 |
omap_i2c_reset(s); |
| 458 |
|
| 459 |
iomemtype = l4_register_io_memory(omap_i2c_readfn, |
| 460 |
omap_i2c_writefn, s); |
| 461 |
omap_l4_attach(ta, 0, iomemtype);
|
| 462 |
|
| 463 |
return s;
|
| 464 |
} |
| 465 |
|
| 466 |
i2c_bus *omap_i2c_bus(struct omap_i2c_s *s)
|
| 467 |
{
|
| 468 |
return s->bus;
|
| 469 |
} |