root / hw / tusb6010.c @ 99a0949b
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/*
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* Texas Instruments TUSB6010 emulation.
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* Based on reverse-engineering of a linux driver.
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*
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* Copyright (C) 2008 Nokia Corporation
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* Written by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu-common.h" |
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#include "qemu-timer.h" |
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#include "usb.h" |
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#include "omap.h" |
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#include "irq.h" |
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#include "devices.h" |
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struct TUSBState {
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int iomemtype[2]; |
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qemu_irq irq; |
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MUSBState *musb; |
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QEMUTimer *otg_timer; |
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QEMUTimer *pwr_timer; |
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int power;
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uint32_t scratch; |
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uint16_t test_reset; |
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uint32_t prcm_config; |
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uint32_t prcm_mngmt; |
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uint16_t otg_status; |
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uint32_t dev_config; |
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int host_mode;
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uint32_t intr; |
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uint32_t intr_ok; |
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uint32_t mask; |
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uint32_t usbip_intr; |
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uint32_t usbip_mask; |
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uint32_t gpio_intr; |
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uint32_t gpio_mask; |
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uint32_t gpio_config; |
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uint32_t dma_intr; |
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uint32_t dma_mask; |
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uint32_t dma_map; |
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uint32_t dma_config; |
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uint32_t ep0_config; |
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uint32_t rx_config[15];
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uint32_t tx_config[15];
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uint32_t wkup_mask; |
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uint32_t pullup[2];
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uint32_t control_config; |
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uint32_t otg_timer_val; |
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}; |
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#define TUSB_DEVCLOCK 60000000 /* 60 MHz */ |
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#define TUSB_VLYNQ_CTRL 0x004 |
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/* Mentor Graphics OTG core registers. */
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#define TUSB_BASE_OFFSET 0x400 |
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/* FIFO registers, 32-bit. */
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#define TUSB_FIFO_BASE 0x600 |
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/* Device System & Control registers, 32-bit. */
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#define TUSB_SYS_REG_BASE 0x800 |
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#define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000) |
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#define TUSB_DEV_CONF_USB_HOST_MODE (1 << 16) |
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#define TUSB_DEV_CONF_PROD_TEST_MODE (1 << 15) |
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#define TUSB_DEV_CONF_SOFT_ID (1 << 1) |
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#define TUSB_DEV_CONF_ID_SEL (1 << 0) |
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#define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004) |
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#define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008) |
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#define TUSB_PHY_OTG_CTRL_WRPROTECT (0xa5 << 24) |
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#define TUSB_PHY_OTG_CTRL_O_ID_PULLUP (1 << 23) |
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#define TUSB_PHY_OTG_CTRL_O_VBUS_DET_EN (1 << 19) |
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#define TUSB_PHY_OTG_CTRL_O_SESS_END_EN (1 << 18) |
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#define TUSB_PHY_OTG_CTRL_TESTM2 (1 << 17) |
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#define TUSB_PHY_OTG_CTRL_TESTM1 (1 << 16) |
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#define TUSB_PHY_OTG_CTRL_TESTM0 (1 << 15) |
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#define TUSB_PHY_OTG_CTRL_TX_DATA2 (1 << 14) |
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#define TUSB_PHY_OTG_CTRL_TX_GZ2 (1 << 13) |
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#define TUSB_PHY_OTG_CTRL_TX_ENABLE2 (1 << 12) |
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#define TUSB_PHY_OTG_CTRL_DM_PULLDOWN (1 << 11) |
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#define TUSB_PHY_OTG_CTRL_DP_PULLDOWN (1 << 10) |
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#define TUSB_PHY_OTG_CTRL_OSC_EN (1 << 9) |
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#define TUSB_PHY_OTG_CTRL_PHYREF_CLK(v) (((v) & 3) << 7) |
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#define TUSB_PHY_OTG_CTRL_PD (1 << 6) |
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#define TUSB_PHY_OTG_CTRL_PLL_ON (1 << 5) |
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#define TUSB_PHY_OTG_CTRL_EXT_RPU (1 << 4) |
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#define TUSB_PHY_OTG_CTRL_PWR_GOOD (1 << 3) |
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#define TUSB_PHY_OTG_CTRL_RESET (1 << 2) |
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#define TUSB_PHY_OTG_CTRL_SUSPENDM (1 << 1) |
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#define TUSB_PHY_OTG_CTRL_CLK_MODE (1 << 0) |
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/* OTG status register */
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#define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c) |
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#define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD (1 << 8) |
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#define TUSB_DEV_OTG_STAT_SESS_END (1 << 7) |
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#define TUSB_DEV_OTG_STAT_SESS_VALID (1 << 6) |
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#define TUSB_DEV_OTG_STAT_VBUS_VALID (1 << 5) |
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#define TUSB_DEV_OTG_STAT_VBUS_SENSE (1 << 4) |
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#define TUSB_DEV_OTG_STAT_ID_STATUS (1 << 3) |
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#define TUSB_DEV_OTG_STAT_HOST_DISCON (1 << 2) |
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#define TUSB_DEV_OTG_STAT_LINE_STATE (3 << 0) |
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#define TUSB_DEV_OTG_STAT_DP_ENABLE (1 << 1) |
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#define TUSB_DEV_OTG_STAT_DM_ENABLE (1 << 0) |
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#define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010) |
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#define TUSB_DEV_OTG_TIMER_ENABLE (1 << 31) |
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#define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff) |
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#define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014) |
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/* PRCM configuration register */
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#define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018) |
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#define TUSB_PRCM_CONF_SFW_CPEN (1 << 24) |
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#define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16) |
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/* PRCM management register */
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#define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c) |
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#define TUSB_PRCM_MNGMT_SRP_FIX_TMR(v) (((v) & 0xf) << 25) |
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#define TUSB_PRCM_MNGMT_SRP_FIX_EN (1 << 24) |
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#define TUSB_PRCM_MNGMT_VBUS_VAL_TMR(v) (((v) & 0xf) << 20) |
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#define TUSB_PRCM_MNGMT_VBUS_VAL_FLT_EN (1 << 19) |
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#define TUSB_PRCM_MNGMT_DFT_CLK_DIS (1 << 18) |
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#define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS (1 << 17) |
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#define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10) |
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#define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9) |
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#define TUSB_PRCM_MNGMT_OTG_ID_PULLUP (1 << 8) |
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#define TUSB_PRCM_MNGMT_15_SW_EN (1 << 4) |
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#define TUSB_PRCM_MNGMT_33_SW_EN (1 << 3) |
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#define TUSB_PRCM_MNGMT_5V_CPEN (1 << 2) |
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#define TUSB_PRCM_MNGMT_PM_IDLE (1 << 1) |
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#define TUSB_PRCM_MNGMT_DEV_IDLE (1 << 0) |
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/* Wake-up source clear and mask registers */
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#define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020) |
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#define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028) |
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#define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c) |
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#define TUSB_PRCM_WAKEUP_RESERVED_BITS (0xffffe << 13) |
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#define TUSB_PRCM_WGPIO_7 (1 << 12) |
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#define TUSB_PRCM_WGPIO_6 (1 << 11) |
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#define TUSB_PRCM_WGPIO_5 (1 << 10) |
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#define TUSB_PRCM_WGPIO_4 (1 << 9) |
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#define TUSB_PRCM_WGPIO_3 (1 << 8) |
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#define TUSB_PRCM_WGPIO_2 (1 << 7) |
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#define TUSB_PRCM_WGPIO_1 (1 << 6) |
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#define TUSB_PRCM_WGPIO_0 (1 << 5) |
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#define TUSB_PRCM_WHOSTDISCON (1 << 4) /* Host disconnect */ |
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#define TUSB_PRCM_WBUS (1 << 3) /* USB bus resume */ |
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#define TUSB_PRCM_WNORCS (1 << 2) /* NOR chip select */ |
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#define TUSB_PRCM_WVBUS (1 << 1) /* OTG PHY VBUS */ |
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#define TUSB_PRCM_WID (1 << 0) /* OTG PHY ID detect */ |
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#define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030) |
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#define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034) |
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#define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038) |
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#define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c) |
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#define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040) |
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#define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044) |
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#define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048) |
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#define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c) |
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#define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050) |
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#define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054) |
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#define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058) |
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#define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c) |
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#define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060) |
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#define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064) |
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#define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068) |
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#define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c) |
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/* NOR flash interrupt source registers */
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#define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070) |
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#define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074) |
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#define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078) |
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#define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c) |
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#define TUSB_INT_SRC_TXRX_DMA_DONE (1 << 24) |
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#define TUSB_INT_SRC_USB_IP_CORE (1 << 17) |
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#define TUSB_INT_SRC_OTG_TIMEOUT (1 << 16) |
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#define TUSB_INT_SRC_VBUS_SENSE_CHNG (1 << 15) |
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#define TUSB_INT_SRC_ID_STATUS_CHNG (1 << 14) |
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#define TUSB_INT_SRC_DEV_WAKEUP (1 << 13) |
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#define TUSB_INT_SRC_DEV_READY (1 << 12) |
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#define TUSB_INT_SRC_USB_IP_TX (1 << 9) |
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#define TUSB_INT_SRC_USB_IP_RX (1 << 8) |
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#define TUSB_INT_SRC_USB_IP_VBUS_ERR (1 << 7) |
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#define TUSB_INT_SRC_USB_IP_VBUS_REQ (1 << 6) |
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#define TUSB_INT_SRC_USB_IP_DISCON (1 << 5) |
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#define TUSB_INT_SRC_USB_IP_CONN (1 << 4) |
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#define TUSB_INT_SRC_USB_IP_SOF (1 << 3) |
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#define TUSB_INT_SRC_USB_IP_RST_BABBLE (1 << 2) |
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#define TUSB_INT_SRC_USB_IP_RESUME (1 << 1) |
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#define TUSB_INT_SRC_USB_IP_SUSPEND (1 << 0) |
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#define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080) |
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#define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084) |
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#define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100) |
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#define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104) |
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#define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108) |
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#define TUSB_EP_IN_SIZE (TUSB_SYS_REG_BASE + 0x10c) |
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#define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148) |
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#define TUSB_EP_OUT_SIZE (TUSB_SYS_REG_BASE + 0x14c) |
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#define TUSB_EP_MAX_PACKET_SIZE_OFFSET (TUSB_SYS_REG_BASE + 0x188) |
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#define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4) |
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#define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8) |
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#define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8) |
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|
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#define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8) |
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#define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc) |
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/* Device System & Control register bitfields */
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#define TUSB_INT_CTRL_CONF_INT_RLCYC(v) (((v) & 0x7) << 18) |
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#define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17) |
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#define TUSB_INT_CTRL_CONF_INT_MODE (1 << 16) |
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#define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24) |
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#define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26) |
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#define TUSB_DMA_REQ_CONF_DMA_RQ_EN(v) (((v) & 0x3f) << 20) |
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#define TUSB_DMA_REQ_CONF_DMA_RQ_ASR(v) (((v) & 0xf) << 16) |
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#define TUSB_EP0_CONFIG_SW_EN (1 << 8) |
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#define TUSB_EP0_CONFIG_DIR_TX (1 << 7) |
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#define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f) |
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#define TUSB_EP_CONFIG_SW_EN (1 << 31) |
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#define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff) |
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#define TUSB_PROD_TEST_RESET_VAL 0xa596 |
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|
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int tusb6010_sync_io(TUSBState *s)
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{ |
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return s->iomemtype[0]; |
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} |
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int tusb6010_async_io(TUSBState *s)
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{ |
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return s->iomemtype[1]; |
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} |
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static void tusb_intr_update(TUSBState *s) |
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{ |
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if (s->control_config & TUSB_INT_CTRL_CONF_INT_POLARITY)
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qemu_set_irq(s->irq, s->intr & ~s->mask & s->intr_ok); |
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else
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qemu_set_irq(s->irq, (!(s->intr & ~s->mask)) & s->intr_ok); |
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} |
254 |
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static void tusb_usbip_intr_update(TUSBState *s) |
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{ |
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/* TX interrupt in the MUSB */
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if (s->usbip_intr & 0x0000ffff & ~s->usbip_mask) |
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s->intr |= TUSB_INT_SRC_USB_IP_TX; |
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else
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s->intr &= ~TUSB_INT_SRC_USB_IP_TX; |
262 |
|
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/* RX interrupt in the MUSB */
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if (s->usbip_intr & 0xffff0000 & ~s->usbip_mask) |
265 |
s->intr |= TUSB_INT_SRC_USB_IP_RX; |
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else
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s->intr &= ~TUSB_INT_SRC_USB_IP_RX; |
268 |
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/* XXX: What about TUSB_INT_SRC_USB_IP_CORE? */
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tusb_intr_update(s); |
272 |
} |
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static void tusb_dma_intr_update(TUSBState *s) |
275 |
{ |
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if (s->dma_intr & ~s->dma_mask)
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s->intr |= TUSB_INT_SRC_TXRX_DMA_DONE; |
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else
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s->intr &= ~TUSB_INT_SRC_TXRX_DMA_DONE; |
280 |
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tusb_intr_update(s); |
282 |
} |
283 |
|
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static void tusb_gpio_intr_update(TUSBState *s) |
285 |
{ |
286 |
/* TODO: How is this signalled? */
|
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} |
288 |
|
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extern CPUReadMemoryFunc * const musb_read[]; |
290 |
extern CPUWriteMemoryFunc * const musb_write[]; |
291 |
|
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static uint32_t tusb_async_readb(void *opaque, a_target_phys_addr addr) |
293 |
{ |
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TUSBState *s = (TUSBState *) opaque; |
295 |
|
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switch (addr & 0xfff) { |
297 |
case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
298 |
return musb_read[0](s->musb, addr & 0x1ff); |
299 |
|
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case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
301 |
return musb_read[0](s->musb, 0x20 + ((addr >> 3) & 0x3c)); |
302 |
} |
303 |
|
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printf("%s: unknown register at %03x\n",
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__FUNCTION__, (int) (addr & 0xfff)); |
306 |
return 0; |
307 |
} |
308 |
|
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static uint32_t tusb_async_readh(void *opaque, a_target_phys_addr addr) |
310 |
{ |
311 |
TUSBState *s = (TUSBState *) opaque; |
312 |
|
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switch (addr & 0xfff) { |
314 |
case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
315 |
return musb_read[1](s->musb, addr & 0x1ff); |
316 |
|
317 |
case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
318 |
return musb_read[1](s->musb, 0x20 + ((addr >> 3) & 0x3c)); |
319 |
} |
320 |
|
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printf("%s: unknown register at %03x\n",
|
322 |
__FUNCTION__, (int) (addr & 0xfff)); |
323 |
return 0; |
324 |
} |
325 |
|
326 |
static uint32_t tusb_async_readw(void *opaque, a_target_phys_addr addr) |
327 |
{ |
328 |
TUSBState *s = (TUSBState *) opaque; |
329 |
int offset = addr & 0xfff; |
330 |
int epnum;
|
331 |
uint32_t ret; |
332 |
|
333 |
switch (offset) {
|
334 |
case TUSB_DEV_CONF:
|
335 |
return s->dev_config;
|
336 |
|
337 |
case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
338 |
return musb_read[2](s->musb, offset & 0x1ff); |
339 |
|
340 |
case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
341 |
return musb_read[2](s->musb, 0x20 + ((addr >> 3) & 0x3c)); |
342 |
|
343 |
case TUSB_PHY_OTG_CTRL_ENABLE:
|
344 |
case TUSB_PHY_OTG_CTRL:
|
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return 0x00; /* TODO */ |
346 |
|
347 |
case TUSB_DEV_OTG_STAT:
|
348 |
ret = s->otg_status; |
349 |
#if 0
|
350 |
if (!(s->prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN))
|
351 |
ret &= ~TUSB_DEV_OTG_STAT_VBUS_VALID;
|
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#endif
|
353 |
return ret;
|
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case TUSB_DEV_OTG_TIMER:
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return s->otg_timer_val;
|
356 |
|
357 |
case TUSB_PRCM_REV:
|
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return 0x20; |
359 |
case TUSB_PRCM_CONF:
|
360 |
return s->prcm_config;
|
361 |
case TUSB_PRCM_MNGMT:
|
362 |
return s->prcm_mngmt;
|
363 |
case TUSB_PRCM_WAKEUP_SOURCE:
|
364 |
case TUSB_PRCM_WAKEUP_CLEAR: /* TODO: What does this one return? */ |
365 |
return 0x00000000; |
366 |
case TUSB_PRCM_WAKEUP_MASK:
|
367 |
return s->wkup_mask;
|
368 |
|
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case TUSB_PULLUP_1_CTRL:
|
370 |
return s->pullup[0]; |
371 |
case TUSB_PULLUP_2_CTRL:
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return s->pullup[1]; |
373 |
|
374 |
case TUSB_INT_CTRL_REV:
|
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return 0x20; |
376 |
case TUSB_INT_CTRL_CONF:
|
377 |
return s->control_config;
|
378 |
|
379 |
case TUSB_USBIP_INT_SRC:
|
380 |
case TUSB_USBIP_INT_SET: /* TODO: What do these two return? */ |
381 |
case TUSB_USBIP_INT_CLEAR:
|
382 |
return s->usbip_intr;
|
383 |
case TUSB_USBIP_INT_MASK:
|
384 |
return s->usbip_mask;
|
385 |
|
386 |
case TUSB_DMA_INT_SRC:
|
387 |
case TUSB_DMA_INT_SET: /* TODO: What do these two return? */ |
388 |
case TUSB_DMA_INT_CLEAR:
|
389 |
return s->dma_intr;
|
390 |
case TUSB_DMA_INT_MASK:
|
391 |
return s->dma_mask;
|
392 |
|
393 |
case TUSB_GPIO_INT_SRC: /* TODO: What do these two return? */ |
394 |
case TUSB_GPIO_INT_SET:
|
395 |
case TUSB_GPIO_INT_CLEAR:
|
396 |
return s->gpio_intr;
|
397 |
case TUSB_GPIO_INT_MASK:
|
398 |
return s->gpio_mask;
|
399 |
|
400 |
case TUSB_INT_SRC:
|
401 |
case TUSB_INT_SRC_SET: /* TODO: What do these two return? */ |
402 |
case TUSB_INT_SRC_CLEAR:
|
403 |
return s->intr;
|
404 |
case TUSB_INT_MASK:
|
405 |
return s->mask;
|
406 |
|
407 |
case TUSB_GPIO_REV:
|
408 |
return 0x30; |
409 |
case TUSB_GPIO_CONF:
|
410 |
return s->gpio_config;
|
411 |
|
412 |
case TUSB_DMA_CTRL_REV:
|
413 |
return 0x30; |
414 |
case TUSB_DMA_REQ_CONF:
|
415 |
return s->dma_config;
|
416 |
case TUSB_EP0_CONF:
|
417 |
return s->ep0_config;
|
418 |
case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b): |
419 |
epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
|
420 |
return s->tx_config[epnum];
|
421 |
case TUSB_DMA_EP_MAP:
|
422 |
return s->dma_map;
|
423 |
case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b): |
424 |
epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
|
425 |
return s->rx_config[epnum];
|
426 |
case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
|
427 |
(TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
|
428 |
epnum = (offset - TUSB_EP_MAX_PACKET_SIZE_OFFSET) >> 2;
|
429 |
return 0x00000000; /* TODO */ |
430 |
case TUSB_WAIT_COUNT:
|
431 |
return 0x00; /* TODO */ |
432 |
|
433 |
case TUSB_SCRATCH_PAD:
|
434 |
return s->scratch;
|
435 |
|
436 |
case TUSB_PROD_TEST_RESET:
|
437 |
return s->test_reset;
|
438 |
|
439 |
/* DIE IDs */
|
440 |
case TUSB_DIDR1_LO:
|
441 |
return 0xa9453c59; |
442 |
case TUSB_DIDR1_HI:
|
443 |
return 0x54059adf; |
444 |
} |
445 |
|
446 |
printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
|
447 |
return 0; |
448 |
} |
449 |
|
450 |
static void tusb_async_writeb(void *opaque, a_target_phys_addr addr, |
451 |
uint32_t value) |
452 |
{ |
453 |
TUSBState *s = (TUSBState *) opaque; |
454 |
|
455 |
switch (addr & 0xfff) { |
456 |
case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
457 |
musb_write[0](s->musb, addr & 0x1ff, value); |
458 |
break;
|
459 |
|
460 |
case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
461 |
musb_write[0](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); |
462 |
break;
|
463 |
|
464 |
default:
|
465 |
printf("%s: unknown register at %03x\n",
|
466 |
__FUNCTION__, (int) (addr & 0xfff)); |
467 |
return;
|
468 |
} |
469 |
} |
470 |
|
471 |
static void tusb_async_writeh(void *opaque, a_target_phys_addr addr, |
472 |
uint32_t value) |
473 |
{ |
474 |
TUSBState *s = (TUSBState *) opaque; |
475 |
|
476 |
switch (addr & 0xfff) { |
477 |
case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
478 |
musb_write[1](s->musb, addr & 0x1ff, value); |
479 |
break;
|
480 |
|
481 |
case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
482 |
musb_write[1](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); |
483 |
break;
|
484 |
|
485 |
default:
|
486 |
printf("%s: unknown register at %03x\n",
|
487 |
__FUNCTION__, (int) (addr & 0xfff)); |
488 |
return;
|
489 |
} |
490 |
} |
491 |
|
492 |
static void tusb_async_writew(void *opaque, a_target_phys_addr addr, |
493 |
uint32_t value) |
494 |
{ |
495 |
TUSBState *s = (TUSBState *) opaque; |
496 |
int offset = addr & 0xfff; |
497 |
int epnum;
|
498 |
|
499 |
switch (offset) {
|
500 |
case TUSB_VLYNQ_CTRL:
|
501 |
break;
|
502 |
|
503 |
case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): |
504 |
musb_write[2](s->musb, offset & 0x1ff, value); |
505 |
break;
|
506 |
|
507 |
case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): |
508 |
musb_write[2](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); |
509 |
break;
|
510 |
|
511 |
case TUSB_DEV_CONF:
|
512 |
s->dev_config = value; |
513 |
s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE); |
514 |
if (value & TUSB_DEV_CONF_PROD_TEST_MODE)
|
515 |
hw_error("%s: Product Test mode not allowed\n", __FUNCTION__);
|
516 |
break;
|
517 |
|
518 |
case TUSB_PHY_OTG_CTRL_ENABLE:
|
519 |
case TUSB_PHY_OTG_CTRL:
|
520 |
return; /* TODO */ |
521 |
case TUSB_DEV_OTG_TIMER:
|
522 |
s->otg_timer_val = value; |
523 |
if (value & TUSB_DEV_OTG_TIMER_ENABLE)
|
524 |
qemu_mod_timer(s->otg_timer, qemu_get_clock(vm_clock) + |
525 |
muldiv64(TUSB_DEV_OTG_TIMER_VAL(value), |
526 |
get_ticks_per_sec(), TUSB_DEVCLOCK)); |
527 |
else
|
528 |
qemu_del_timer(s->otg_timer); |
529 |
break;
|
530 |
|
531 |
case TUSB_PRCM_CONF:
|
532 |
s->prcm_config = value; |
533 |
break;
|
534 |
case TUSB_PRCM_MNGMT:
|
535 |
s->prcm_mngmt = value; |
536 |
break;
|
537 |
case TUSB_PRCM_WAKEUP_CLEAR:
|
538 |
break;
|
539 |
case TUSB_PRCM_WAKEUP_MASK:
|
540 |
s->wkup_mask = value; |
541 |
break;
|
542 |
|
543 |
case TUSB_PULLUP_1_CTRL:
|
544 |
s->pullup[0] = value;
|
545 |
break;
|
546 |
case TUSB_PULLUP_2_CTRL:
|
547 |
s->pullup[1] = value;
|
548 |
break;
|
549 |
case TUSB_INT_CTRL_CONF:
|
550 |
s->control_config = value; |
551 |
tusb_intr_update(s); |
552 |
break;
|
553 |
|
554 |
case TUSB_USBIP_INT_SET:
|
555 |
s->usbip_intr |= value; |
556 |
tusb_usbip_intr_update(s); |
557 |
break;
|
558 |
case TUSB_USBIP_INT_CLEAR:
|
559 |
s->usbip_intr &= ~value; |
560 |
tusb_usbip_intr_update(s); |
561 |
musb_core_intr_clear(s->musb, ~value); |
562 |
break;
|
563 |
case TUSB_USBIP_INT_MASK:
|
564 |
s->usbip_mask = value; |
565 |
tusb_usbip_intr_update(s); |
566 |
break;
|
567 |
|
568 |
case TUSB_DMA_INT_SET:
|
569 |
s->dma_intr |= value; |
570 |
tusb_dma_intr_update(s); |
571 |
break;
|
572 |
case TUSB_DMA_INT_CLEAR:
|
573 |
s->dma_intr &= ~value; |
574 |
tusb_dma_intr_update(s); |
575 |
break;
|
576 |
case TUSB_DMA_INT_MASK:
|
577 |
s->dma_mask = value; |
578 |
tusb_dma_intr_update(s); |
579 |
break;
|
580 |
|
581 |
case TUSB_GPIO_INT_SET:
|
582 |
s->gpio_intr |= value; |
583 |
tusb_gpio_intr_update(s); |
584 |
break;
|
585 |
case TUSB_GPIO_INT_CLEAR:
|
586 |
s->gpio_intr &= ~value; |
587 |
tusb_gpio_intr_update(s); |
588 |
break;
|
589 |
case TUSB_GPIO_INT_MASK:
|
590 |
s->gpio_mask = value; |
591 |
tusb_gpio_intr_update(s); |
592 |
break;
|
593 |
|
594 |
case TUSB_INT_SRC_SET:
|
595 |
s->intr |= value; |
596 |
tusb_intr_update(s); |
597 |
break;
|
598 |
case TUSB_INT_SRC_CLEAR:
|
599 |
s->intr &= ~value; |
600 |
tusb_intr_update(s); |
601 |
break;
|
602 |
case TUSB_INT_MASK:
|
603 |
s->mask = value; |
604 |
tusb_intr_update(s); |
605 |
break;
|
606 |
|
607 |
case TUSB_GPIO_CONF:
|
608 |
s->gpio_config = value; |
609 |
break;
|
610 |
case TUSB_DMA_REQ_CONF:
|
611 |
s->dma_config = value; |
612 |
break;
|
613 |
case TUSB_EP0_CONF:
|
614 |
s->ep0_config = value & 0x1ff;
|
615 |
musb_set_size(s->musb, 0, TUSB_EP0_CONFIG_XFR_SIZE(value),
|
616 |
value & TUSB_EP0_CONFIG_DIR_TX); |
617 |
break;
|
618 |
case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b): |
619 |
epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
|
620 |
s->tx_config[epnum] = value; |
621 |
musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 1); |
622 |
break;
|
623 |
case TUSB_DMA_EP_MAP:
|
624 |
s->dma_map = value; |
625 |
break;
|
626 |
case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b): |
627 |
epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
|
628 |
s->rx_config[epnum] = value; |
629 |
musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 0); |
630 |
break;
|
631 |
case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
|
632 |
(TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
|
633 |
epnum = (offset - TUSB_EP_MAX_PACKET_SIZE_OFFSET) >> 2;
|
634 |
return; /* TODO */ |
635 |
case TUSB_WAIT_COUNT:
|
636 |
return; /* TODO */ |
637 |
|
638 |
case TUSB_SCRATCH_PAD:
|
639 |
s->scratch = value; |
640 |
break;
|
641 |
|
642 |
case TUSB_PROD_TEST_RESET:
|
643 |
s->test_reset = value; |
644 |
break;
|
645 |
|
646 |
default:
|
647 |
printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
|
648 |
return;
|
649 |
} |
650 |
} |
651 |
|
652 |
static CPUReadMemoryFunc * const tusb_async_readfn[] = { |
653 |
tusb_async_readb, |
654 |
tusb_async_readh, |
655 |
tusb_async_readw, |
656 |
}; |
657 |
|
658 |
static CPUWriteMemoryFunc * const tusb_async_writefn[] = { |
659 |
tusb_async_writeb, |
660 |
tusb_async_writeh, |
661 |
tusb_async_writew, |
662 |
}; |
663 |
|
664 |
static void tusb_otg_tick(void *opaque) |
665 |
{ |
666 |
TUSBState *s = (TUSBState *) opaque; |
667 |
|
668 |
s->otg_timer_val = 0;
|
669 |
s->intr |= TUSB_INT_SRC_OTG_TIMEOUT; |
670 |
tusb_intr_update(s); |
671 |
} |
672 |
|
673 |
static void tusb_power_tick(void *opaque) |
674 |
{ |
675 |
TUSBState *s = (TUSBState *) opaque; |
676 |
|
677 |
if (s->power) {
|
678 |
s->intr_ok = ~0;
|
679 |
tusb_intr_update(s); |
680 |
} |
681 |
} |
682 |
|
683 |
static void tusb_musb_core_intr(void *opaque, int source, int level) |
684 |
{ |
685 |
TUSBState *s = (TUSBState *) opaque; |
686 |
uint16_t otg_status = s->otg_status; |
687 |
|
688 |
switch (source) {
|
689 |
case musb_set_vbus:
|
690 |
if (level)
|
691 |
otg_status |= TUSB_DEV_OTG_STAT_VBUS_VALID; |
692 |
else
|
693 |
otg_status &= ~TUSB_DEV_OTG_STAT_VBUS_VALID; |
694 |
|
695 |
/* XXX: only if TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN set? */
|
696 |
/* XXX: only if TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN set? */
|
697 |
if (s->otg_status != otg_status) {
|
698 |
s->otg_status = otg_status; |
699 |
s->intr |= TUSB_INT_SRC_VBUS_SENSE_CHNG; |
700 |
tusb_intr_update(s); |
701 |
} |
702 |
break;
|
703 |
|
704 |
case musb_set_session:
|
705 |
/* XXX: only if TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN set? */
|
706 |
/* XXX: only if TUSB_PRCM_MNGMT_OTG_SESS_END_EN set? */
|
707 |
if (level) {
|
708 |
s->otg_status |= TUSB_DEV_OTG_STAT_SESS_VALID; |
709 |
s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_END; |
710 |
} else {
|
711 |
s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_VALID; |
712 |
s->otg_status |= TUSB_DEV_OTG_STAT_SESS_END; |
713 |
} |
714 |
|
715 |
/* XXX: some IRQ or anything? */
|
716 |
break;
|
717 |
|
718 |
case musb_irq_tx:
|
719 |
case musb_irq_rx:
|
720 |
s->usbip_intr = musb_core_intr_get(s->musb); |
721 |
/* Fall through. */
|
722 |
default:
|
723 |
if (level)
|
724 |
s->intr |= 1 << source;
|
725 |
else
|
726 |
s->intr &= ~(1 << source);
|
727 |
tusb_intr_update(s); |
728 |
break;
|
729 |
} |
730 |
} |
731 |
|
732 |
TUSBState *tusb6010_init(qemu_irq intr) |
733 |
{ |
734 |
TUSBState *s = qemu_mallocz(sizeof(*s));
|
735 |
|
736 |
s->test_reset = TUSB_PROD_TEST_RESET_VAL; |
737 |
s->host_mode = 0;
|
738 |
s->dev_config = 0;
|
739 |
s->otg_status = 0; /* !TUSB_DEV_OTG_STAT_ID_STATUS means host mode */ |
740 |
s->power = 0;
|
741 |
s->mask = 0xffffffff;
|
742 |
s->intr = 0x00000000;
|
743 |
s->otg_timer_val = 0;
|
744 |
s->iomemtype[1] = cpu_register_io_memory(tusb_async_readfn,
|
745 |
tusb_async_writefn, s); |
746 |
s->irq = intr; |
747 |
s->otg_timer = qemu_new_timer(vm_clock, tusb_otg_tick, s); |
748 |
s->pwr_timer = qemu_new_timer(vm_clock, tusb_power_tick, s); |
749 |
s->musb = musb_init(qemu_allocate_irqs(tusb_musb_core_intr, s, |
750 |
__musb_irq_max)); |
751 |
|
752 |
return s;
|
753 |
} |
754 |
|
755 |
void tusb6010_power(TUSBState *s, int on) |
756 |
{ |
757 |
if (!on)
|
758 |
s->power = 0;
|
759 |
else if (!s->power && on) { |
760 |
s->power = 1;
|
761 |
|
762 |
/* Pull the interrupt down after TUSB6010 comes up. */
|
763 |
s->intr_ok = 0;
|
764 |
tusb_intr_update(s); |
765 |
qemu_mod_timer(s->pwr_timer, |
766 |
qemu_get_clock(vm_clock) + get_ticks_per_sec() / 2);
|
767 |
} |
768 |
} |