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/*
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 * QEMU Sparc Sun4m ECC memory controller emulation
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 *
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 * Copyright (c) 2007 Robert Reif
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "hw.h"
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#include "sun4m.h"
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#include "sysemu.h"
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//#define DEBUG_ECC
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#ifdef DEBUG_ECC
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#define DPRINTF(fmt, args...)                           \
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    do { printf("ECC: " fmt , ##args); } while (0)
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#else
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#define DPRINTF(fmt, args...)
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#endif
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/* There are 3 versions of this chip used in SMP sun4m systems:
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 * MCC (version 0, implementation 0) SS-600MP
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 * EMC (version 0, implementation 1) SS-10
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 * SMC (version 0, implementation 2) SS-10SX and SS-20
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 */
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/* Register offsets */
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#define ECC_FCR_REG    0
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#define ECC_FSR_REG    8
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#define ECC_FAR0_REG   16
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#define ECC_FAR1_REG   20
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#define ECC_DIAG_REG   24
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/* ECC fault control register */
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#define ECC_FCR_EE     0x00000001      /* Enable ECC checking */
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#define ECC_FCR_EI     0x00000010      /* Enable Interrupts on correctable errors */
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#define ECC_FCR_VER    0x0f000000      /* Version */
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#define ECC_FCR_IMPL   0xf0000000      /* Implementation */
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/* ECC fault status register */
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#define ECC_FSR_CE     0x00000001      /* Correctable error */
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#define ECC_FSR_BS     0x00000002      /* C2 graphics bad slot access */
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#define ECC_FSR_TO     0x00000004      /* Timeout on write */
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#define ECC_FSR_UE     0x00000008      /* Uncorrectable error */
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#define ECC_FSR_DW     0x000000f0      /* Index of double word in block */
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#define ECC_FSR_SYND   0x0000ff00      /* Syndrome for correctable error */
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#define ECC_FSR_ME     0x00010000      /* Multiple errors */
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#define ECC_FSR_C2ERR  0x00020000      /* C2 graphics error */
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/* ECC fault address register 0 */
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#define ECC_FAR0_PADDR 0x0000000f      /* PA[32-35] */
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#define ECC_FAR0_TYPE  0x000000f0      /* Transaction type */
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#define ECC_FAR0_SIZE  0x00000700      /* Transaction size */
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#define ECC_FAR0_CACHE 0x00000800      /* Mapped cacheable */
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#define ECC_FAR0_LOCK  0x00001000      /* Error occurred in atomic cycle */
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#define ECC_FAR0_BMODE 0x00002000      /* Boot mode */
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#define ECC_FAR0_VADDR 0x003fc000      /* VA[12-19] (superset bits) */
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#define ECC_FAR0_S     0x08000000      /* Supervisor mode */
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#define ECC_FARO_MID   0xf0000000      /* Module ID */
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/* ECC diagnostic register */
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#define ECC_DIAG_CBX   0x00000001
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#define ECC_DIAG_CB0   0x00000002
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#define ECC_DIAG_CB1   0x00000004
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#define ECC_DIAG_CB2   0x00000008
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#define ECC_DIAG_CB4   0x00000010
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#define ECC_DIAG_CB8   0x00000020
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#define ECC_DIAG_CB16  0x00000040
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#define ECC_DIAG_CB32  0x00000080
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#define ECC_DIAG_DMODE 0x00000c00
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#define ECC_NREGS      8
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#define ECC_SIZE       (ECC_NREGS * sizeof(uint32_t))
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#define ECC_ADDR_MASK  (ECC_SIZE - 1)
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typedef struct ECCState {
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    qemu_irq irq;
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    uint32_t regs[ECC_NREGS];
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} ECCState;
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static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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    ECCState *s = opaque;
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    switch (addr & ECC_ADDR_MASK) {
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    case ECC_FCR_REG:
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        s->regs[0] = (s->regs[0] & (ECC_FCR_VER | ECC_FCR_IMPL)) |
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                     (val & ~(ECC_FCR_VER | ECC_FCR_IMPL));
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        DPRINTF("Write fault control %08x\n", val);
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        break;
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    case 4:
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        s->regs[1] =  val;
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        DPRINTF("Write reg[1] %08x\n", val);
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        break;
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    case ECC_FSR_REG:
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        s->regs[2] =  val;
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        DPRINTF("Write fault status %08x\n", val);
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        break;
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    case 12:
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        s->regs[3] =  val;
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        DPRINTF("Write reg[3] %08x\n", val);
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        break;
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    case ECC_FAR0_REG:
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        s->regs[4] =  val;
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        DPRINTF("Write fault address 0 %08x\n", val);
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        break;
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    case ECC_FAR1_REG:
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        s->regs[5] =  val;
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        DPRINTF("Write fault address 1 %08x\n", val);
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        break;
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    case ECC_DIAG_REG:
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        s->regs[6] =  val;
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        DPRINTF("Write diag %08x\n", val);
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        break;
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    case 28:
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        s->regs[7] =  val;
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        DPRINTF("Write reg[7] %08x\n", val);
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        break;
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    }
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}
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static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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    ECCState *s = opaque;
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    uint32_t ret = 0;
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    switch (addr & ECC_ADDR_MASK) {
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    case ECC_FCR_REG:
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        ret = s->regs[0];
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        DPRINTF("Read enable %08x\n", ret);
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        break;
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    case 4:
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        ret = s->regs[1];
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        DPRINTF("Read register[1] %08x\n", ret);
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        break;
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    case ECC_FSR_REG:
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        ret = s->regs[2];
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        DPRINTF("Read fault status %08x\n", ret);
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        break;
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    case 12:
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        ret = s->regs[3];
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        DPRINTF("Read reg[3] %08x\n", ret);
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        break;
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    case ECC_FAR0_REG:
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        ret = s->regs[4];
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        DPRINTF("Read fault address 0 %08x\n", ret);
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        break;
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    case ECC_FAR1_REG:
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        ret = s->regs[5];
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        DPRINTF("Read fault address 1 %08x\n", ret);
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        break;
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    case ECC_DIAG_REG:
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        ret = s->regs[6];
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        DPRINTF("Read diag %08x\n", ret);
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        break;
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    case 28:
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        ret = s->regs[7];
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        DPRINTF("Read reg[7] %08x\n", ret);
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        break;
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    }
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    return ret;
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}
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static CPUReadMemoryFunc *ecc_mem_read[3] = {
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    NULL,
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    NULL,
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    ecc_mem_readl,
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};
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static CPUWriteMemoryFunc *ecc_mem_write[3] = {
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    NULL,
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    NULL,
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    ecc_mem_writel,
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};
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static int ecc_load(QEMUFile *f, void *opaque, int version_id)
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{
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    ECCState *s = opaque;
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    int i;
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    if (version_id != 1)
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        return -EINVAL;
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    for (i = 0; i < ECC_NREGS; i++)
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        qemu_get_be32s(f, &s->regs[i]);
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    return 0;
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}
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static void ecc_save(QEMUFile *f, void *opaque)
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{
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    ECCState *s = opaque;
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    int i;
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    for (i = 0; i < ECC_NREGS; i++)
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        qemu_put_be32s(f, &s->regs[i]);
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}
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static void ecc_reset(void *opaque)
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{
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    ECCState *s = opaque;
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    int i;
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    s->regs[ECC_FCR_REG] &= (ECC_FCR_VER | ECC_FCR_IMPL);
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    for (i = 1; i < ECC_NREGS; i++)
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        s->regs[i] = 0;
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}
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void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
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{
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    int ecc_io_memory;
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    ECCState *s;
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    s = qemu_mallocz(sizeof(ECCState));
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    if (!s)
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        return NULL;
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    s->regs[0] = version;
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    s->irq = irq;
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    ecc_io_memory = cpu_register_io_memory(0, ecc_mem_read, ecc_mem_write, s);
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    cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory);
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    register_savevm("ECC", base, 1, ecc_save, ecc_load, s);
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    qemu_register_reset(ecc_reset, s);
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    ecc_reset(s);
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    return s;
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}