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#ifndef FIRMWARE_ABI_H
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#define FIRMWARE_ABI_H
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#ifndef __ASSEMBLY__
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/* Open Hack'Ware NVRAM configuration structure */
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/* Version 3 */
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typedef struct ohwcfg_v3_t ohwcfg_v3_t;
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struct ohwcfg_v3_t {
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    /* 0x00: structure identifier                    */
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    uint8_t  struct_ident[0x10];
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    /* 0x10: structure version and NVRAM description */
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    uint32_t struct_version;
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    uint16_t nvram_size;
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    uint16_t pad0;
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    uint16_t nvram_arch_ptr;
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    uint16_t nvram_arch_size;
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    uint16_t nvram_arch_crc;
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    uint8_t  pad1[0x02];
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    /* 0x20: host architecture                       */
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    uint8_t  arch[0x10];
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    /* 0x30: RAM/ROM description                     */
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    uint64_t RAM0_base;
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    uint64_t RAM0_size;
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    uint64_t RAM1_base;
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    uint64_t RAM1_size;
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    uint64_t RAM2_base;
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    uint64_t RAM2_size;
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    uint64_t RAM3_base;
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    uint64_t RAM3_size;
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    uint64_t ROM_base;
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    uint64_t ROM_size;
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    /* 0x80: Kernel description                      */
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    uint64_t kernel_image;
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    uint64_t kernel_size;
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    /* 0x90: Kernel command line                     */
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    uint64_t cmdline;
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    uint64_t cmdline_size;
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    /* 0xA0: Kernel boot image                       */
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    uint64_t initrd_image;
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    uint64_t initrd_size;
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    /* 0xB0: NVRAM image                             */
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    uint64_t NVRAM_image;
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    uint8_t  pad2[8];
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    /* 0xC0: graphic configuration                   */
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    uint16_t width;
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    uint16_t height;
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    uint16_t depth;
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    uint16_t graphic_flags;
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    /* 0xC8: CPUs description                        */
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    uint8_t  nb_cpus;
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    uint8_t  boot_cpu;
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    uint8_t  nboot_devices;
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    uint8_t  pad3[5];
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    /* 0xD0: boot devices                            */
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    uint8_t  boot_devices[0x10];
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    /* 0xE0                                          */
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    uint8_t  pad4[0x1C]; /* 28 */
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    /* 0xFC: checksum                                */
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    uint16_t crc;
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    uint8_t  pad5[0x02];
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} __attribute__ (( packed ));
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#define OHW_GF_NOGRAPHICS 0x0001
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static inline uint16_t
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OHW_crc_update (uint16_t prev, uint16_t value)
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{
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    uint16_t tmp;
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    uint16_t pd, pd1, pd2;
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    tmp = prev >> 8;
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    pd = prev ^ value;
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    pd1 = pd & 0x000F;
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    pd2 = ((pd >> 4) & 0x000F) ^ pd1;
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    tmp ^= (pd1 << 3) | (pd1 << 8);
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    tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
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    return tmp;
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}
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static inline uint16_t
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OHW_compute_crc (ohwcfg_v3_t *header, uint32_t start, uint32_t count)
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{
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    uint32_t i;
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    uint16_t crc = 0xFFFF;
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    uint8_t *ptr = (uint8_t *)header;
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    int odd;
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    odd = count & 1;
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    count &= ~1;
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    for (i = 0; i != count; i++) {
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        crc = OHW_crc_update(crc, (ptr[start + i] << 8) | ptr[start + i + 1]);
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    }
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    if (odd) {
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        crc = OHW_crc_update(crc, ptr[start + i] << 8);
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    }
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    return crc;
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}
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/* Sparc32 runtime NVRAM structure for SMP CPU boot */
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struct sparc_arch_cfg {
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    uint32_t smp_ctx;
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    uint32_t smp_ctxtbl;
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    uint32_t smp_entry;
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    uint8_t valid;
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    uint8_t unused[51];
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};
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/* OpenBIOS NVRAM partition */
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struct OpenBIOS_nvpart_v1 {
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    uint8_t signature;
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    uint8_t checksum;
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    uint16_t len; // BE, length divided by 16
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    char name[12];
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};
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#define OPENBIOS_PART_SYSTEM 0x70
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#define OPENBIOS_PART_FREE 0x7f
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static inline void
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OpenBIOS_finish_partition(struct OpenBIOS_nvpart_v1 *header, uint32_t size)
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{
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    unsigned int i, sum;
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    uint8_t *tmpptr;
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    // Length divided by 16
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    header->len = cpu_to_be16(size >> 4);
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    // Checksum
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    tmpptr = (uint8_t *)header;
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    sum = *tmpptr;
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    for (i = 0; i < 14; i++) {
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        sum += tmpptr[2 + i];
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        sum = (sum + ((sum & 0xff00) >> 8)) & 0xff;
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    }
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    header->checksum = sum & 0xff;
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}
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static inline uint32_t
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OpenBIOS_set_var(uint8_t *nvram, uint32_t addr, const unsigned char *str)
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{
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    uint32_t len;
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    len = strlen(str) + 1;
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    memcpy(&nvram[addr], str, len);
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    return addr + len;
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}
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/* Sun IDPROM structure at the end of NVRAM */
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struct Sun_nvram {
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    uint8_t type;
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    uint8_t machine_id;
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    uint8_t macaddr[6];
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    uint8_t unused[7];
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    uint8_t checksum;
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};
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static inline void
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Sun_init_header(struct Sun_nvram *header, const uint8_t *macaddr, int machine_id)
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{
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    uint8_t tmp, *tmpptr;
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    unsigned int i;
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    header->type = 1;
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    header->machine_id = machine_id & 0xff;
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    memcpy(&header->macaddr, macaddr, 6);
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    /* Calculate checksum */
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    tmp = 0;
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    tmpptr = (uint8_t *)header;
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    for (i = 0; i < 15; i++)
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        tmp ^= tmpptr[i];
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    header->checksum = tmp;
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}
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#else /* __ASSEMBLY__ */
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/* Structure offsets for asm use */
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/* Open Hack'Ware NVRAM configuration structure */
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#define OHW_ARCH_PTR   0x18
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#define OHW_RAM_SIZE   0x38
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#define OHW_BOOT_CPU   0xC9
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/* Sparc32 runtime NVRAM structure for SMP CPU boot */
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#define SPARC_SMP_CTX    0x0
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#define SPARC_SMP_CTXTBL 0x4
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#define SPARC_SMP_ENTRY  0x8
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#define SPARC_SMP_VALID  0xc
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/* Sun IDPROM structure at the end of NVRAM */
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#define SPARC_MACHINE_ID 0x1fd9
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#endif /* __ASSEMBLY__ */
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#endif /* FIRMWARE_ABI_H */