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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Andrzej Zaborowski
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#if defined(__ARM_ARCH_7__) ||  \
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    defined(__ARM_ARCH_7A__) || \
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    defined(__ARM_ARCH_7EM__) || \
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    defined(__ARM_ARCH_7M__) || \
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    defined(__ARM_ARCH_7R__)
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#define USE_ARMV7_INSTRUCTIONS
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#endif
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#if defined(USE_ARMV7_INSTRUCTIONS) || \
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    defined(__ARM_ARCH_6J__) || \
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    defined(__ARM_ARCH_6K__) || \
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    defined(__ARM_ARCH_6T2__) || \
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    defined(__ARM_ARCH_6Z__) || \
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    defined(__ARM_ARCH_6ZK__)
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#define USE_ARMV6_INSTRUCTIONS
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#endif
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#if defined(USE_ARMV6_INSTRUCTIONS) || \
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    defined(__ARM_ARCH_5T__) || \
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    defined(__ARM_ARCH_5TE__) || \
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    defined(__ARM_ARCH_5TEJ__)
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#define USE_ARMV5_INSTRUCTIONS
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#endif
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#ifdef USE_ARMV5_INSTRUCTIONS
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static const int use_armv5_instructions = 1;
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#else
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static const int use_armv5_instructions = 0;
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#endif
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#undef USE_ARMV5_INSTRUCTIONS
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#ifdef USE_ARMV6_INSTRUCTIONS
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static const int use_armv6_instructions = 1;
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#else
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static const int use_armv6_instructions = 0;
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#endif
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#undef USE_ARMV6_INSTRUCTIONS
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#ifdef USE_ARMV7_INSTRUCTIONS
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static const int use_armv7_instructions = 1;
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#else
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static const int use_armv7_instructions = 0;
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#endif
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#undef USE_ARMV7_INSTRUCTIONS
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#ifndef NDEBUG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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    "%r0",
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    "%r1",
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    "%r2",
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    "%r3",
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    "%r4",
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    "%r5",
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    "%r6",
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    "%r7",
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    "%r8",
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    "%r9",
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    "%r10",
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    "%r11",
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    "%r12",
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    "%r13",
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    "%r14",
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    "%pc",
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};
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#endif
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static const int tcg_target_reg_alloc_order[] = {
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    TCG_REG_R4,
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    TCG_REG_R5,
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    TCG_REG_R6,
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    TCG_REG_R7,
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    TCG_REG_R8,
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    TCG_REG_R9,
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    TCG_REG_R10,
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    TCG_REG_R11,
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    TCG_REG_R13,
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    TCG_REG_R0,
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    TCG_REG_R1,
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    TCG_REG_R2,
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    TCG_REG_R3,
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    TCG_REG_R12,
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    TCG_REG_R14,
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};
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static const int tcg_target_call_iarg_regs[4] = {
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    TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
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};
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static const int tcg_target_call_oarg_regs[2] = {
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    TCG_REG_R0, TCG_REG_R1
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};
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static inline void reloc_abs32(void *code_ptr, tcg_target_long target)
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{
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    *(uint32_t *) code_ptr = target;
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}
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static inline void reloc_pc24(void *code_ptr, tcg_target_long target)
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{
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    uint32_t offset = ((target - ((tcg_target_long) code_ptr + 8)) >> 2);
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    *(uint32_t *) code_ptr = ((*(uint32_t *) code_ptr) & ~0xffffff)
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                             | (offset & 0xffffff);
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}
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static void patch_reloc(uint8_t *code_ptr, int type,
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                tcg_target_long value, tcg_target_long addend)
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{
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    switch (type) {
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    case R_ARM_ABS32:
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        reloc_abs32(code_ptr, value);
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        break;
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    case R_ARM_CALL:
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    case R_ARM_JUMP24:
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    default:
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        tcg_abort();
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    case R_ARM_PC24:
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        reloc_pc24(code_ptr, value);
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        break;
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    }
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}
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/* maximum number of register used for input function arguments */
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static inline int tcg_target_get_call_iarg_regs_count(int flags)
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{
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    return 4;
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}
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/* parse target specific constraints */
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static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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{
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    const char *ct_str;
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    ct_str = *pct_str;
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    switch (ct_str[0]) {
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    case 'I':
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         ct->ct |= TCG_CT_CONST_ARM;
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         break;
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    case 'r':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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        break;
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    /* qemu_ld address */
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    case 'l':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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#ifdef CONFIG_SOFTMMU
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        /* r0 and r1 will be overwritten when reading the tlb entry,
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           so don't use these. */
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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#endif
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        break;
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    case 'L':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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#ifdef CONFIG_SOFTMMU
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        /* r1 is still needed to load data_reg or data_reg2,
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           so don't use it. */
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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#endif
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        break;
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    /* qemu_st address & data_reg */
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    case 's':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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        /* r0 and r1 will be overwritten when reading the tlb entry
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           (softmmu only) and doing the byte swapping, so don't
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           use these. */
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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        break;
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    /* qemu_st64 data_reg2 */
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    case 'S':
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        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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        /* r0 and r1 will be overwritten when reading the tlb entry
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            (softmmu only) and doing the byte swapping, so don't
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            use these. */
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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#ifdef CONFIG_SOFTMMU
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        /* r2 is still needed to load data_reg, so don't use it. */
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        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
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#endif
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        break;
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    default:
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        return -1;
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    }
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    ct_str++;
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    *pct_str = ct_str;
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    return 0;
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}
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static inline uint32_t rotl(uint32_t val, int n)
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{
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  return (val << n) | (val >> (32 - n));
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}
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/* ARM immediates for ALU instructions are made of an unsigned 8-bit
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   right-rotated by an even amount between 0 and 30. */
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static inline int encode_imm(uint32_t imm)
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{
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    int shift;
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    /* simple case, only lower bits */
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    if ((imm & ~0xff) == 0)
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        return 0;
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    /* then try a simple even shift */
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    shift = ctz32(imm) & ~1;
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    if (((imm >> shift) & ~0xff) == 0)
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        return 32 - shift;
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    /* now try harder with rotations */
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    if ((rotl(imm, 2) & ~0xff) == 0)
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        return 2;
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    if ((rotl(imm, 4) & ~0xff) == 0)
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        return 4;
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    if ((rotl(imm, 6) & ~0xff) == 0)
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        return 6;
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    /* imm can't be encoded */
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    return -1;
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}
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static inline int check_fit_imm(uint32_t imm)
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{
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    return encode_imm(imm) >= 0;
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}
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/* Test if a constant matches the constraint.
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 * TODO: define constraints for:
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 *
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 * ldr/str offset:   between -0xfff and 0xfff
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 * ldrh/strh offset: between -0xff and 0xff
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 * mov operand2:     values represented with x << (2 * y), x < 0x100
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 * add, sub, eor...: ditto
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 */
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static inline int tcg_target_const_match(tcg_target_long val,
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                const TCGArgConstraint *arg_ct)
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{
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    int ct;
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    ct = arg_ct->ct;
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    if (ct & TCG_CT_CONST)
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        return 1;
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    else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val))
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        return 1;
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    else
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        return 0;
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}
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enum arm_data_opc_e {
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    ARITH_AND = 0x0,
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    ARITH_EOR = 0x1,
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    ARITH_SUB = 0x2,
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    ARITH_RSB = 0x3,
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    ARITH_ADD = 0x4,
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    ARITH_ADC = 0x5,
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    ARITH_SBC = 0x6,
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    ARITH_RSC = 0x7,
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    ARITH_TST = 0x8,
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    ARITH_CMP = 0xa,
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    ARITH_CMN = 0xb,
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    ARITH_ORR = 0xc,
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    ARITH_MOV = 0xd,
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    ARITH_BIC = 0xe,
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    ARITH_MVN = 0xf,
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};
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#define TO_CPSR(opc) \
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  ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
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#define SHIFT_IMM_LSL(im)        (((im) << 7) | 0x00)
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#define SHIFT_IMM_LSR(im)        (((im) << 7) | 0x20)
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#define SHIFT_IMM_ASR(im)        (((im) << 7) | 0x40)
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#define SHIFT_IMM_ROR(im)        (((im) << 7) | 0x60)
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#define SHIFT_REG_LSL(rs)        (((rs) << 8) | 0x10)
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#define SHIFT_REG_LSR(rs)        (((rs) << 8) | 0x30)
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#define SHIFT_REG_ASR(rs)        (((rs) << 8) | 0x50)
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#define SHIFT_REG_ROR(rs)        (((rs) << 8) | 0x70)
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enum arm_cond_code_e {
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    COND_EQ = 0x0,
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    COND_NE = 0x1,
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    COND_CS = 0x2,        /* Unsigned greater or equal */
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    COND_CC = 0x3,        /* Unsigned less than */
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    COND_MI = 0x4,        /* Negative */
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    COND_PL = 0x5,        /* Zero or greater */
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    COND_VS = 0x6,        /* Overflow */
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    COND_VC = 0x7,        /* No overflow */
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    COND_HI = 0x8,        /* Unsigned greater than */
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    COND_LS = 0x9,        /* Unsigned less or equal */
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    COND_GE = 0xa,
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    COND_LT = 0xb,
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    COND_GT = 0xc,
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    COND_LE = 0xd,
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    COND_AL = 0xe,
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};
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static const uint8_t tcg_cond_to_arm_cond[10] = {
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    [TCG_COND_EQ] = COND_EQ,
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    [TCG_COND_NE] = COND_NE,
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    [TCG_COND_LT] = COND_LT,
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    [TCG_COND_GE] = COND_GE,
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    [TCG_COND_LE] = COND_LE,
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    [TCG_COND_GT] = COND_GT,
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    /* unsigned */
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    [TCG_COND_LTU] = COND_CC,
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    [TCG_COND_GEU] = COND_CS,
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    [TCG_COND_LEU] = COND_LS,
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    [TCG_COND_GTU] = COND_HI,
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};
341 811d4cf4 balrog
342 811d4cf4 balrog
static inline void tcg_out_bx(TCGContext *s, int cond, int rn)
343 811d4cf4 balrog
{
344 811d4cf4 balrog
    tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
345 811d4cf4 balrog
}
346 811d4cf4 balrog
347 811d4cf4 balrog
static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
348 811d4cf4 balrog
{
349 811d4cf4 balrog
    tcg_out32(s, (cond << 28) | 0x0a000000 |
350 811d4cf4 balrog
                    (((offset - 8) >> 2) & 0x00ffffff));
351 811d4cf4 balrog
}
352 811d4cf4 balrog
353 e936243a balrog
static inline void tcg_out_b_noaddr(TCGContext *s, int cond)
354 e936243a balrog
{
355 e2542fe2 Juan Quintela
#ifdef HOST_WORDS_BIGENDIAN
356 e936243a balrog
    tcg_out8(s, (cond << 4) | 0x0a);
357 e936243a balrog
    s->code_ptr += 3;
358 e936243a balrog
#else
359 e936243a balrog
    s->code_ptr += 3;
360 e936243a balrog
    tcg_out8(s, (cond << 4) | 0x0a);
361 e936243a balrog
#endif
362 e936243a balrog
}
363 e936243a balrog
364 811d4cf4 balrog
static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
365 811d4cf4 balrog
{
366 811d4cf4 balrog
    tcg_out32(s, (cond << 28) | 0x0b000000 |
367 811d4cf4 balrog
                    (((offset - 8) >> 2) & 0x00ffffff));
368 811d4cf4 balrog
}
369 811d4cf4 balrog
370 23401b58 Aurelien Jarno
static inline void tcg_out_blx(TCGContext *s, int cond, int rn)
371 23401b58 Aurelien Jarno
{
372 23401b58 Aurelien Jarno
    tcg_out32(s, (cond << 28) | 0x012fff30 | rn);
373 23401b58 Aurelien Jarno
}
374 23401b58 Aurelien Jarno
375 811d4cf4 balrog
static inline void tcg_out_dat_reg(TCGContext *s,
376 811d4cf4 balrog
                int cond, int opc, int rd, int rn, int rm, int shift)
377 811d4cf4 balrog
{
378 811d4cf4 balrog
    tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
379 811d4cf4 balrog
                    (rn << 16) | (rd << 12) | shift | rm);
380 811d4cf4 balrog
}
381 811d4cf4 balrog
382 811d4cf4 balrog
static inline void tcg_out_dat_reg2(TCGContext *s,
383 811d4cf4 balrog
                int cond, int opc0, int opc1, int rd0, int rd1,
384 811d4cf4 balrog
                int rn0, int rn1, int rm0, int rm1, int shift)
385 811d4cf4 balrog
{
386 0c9c3a9e balrog
    if (rd0 == rn1 || rd0 == rm1) {
387 0c9c3a9e balrog
        tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
388 0c9c3a9e balrog
                        (rn0 << 16) | (8 << 12) | shift | rm0);
389 0c9c3a9e balrog
        tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
390 0c9c3a9e balrog
                        (rn1 << 16) | (rd1 << 12) | shift | rm1);
391 0c9c3a9e balrog
        tcg_out_dat_reg(s, cond, ARITH_MOV,
392 0c9c3a9e balrog
                        rd0, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
393 0c9c3a9e balrog
    } else {
394 0c9c3a9e balrog
        tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
395 0c9c3a9e balrog
                        (rn0 << 16) | (rd0 << 12) | shift | rm0);
396 0c9c3a9e balrog
        tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
397 0c9c3a9e balrog
                        (rn1 << 16) | (rd1 << 12) | shift | rm1);
398 0c9c3a9e balrog
    }
399 811d4cf4 balrog
}
400 811d4cf4 balrog
401 811d4cf4 balrog
static inline void tcg_out_dat_imm(TCGContext *s,
402 811d4cf4 balrog
                int cond, int opc, int rd, int rn, int im)
403 811d4cf4 balrog
{
404 3979144c pbrook
    tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |
405 811d4cf4 balrog
                    (rn << 16) | (rd << 12) | im);
406 811d4cf4 balrog
}
407 811d4cf4 balrog
408 811d4cf4 balrog
static inline void tcg_out_movi32(TCGContext *s,
409 811d4cf4 balrog
                int cond, int rd, int32_t arg)
410 811d4cf4 balrog
{
411 811d4cf4 balrog
    /* TODO: This is very suboptimal, we can easily have a constant
412 811d4cf4 balrog
     * pool somewhere after all the instructions.  */
413 811d4cf4 balrog
414 811d4cf4 balrog
    if (arg < 0 && arg > -0x100)
415 811d4cf4 balrog
        return tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, (~arg) & 0xff);
416 811d4cf4 balrog
417 ac34fb5c Aurelien Jarno
    if (use_armv7_instructions) {
418 ac34fb5c Aurelien Jarno
        /* use movw/movt */
419 ac34fb5c Aurelien Jarno
        /* movw */
420 ac34fb5c Aurelien Jarno
        tcg_out32(s, (cond << 28) | 0x03000000 | (rd << 12)
421 ac34fb5c Aurelien Jarno
                  | ((arg << 4) & 0x000f0000) | (arg & 0xfff));
422 ac34fb5c Aurelien Jarno
        if (arg & 0xffff0000)
423 ac34fb5c Aurelien Jarno
            /* movt */
424 ac34fb5c Aurelien Jarno
            tcg_out32(s, (cond << 28) | 0x03400000 | (rd << 12)
425 ac34fb5c Aurelien Jarno
                      | ((arg >> 12) & 0x000f0000) | ((arg >> 16) & 0xfff));
426 ac34fb5c Aurelien Jarno
    } else {
427 ac34fb5c Aurelien Jarno
        tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, arg & 0xff);
428 ac34fb5c Aurelien Jarno
        if (arg & 0x0000ff00)
429 ac34fb5c Aurelien Jarno
            tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
430 ac34fb5c Aurelien Jarno
                            ((arg >>  8) & 0xff) | 0xc00);
431 ac34fb5c Aurelien Jarno
        if (arg & 0x00ff0000)
432 ac34fb5c Aurelien Jarno
            tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
433 ac34fb5c Aurelien Jarno
                            ((arg >> 16) & 0xff) | 0x800);
434 ac34fb5c Aurelien Jarno
        if (arg & 0xff000000)
435 ac34fb5c Aurelien Jarno
            tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
436 ac34fb5c Aurelien Jarno
                            ((arg >> 24) & 0xff) | 0x400);
437 ac34fb5c Aurelien Jarno
        }
438 811d4cf4 balrog
}
439 811d4cf4 balrog
440 811d4cf4 balrog
static inline void tcg_out_mul32(TCGContext *s,
441 811d4cf4 balrog
                int cond, int rd, int rs, int rm)
442 811d4cf4 balrog
{
443 811d4cf4 balrog
    if (rd != rm)
444 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
445 811d4cf4 balrog
                        (rs << 8) | 0x90 | rm);
446 811d4cf4 balrog
    else if (rd != rs)
447 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
448 811d4cf4 balrog
                        (rm << 8) | 0x90 | rs);
449 811d4cf4 balrog
    else {
450 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | ( 8 << 16) | (0 << 12) |
451 811d4cf4 balrog
                        (rs << 8) | 0x90 | rm);
452 811d4cf4 balrog
        tcg_out_dat_reg(s, cond, ARITH_MOV,
453 c8d80cef Aurelien Jarno
                        rd, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
454 811d4cf4 balrog
    }
455 811d4cf4 balrog
}
456 811d4cf4 balrog
457 811d4cf4 balrog
static inline void tcg_out_umull32(TCGContext *s,
458 811d4cf4 balrog
                int cond, int rd0, int rd1, int rs, int rm)
459 811d4cf4 balrog
{
460 811d4cf4 balrog
    if (rd0 != rm && rd1 != rm)
461 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x800090 |
462 811d4cf4 balrog
                        (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
463 811d4cf4 balrog
    else if (rd0 != rs && rd1 != rs)
464 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x800090 |
465 811d4cf4 balrog
                        (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
466 811d4cf4 balrog
    else {
467 811d4cf4 balrog
        tcg_out_dat_reg(s, cond, ARITH_MOV,
468 811d4cf4 balrog
                        TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
469 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x800098 |
470 811d4cf4 balrog
                        (rd1 << 16) | (rd0 << 12) | (rs << 8));
471 811d4cf4 balrog
    }
472 811d4cf4 balrog
}
473 811d4cf4 balrog
474 811d4cf4 balrog
static inline void tcg_out_smull32(TCGContext *s,
475 811d4cf4 balrog
                int cond, int rd0, int rd1, int rs, int rm)
476 811d4cf4 balrog
{
477 811d4cf4 balrog
    if (rd0 != rm && rd1 != rm)
478 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0xc00090 |
479 811d4cf4 balrog
                        (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
480 811d4cf4 balrog
    else if (rd0 != rs && rd1 != rs)
481 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0xc00090 |
482 811d4cf4 balrog
                        (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
483 811d4cf4 balrog
    else {
484 811d4cf4 balrog
        tcg_out_dat_reg(s, cond, ARITH_MOV,
485 811d4cf4 balrog
                        TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
486 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0xc00098 |
487 811d4cf4 balrog
                        (rd1 << 16) | (rd0 << 12) | (rs << 8));
488 811d4cf4 balrog
    }
489 811d4cf4 balrog
}
490 811d4cf4 balrog
491 9517094f Aurelien Jarno
static inline void tcg_out_ext8s(TCGContext *s, int cond,
492 9517094f Aurelien Jarno
                                 int rd, int rn)
493 9517094f Aurelien Jarno
{
494 9517094f Aurelien Jarno
    if (use_armv6_instructions) {
495 9517094f Aurelien Jarno
        /* sxtb */
496 9517094f Aurelien Jarno
        tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn);
497 9517094f Aurelien Jarno
    } else {
498 e23886a9 Aurelien Jarno
        tcg_out_dat_reg(s, cond, ARITH_MOV,
499 9517094f Aurelien Jarno
                        rd, 0, rn, SHIFT_IMM_LSL(24));
500 e23886a9 Aurelien Jarno
        tcg_out_dat_reg(s, cond, ARITH_MOV,
501 9517094f Aurelien Jarno
                        rd, 0, rd, SHIFT_IMM_ASR(24));
502 9517094f Aurelien Jarno
    }
503 9517094f Aurelien Jarno
}
504 9517094f Aurelien Jarno
505 e854b6d3 Aurelien Jarno
static inline void tcg_out_ext8u(TCGContext *s, int cond,
506 e854b6d3 Aurelien Jarno
                                 int rd, int rn)
507 e854b6d3 Aurelien Jarno
{
508 e854b6d3 Aurelien Jarno
    tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff);
509 e854b6d3 Aurelien Jarno
}
510 e854b6d3 Aurelien Jarno
511 9517094f Aurelien Jarno
static inline void tcg_out_ext16s(TCGContext *s, int cond,
512 9517094f Aurelien Jarno
                                  int rd, int rn)
513 9517094f Aurelien Jarno
{
514 9517094f Aurelien Jarno
    if (use_armv6_instructions) {
515 9517094f Aurelien Jarno
        /* sxth */
516 9517094f Aurelien Jarno
        tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn);
517 9517094f Aurelien Jarno
    } else {
518 e23886a9 Aurelien Jarno
        tcg_out_dat_reg(s, cond, ARITH_MOV,
519 9517094f Aurelien Jarno
                        rd, 0, rn, SHIFT_IMM_LSL(16));
520 e23886a9 Aurelien Jarno
        tcg_out_dat_reg(s, cond, ARITH_MOV,
521 9517094f Aurelien Jarno
                        rd, 0, rd, SHIFT_IMM_ASR(16));
522 9517094f Aurelien Jarno
    }
523 9517094f Aurelien Jarno
}
524 9517094f Aurelien Jarno
525 9517094f Aurelien Jarno
static inline void tcg_out_ext16u(TCGContext *s, int cond,
526 9517094f Aurelien Jarno
                                  int rd, int rn)
527 9517094f Aurelien Jarno
{
528 9517094f Aurelien Jarno
    if (use_armv6_instructions) {
529 9517094f Aurelien Jarno
        /* uxth */
530 9517094f Aurelien Jarno
        tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn);
531 9517094f Aurelien Jarno
    } else {
532 e23886a9 Aurelien Jarno
        tcg_out_dat_reg(s, cond, ARITH_MOV,
533 9517094f Aurelien Jarno
                        rd, 0, rn, SHIFT_IMM_LSL(16));
534 e23886a9 Aurelien Jarno
        tcg_out_dat_reg(s, cond, ARITH_MOV,
535 9517094f Aurelien Jarno
                        rd, 0, rd, SHIFT_IMM_LSR(16));
536 9517094f Aurelien Jarno
    }
537 9517094f Aurelien Jarno
}
538 9517094f Aurelien Jarno
539 67dcab73 Aurelien Jarno
static inline void tcg_out_bswap16s(TCGContext *s, int cond, int rd, int rn)
540 67dcab73 Aurelien Jarno
{
541 67dcab73 Aurelien Jarno
    if (use_armv6_instructions) {
542 67dcab73 Aurelien Jarno
        /* revsh */
543 67dcab73 Aurelien Jarno
        tcg_out32(s, 0x06ff0fb0 | (cond << 28) | (rd << 12) | rn);
544 67dcab73 Aurelien Jarno
    } else {
545 67dcab73 Aurelien Jarno
        tcg_out_dat_reg(s, cond, ARITH_MOV,
546 67dcab73 Aurelien Jarno
                        TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24));
547 67dcab73 Aurelien Jarno
        tcg_out_dat_reg(s, cond, ARITH_MOV,
548 67dcab73 Aurelien Jarno
                        TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_ASR(16));
549 67dcab73 Aurelien Jarno
        tcg_out_dat_reg(s, cond, ARITH_ORR,
550 67dcab73 Aurelien Jarno
                        rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8));
551 67dcab73 Aurelien Jarno
    }
552 67dcab73 Aurelien Jarno
}
553 67dcab73 Aurelien Jarno
554 244b1e81 Aurelien Jarno
static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn)
555 244b1e81 Aurelien Jarno
{
556 244b1e81 Aurelien Jarno
    if (use_armv6_instructions) {
557 244b1e81 Aurelien Jarno
        /* rev16 */
558 244b1e81 Aurelien Jarno
        tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn);
559 244b1e81 Aurelien Jarno
    } else {
560 244b1e81 Aurelien Jarno
        tcg_out_dat_reg(s, cond, ARITH_MOV,
561 244b1e81 Aurelien Jarno
                        TCG_REG_R8, 0, rn, SHIFT_IMM_LSL(24));
562 244b1e81 Aurelien Jarno
        tcg_out_dat_reg(s, cond, ARITH_MOV,
563 244b1e81 Aurelien Jarno
                        TCG_REG_R8, 0, TCG_REG_R8, SHIFT_IMM_LSR(16));
564 244b1e81 Aurelien Jarno
        tcg_out_dat_reg(s, cond, ARITH_ORR,
565 244b1e81 Aurelien Jarno
                        rd, TCG_REG_R8, rn, SHIFT_IMM_LSR(8));
566 244b1e81 Aurelien Jarno
    }
567 244b1e81 Aurelien Jarno
}
568 244b1e81 Aurelien Jarno
569 244b1e81 Aurelien Jarno
static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn)
570 244b1e81 Aurelien Jarno
{
571 244b1e81 Aurelien Jarno
    if (use_armv6_instructions) {
572 244b1e81 Aurelien Jarno
        /* rev */
573 244b1e81 Aurelien Jarno
        tcg_out32(s, 0x06bf0f30 | (cond << 28) | (rd << 12) | rn);
574 244b1e81 Aurelien Jarno
    } else {
575 244b1e81 Aurelien Jarno
        tcg_out_dat_reg(s, cond, ARITH_EOR,
576 244b1e81 Aurelien Jarno
                        TCG_REG_R8, rn, rn, SHIFT_IMM_ROR(16));
577 244b1e81 Aurelien Jarno
        tcg_out_dat_imm(s, cond, ARITH_BIC,
578 244b1e81 Aurelien Jarno
                        TCG_REG_R8, TCG_REG_R8, 0xff | 0x800);
579 244b1e81 Aurelien Jarno
        tcg_out_dat_reg(s, cond, ARITH_MOV,
580 244b1e81 Aurelien Jarno
                        rd, 0, rn, SHIFT_IMM_ROR(8));
581 244b1e81 Aurelien Jarno
        tcg_out_dat_reg(s, cond, ARITH_EOR,
582 244b1e81 Aurelien Jarno
                        rd, rd, TCG_REG_R8, SHIFT_IMM_LSR(8));
583 244b1e81 Aurelien Jarno
    }
584 244b1e81 Aurelien Jarno
}
585 244b1e81 Aurelien Jarno
586 811d4cf4 balrog
static inline void tcg_out_ld32_12(TCGContext *s, int cond,
587 811d4cf4 balrog
                int rd, int rn, tcg_target_long im)
588 811d4cf4 balrog
{
589 811d4cf4 balrog
    if (im >= 0)
590 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x05900000 |
591 811d4cf4 balrog
                        (rn << 16) | (rd << 12) | (im & 0xfff));
592 811d4cf4 balrog
    else
593 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x05100000 |
594 811d4cf4 balrog
                        (rn << 16) | (rd << 12) | ((-im) & 0xfff));
595 811d4cf4 balrog
}
596 811d4cf4 balrog
597 811d4cf4 balrog
static inline void tcg_out_st32_12(TCGContext *s, int cond,
598 811d4cf4 balrog
                int rd, int rn, tcg_target_long im)
599 811d4cf4 balrog
{
600 811d4cf4 balrog
    if (im >= 0)
601 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x05800000 |
602 811d4cf4 balrog
                        (rn << 16) | (rd << 12) | (im & 0xfff));
603 811d4cf4 balrog
    else
604 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x05000000 |
605 811d4cf4 balrog
                        (rn << 16) | (rd << 12) | ((-im) & 0xfff));
606 811d4cf4 balrog
}
607 811d4cf4 balrog
608 811d4cf4 balrog
static inline void tcg_out_ld32_r(TCGContext *s, int cond,
609 811d4cf4 balrog
                int rd, int rn, int rm)
610 811d4cf4 balrog
{
611 811d4cf4 balrog
    tcg_out32(s, (cond << 28) | 0x07900000 |
612 811d4cf4 balrog
                    (rn << 16) | (rd << 12) | rm);
613 811d4cf4 balrog
}
614 811d4cf4 balrog
615 811d4cf4 balrog
static inline void tcg_out_st32_r(TCGContext *s, int cond,
616 811d4cf4 balrog
                int rd, int rn, int rm)
617 811d4cf4 balrog
{
618 811d4cf4 balrog
    tcg_out32(s, (cond << 28) | 0x07800000 |
619 811d4cf4 balrog
                    (rn << 16) | (rd << 12) | rm);
620 811d4cf4 balrog
}
621 811d4cf4 balrog
622 3979144c pbrook
/* Register pre-increment with base writeback.  */
623 3979144c pbrook
static inline void tcg_out_ld32_rwb(TCGContext *s, int cond,
624 3979144c pbrook
                int rd, int rn, int rm)
625 3979144c pbrook
{
626 3979144c pbrook
    tcg_out32(s, (cond << 28) | 0x07b00000 |
627 3979144c pbrook
                    (rn << 16) | (rd << 12) | rm);
628 3979144c pbrook
}
629 3979144c pbrook
630 3979144c pbrook
static inline void tcg_out_st32_rwb(TCGContext *s, int cond,
631 3979144c pbrook
                int rd, int rn, int rm)
632 3979144c pbrook
{
633 3979144c pbrook
    tcg_out32(s, (cond << 28) | 0x07a00000 |
634 3979144c pbrook
                    (rn << 16) | (rd << 12) | rm);
635 3979144c pbrook
}
636 3979144c pbrook
637 811d4cf4 balrog
static inline void tcg_out_ld16u_8(TCGContext *s, int cond,
638 811d4cf4 balrog
                int rd, int rn, tcg_target_long im)
639 811d4cf4 balrog
{
640 811d4cf4 balrog
    if (im >= 0)
641 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x01d000b0 |
642 811d4cf4 balrog
                        (rn << 16) | (rd << 12) |
643 811d4cf4 balrog
                        ((im & 0xf0) << 4) | (im & 0xf));
644 811d4cf4 balrog
    else
645 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x015000b0 |
646 811d4cf4 balrog
                        (rn << 16) | (rd << 12) |
647 811d4cf4 balrog
                        (((-im) & 0xf0) << 4) | ((-im) & 0xf));
648 811d4cf4 balrog
}
649 811d4cf4 balrog
650 f694a27e Aurelien Jarno
static inline void tcg_out_st16_8(TCGContext *s, int cond,
651 811d4cf4 balrog
                int rd, int rn, tcg_target_long im)
652 811d4cf4 balrog
{
653 811d4cf4 balrog
    if (im >= 0)
654 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x01c000b0 |
655 811d4cf4 balrog
                        (rn << 16) | (rd << 12) |
656 811d4cf4 balrog
                        ((im & 0xf0) << 4) | (im & 0xf));
657 811d4cf4 balrog
    else
658 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x014000b0 |
659 811d4cf4 balrog
                        (rn << 16) | (rd << 12) |
660 811d4cf4 balrog
                        (((-im) & 0xf0) << 4) | ((-im) & 0xf));
661 811d4cf4 balrog
}
662 811d4cf4 balrog
663 811d4cf4 balrog
static inline void tcg_out_ld16u_r(TCGContext *s, int cond,
664 811d4cf4 balrog
                int rd, int rn, int rm)
665 811d4cf4 balrog
{
666 811d4cf4 balrog
    tcg_out32(s, (cond << 28) | 0x019000b0 |
667 811d4cf4 balrog
                    (rn << 16) | (rd << 12) | rm);
668 811d4cf4 balrog
}
669 811d4cf4 balrog
670 f694a27e Aurelien Jarno
static inline void tcg_out_st16_r(TCGContext *s, int cond,
671 811d4cf4 balrog
                int rd, int rn, int rm)
672 811d4cf4 balrog
{
673 811d4cf4 balrog
    tcg_out32(s, (cond << 28) | 0x018000b0 |
674 811d4cf4 balrog
                    (rn << 16) | (rd << 12) | rm);
675 811d4cf4 balrog
}
676 811d4cf4 balrog
677 811d4cf4 balrog
static inline void tcg_out_ld16s_8(TCGContext *s, int cond,
678 811d4cf4 balrog
                int rd, int rn, tcg_target_long im)
679 811d4cf4 balrog
{
680 811d4cf4 balrog
    if (im >= 0)
681 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x01d000f0 |
682 811d4cf4 balrog
                        (rn << 16) | (rd << 12) |
683 811d4cf4 balrog
                        ((im & 0xf0) << 4) | (im & 0xf));
684 811d4cf4 balrog
    else
685 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x015000f0 |
686 811d4cf4 balrog
                        (rn << 16) | (rd << 12) |
687 811d4cf4 balrog
                        (((-im) & 0xf0) << 4) | ((-im) & 0xf));
688 811d4cf4 balrog
}
689 811d4cf4 balrog
690 811d4cf4 balrog
static inline void tcg_out_ld16s_r(TCGContext *s, int cond,
691 811d4cf4 balrog
                int rd, int rn, int rm)
692 811d4cf4 balrog
{
693 811d4cf4 balrog
    tcg_out32(s, (cond << 28) | 0x019000f0 |
694 811d4cf4 balrog
                    (rn << 16) | (rd << 12) | rm);
695 811d4cf4 balrog
}
696 811d4cf4 balrog
697 811d4cf4 balrog
static inline void tcg_out_ld8_12(TCGContext *s, int cond,
698 811d4cf4 balrog
                int rd, int rn, tcg_target_long im)
699 811d4cf4 balrog
{
700 811d4cf4 balrog
    if (im >= 0)
701 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x05d00000 |
702 811d4cf4 balrog
                        (rn << 16) | (rd << 12) | (im & 0xfff));
703 811d4cf4 balrog
    else
704 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x05500000 |
705 811d4cf4 balrog
                        (rn << 16) | (rd << 12) | ((-im) & 0xfff));
706 811d4cf4 balrog
}
707 811d4cf4 balrog
708 811d4cf4 balrog
static inline void tcg_out_st8_12(TCGContext *s, int cond,
709 811d4cf4 balrog
                int rd, int rn, tcg_target_long im)
710 811d4cf4 balrog
{
711 811d4cf4 balrog
    if (im >= 0)
712 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x05c00000 |
713 811d4cf4 balrog
                        (rn << 16) | (rd << 12) | (im & 0xfff));
714 811d4cf4 balrog
    else
715 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x05400000 |
716 811d4cf4 balrog
                        (rn << 16) | (rd << 12) | ((-im) & 0xfff));
717 811d4cf4 balrog
}
718 811d4cf4 balrog
719 811d4cf4 balrog
static inline void tcg_out_ld8_r(TCGContext *s, int cond,
720 811d4cf4 balrog
                int rd, int rn, int rm)
721 811d4cf4 balrog
{
722 811d4cf4 balrog
    tcg_out32(s, (cond << 28) | 0x07d00000 |
723 811d4cf4 balrog
                    (rn << 16) | (rd << 12) | rm);
724 811d4cf4 balrog
}
725 811d4cf4 balrog
726 811d4cf4 balrog
static inline void tcg_out_st8_r(TCGContext *s, int cond,
727 811d4cf4 balrog
                int rd, int rn, int rm)
728 811d4cf4 balrog
{
729 811d4cf4 balrog
    tcg_out32(s, (cond << 28) | 0x07c00000 |
730 811d4cf4 balrog
                    (rn << 16) | (rd << 12) | rm);
731 811d4cf4 balrog
}
732 811d4cf4 balrog
733 811d4cf4 balrog
static inline void tcg_out_ld8s_8(TCGContext *s, int cond,
734 811d4cf4 balrog
                int rd, int rn, tcg_target_long im)
735 811d4cf4 balrog
{
736 811d4cf4 balrog
    if (im >= 0)
737 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x01d000d0 |
738 811d4cf4 balrog
                        (rn << 16) | (rd << 12) |
739 811d4cf4 balrog
                        ((im & 0xf0) << 4) | (im & 0xf));
740 811d4cf4 balrog
    else
741 811d4cf4 balrog
        tcg_out32(s, (cond << 28) | 0x015000d0 |
742 811d4cf4 balrog
                        (rn << 16) | (rd << 12) |
743 811d4cf4 balrog
                        (((-im) & 0xf0) << 4) | ((-im) & 0xf));
744 811d4cf4 balrog
}
745 811d4cf4 balrog
746 811d4cf4 balrog
static inline void tcg_out_ld8s_r(TCGContext *s, int cond,
747 811d4cf4 balrog
                int rd, int rn, int rm)
748 811d4cf4 balrog
{
749 204c1674 balrog
    tcg_out32(s, (cond << 28) | 0x019000d0 |
750 811d4cf4 balrog
                    (rn << 16) | (rd << 12) | rm);
751 811d4cf4 balrog
}
752 811d4cf4 balrog
753 811d4cf4 balrog
static inline void tcg_out_ld32u(TCGContext *s, int cond,
754 811d4cf4 balrog
                int rd, int rn, int32_t offset)
755 811d4cf4 balrog
{
756 811d4cf4 balrog
    if (offset > 0xfff || offset < -0xfff) {
757 811d4cf4 balrog
        tcg_out_movi32(s, cond, TCG_REG_R8, offset);
758 811d4cf4 balrog
        tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_R8);
759 811d4cf4 balrog
    } else
760 811d4cf4 balrog
        tcg_out_ld32_12(s, cond, rd, rn, offset);
761 811d4cf4 balrog
}
762 811d4cf4 balrog
763 811d4cf4 balrog
static inline void tcg_out_st32(TCGContext *s, int cond,
764 811d4cf4 balrog
                int rd, int rn, int32_t offset)
765 811d4cf4 balrog
{
766 811d4cf4 balrog
    if (offset > 0xfff || offset < -0xfff) {
767 811d4cf4 balrog
        tcg_out_movi32(s, cond, TCG_REG_R8, offset);
768 811d4cf4 balrog
        tcg_out_st32_r(s, cond, rd, rn, TCG_REG_R8);
769 811d4cf4 balrog
    } else
770 811d4cf4 balrog
        tcg_out_st32_12(s, cond, rd, rn, offset);
771 811d4cf4 balrog
}
772 811d4cf4 balrog
773 811d4cf4 balrog
static inline void tcg_out_ld16u(TCGContext *s, int cond,
774 811d4cf4 balrog
                int rd, int rn, int32_t offset)
775 811d4cf4 balrog
{
776 811d4cf4 balrog
    if (offset > 0xff || offset < -0xff) {
777 811d4cf4 balrog
        tcg_out_movi32(s, cond, TCG_REG_R8, offset);
778 811d4cf4 balrog
        tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_R8);
779 811d4cf4 balrog
    } else
780 811d4cf4 balrog
        tcg_out_ld16u_8(s, cond, rd, rn, offset);
781 811d4cf4 balrog
}
782 811d4cf4 balrog
783 811d4cf4 balrog
static inline void tcg_out_ld16s(TCGContext *s, int cond,
784 811d4cf4 balrog
                int rd, int rn, int32_t offset)
785 811d4cf4 balrog
{
786 811d4cf4 balrog
    if (offset > 0xff || offset < -0xff) {
787 811d4cf4 balrog
        tcg_out_movi32(s, cond, TCG_REG_R8, offset);
788 811d4cf4 balrog
        tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_R8);
789 811d4cf4 balrog
    } else
790 811d4cf4 balrog
        tcg_out_ld16s_8(s, cond, rd, rn, offset);
791 811d4cf4 balrog
}
792 811d4cf4 balrog
793 f694a27e Aurelien Jarno
static inline void tcg_out_st16(TCGContext *s, int cond,
794 811d4cf4 balrog
                int rd, int rn, int32_t offset)
795 811d4cf4 balrog
{
796 811d4cf4 balrog
    if (offset > 0xff || offset < -0xff) {
797 811d4cf4 balrog
        tcg_out_movi32(s, cond, TCG_REG_R8, offset);
798 f694a27e Aurelien Jarno
        tcg_out_st16_r(s, cond, rd, rn, TCG_REG_R8);
799 811d4cf4 balrog
    } else
800 f694a27e Aurelien Jarno
        tcg_out_st16_8(s, cond, rd, rn, offset);
801 811d4cf4 balrog
}
802 811d4cf4 balrog
803 811d4cf4 balrog
static inline void tcg_out_ld8u(TCGContext *s, int cond,
804 811d4cf4 balrog
                int rd, int rn, int32_t offset)
805 811d4cf4 balrog
{
806 811d4cf4 balrog
    if (offset > 0xfff || offset < -0xfff) {
807 811d4cf4 balrog
        tcg_out_movi32(s, cond, TCG_REG_R8, offset);
808 811d4cf4 balrog
        tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_R8);
809 811d4cf4 balrog
    } else
810 811d4cf4 balrog
        tcg_out_ld8_12(s, cond, rd, rn, offset);
811 811d4cf4 balrog
}
812 811d4cf4 balrog
813 811d4cf4 balrog
static inline void tcg_out_ld8s(TCGContext *s, int cond,
814 811d4cf4 balrog
                int rd, int rn, int32_t offset)
815 811d4cf4 balrog
{
816 811d4cf4 balrog
    if (offset > 0xff || offset < -0xff) {
817 811d4cf4 balrog
        tcg_out_movi32(s, cond, TCG_REG_R8, offset);
818 811d4cf4 balrog
        tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_R8);
819 811d4cf4 balrog
    } else
820 811d4cf4 balrog
        tcg_out_ld8s_8(s, cond, rd, rn, offset);
821 811d4cf4 balrog
}
822 811d4cf4 balrog
823 f694a27e Aurelien Jarno
static inline void tcg_out_st8(TCGContext *s, int cond,
824 811d4cf4 balrog
                int rd, int rn, int32_t offset)
825 811d4cf4 balrog
{
826 811d4cf4 balrog
    if (offset > 0xfff || offset < -0xfff) {
827 811d4cf4 balrog
        tcg_out_movi32(s, cond, TCG_REG_R8, offset);
828 811d4cf4 balrog
        tcg_out_st8_r(s, cond, rd, rn, TCG_REG_R8);
829 811d4cf4 balrog
    } else
830 811d4cf4 balrog
        tcg_out_st8_12(s, cond, rd, rn, offset);
831 811d4cf4 balrog
}
832 811d4cf4 balrog
833 811d4cf4 balrog
static inline void tcg_out_goto(TCGContext *s, int cond, uint32_t addr)
834 811d4cf4 balrog
{
835 811d4cf4 balrog
    int32_t val;
836 811d4cf4 balrog
837 811d4cf4 balrog
    val = addr - (tcg_target_long) s->code_ptr;
838 811d4cf4 balrog
    if (val - 8 < 0x01fffffd && val - 8 > -0x01fffffd)
839 811d4cf4 balrog
        tcg_out_b(s, cond, val);
840 811d4cf4 balrog
    else {
841 811d4cf4 balrog
#if 1
842 811d4cf4 balrog
        tcg_abort();
843 811d4cf4 balrog
#else
844 811d4cf4 balrog
        if (cond == COND_AL) {
845 c8d80cef Aurelien Jarno
            tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
846 811d4cf4 balrog
            tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
847 811d4cf4 balrog
        } else {
848 811d4cf4 balrog
            tcg_out_movi32(s, cond, TCG_REG_R8, val - 8);
849 811d4cf4 balrog
            tcg_out_dat_reg(s, cond, ARITH_ADD,
850 c8d80cef Aurelien Jarno
                            TCG_REG_PC, TCG_REG_PC,
851 c8d80cef Aurelien Jarno
                            TCG_REG_R8, SHIFT_IMM_LSL(0));
852 811d4cf4 balrog
        }
853 811d4cf4 balrog
#endif
854 811d4cf4 balrog
    }
855 811d4cf4 balrog
}
856 811d4cf4 balrog
857 811d4cf4 balrog
static inline void tcg_out_call(TCGContext *s, int cond, uint32_t addr)
858 811d4cf4 balrog
{
859 811d4cf4 balrog
    int32_t val;
860 811d4cf4 balrog
861 811d4cf4 balrog
    val = addr - (tcg_target_long) s->code_ptr;
862 811d4cf4 balrog
    if (val < 0x01fffffd && val > -0x01fffffd)
863 811d4cf4 balrog
        tcg_out_bl(s, cond, val);
864 811d4cf4 balrog
    else {
865 811d4cf4 balrog
#if 1
866 811d4cf4 balrog
        tcg_abort();
867 811d4cf4 balrog
#else
868 811d4cf4 balrog
        if (cond == COND_AL) {
869 c8d80cef Aurelien Jarno
            tcg_out_dat_imm(s, cond, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 4);
870 c8d80cef Aurelien Jarno
            tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
871 811d4cf4 balrog
            tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
872 811d4cf4 balrog
        } else {
873 811d4cf4 balrog
            tcg_out_movi32(s, cond, TCG_REG_R9, addr);
874 c8d80cef Aurelien Jarno
            tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R14, 0,
875 c8d80cef Aurelien Jarno
                            TCG_REG_PC, SHIFT_IMM_LSL(0));
876 811d4cf4 balrog
            tcg_out_bx(s, cond, TCG_REG_R9);
877 811d4cf4 balrog
        }
878 811d4cf4 balrog
#endif
879 811d4cf4 balrog
    }
880 811d4cf4 balrog
}
881 811d4cf4 balrog
882 811d4cf4 balrog
static inline void tcg_out_callr(TCGContext *s, int cond, int arg)
883 811d4cf4 balrog
{
884 23401b58 Aurelien Jarno
    if (use_armv5_instructions) {
885 23401b58 Aurelien Jarno
        tcg_out_blx(s, cond, arg);
886 23401b58 Aurelien Jarno
    } else {
887 23401b58 Aurelien Jarno
        tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R14, 0,
888 23401b58 Aurelien Jarno
                        TCG_REG_PC, SHIFT_IMM_LSL(0));
889 23401b58 Aurelien Jarno
        tcg_out_bx(s, cond, arg);
890 23401b58 Aurelien Jarno
    }
891 811d4cf4 balrog
}
892 811d4cf4 balrog
893 811d4cf4 balrog
static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
894 811d4cf4 balrog
{
895 811d4cf4 balrog
    TCGLabel *l = &s->labels[label_index];
896 811d4cf4 balrog
897 811d4cf4 balrog
    if (l->has_value)
898 811d4cf4 balrog
        tcg_out_goto(s, cond, l->u.value);
899 811d4cf4 balrog
    else if (cond == COND_AL) {
900 c8d80cef Aurelien Jarno
        tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
901 811d4cf4 balrog
        tcg_out_reloc(s, s->code_ptr, R_ARM_ABS32, label_index, 31337);
902 811d4cf4 balrog
        s->code_ptr += 4;
903 811d4cf4 balrog
    } else {
904 811d4cf4 balrog
        /* Probably this should be preferred even for COND_AL... */
905 811d4cf4 balrog
        tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, label_index, 31337);
906 e936243a balrog
        tcg_out_b_noaddr(s, cond);
907 811d4cf4 balrog
    }
908 811d4cf4 balrog
}
909 811d4cf4 balrog
910 811d4cf4 balrog
#ifdef CONFIG_SOFTMMU
911 79383c9c blueswir1
912 79383c9c blueswir1
#include "../../softmmu_defs.h"
913 811d4cf4 balrog
914 811d4cf4 balrog
static void *qemu_ld_helpers[4] = {
915 811d4cf4 balrog
    __ldb_mmu,
916 811d4cf4 balrog
    __ldw_mmu,
917 811d4cf4 balrog
    __ldl_mmu,
918 811d4cf4 balrog
    __ldq_mmu,
919 811d4cf4 balrog
};
920 811d4cf4 balrog
921 811d4cf4 balrog
static void *qemu_st_helpers[4] = {
922 811d4cf4 balrog
    __stb_mmu,
923 811d4cf4 balrog
    __stw_mmu,
924 811d4cf4 balrog
    __stl_mmu,
925 811d4cf4 balrog
    __stq_mmu,
926 811d4cf4 balrog
};
927 811d4cf4 balrog
#endif
928 811d4cf4 balrog
929 3979144c pbrook
#define TLB_SHIFT        (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
930 3979144c pbrook
931 7e0d9562 Aurelien Jarno
static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
932 811d4cf4 balrog
{
933 67dcab73 Aurelien Jarno
    int addr_reg, data_reg, data_reg2, bswap;
934 811d4cf4 balrog
#ifdef CONFIG_SOFTMMU
935 811d4cf4 balrog
    int mem_index, s_bits;
936 811d4cf4 balrog
# if TARGET_LONG_BITS == 64
937 811d4cf4 balrog
    int addr_reg2;
938 811d4cf4 balrog
# endif
939 811d4cf4 balrog
    uint32_t *label_ptr;
940 811d4cf4 balrog
#endif
941 811d4cf4 balrog
942 67dcab73 Aurelien Jarno
#ifdef TARGET_WORDS_BIGENDIAN
943 67dcab73 Aurelien Jarno
    bswap = 1;
944 67dcab73 Aurelien Jarno
#else
945 67dcab73 Aurelien Jarno
    bswap = 0;
946 67dcab73 Aurelien Jarno
#endif
947 811d4cf4 balrog
    data_reg = *args++;
948 811d4cf4 balrog
    if (opc == 3)
949 811d4cf4 balrog
        data_reg2 = *args++;
950 811d4cf4 balrog
    else
951 d89c682f Stefan Weil
        data_reg2 = 0; /* suppress warning */
952 811d4cf4 balrog
    addr_reg = *args++;
953 811d4cf4 balrog
#ifdef CONFIG_SOFTMMU
954 aef3a282 balrog
# if TARGET_LONG_BITS == 64
955 aef3a282 balrog
    addr_reg2 = *args++;
956 aef3a282 balrog
# endif
957 811d4cf4 balrog
    mem_index = *args;
958 811d4cf4 balrog
    s_bits = opc & 3;
959 811d4cf4 balrog
960 91a3c1b0 balrog
    /* Should generate something like the following:
961 3979144c pbrook
     *  shr r8, addr_reg, #TARGET_PAGE_BITS
962 91a3c1b0 balrog
     *  and r0, r8, #(CPU_TLB_SIZE - 1)   @ Assumption: CPU_TLB_BITS <= 8
963 3979144c pbrook
     *  add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
964 91a3c1b0 balrog
     */
965 91a3c1b0 balrog
#  if CPU_TLB_BITS > 8
966 91a3c1b0 balrog
#   error
967 91a3c1b0 balrog
#  endif
968 c8d80cef Aurelien Jarno
    tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_R8,
969 c8d80cef Aurelien Jarno
                    0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
970 811d4cf4 balrog
    tcg_out_dat_imm(s, COND_AL, ARITH_AND,
971 c8d80cef Aurelien Jarno
                    TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
972 c8d80cef Aurelien Jarno
    tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0,
973 c8d80cef Aurelien Jarno
                    TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
974 91a3c1b0 balrog
    /* In the
975 91a3c1b0 balrog
     *  ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_read))]
976 91a3c1b0 balrog
     * below, the offset is likely to exceed 12 bits if mem_index != 0 and
977 91a3c1b0 balrog
     * not exceed otherwise, so use an
978 91a3c1b0 balrog
     *  add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
979 91a3c1b0 balrog
     * before.
980 91a3c1b0 balrog
     */
981 225b4376 balrog
    if (mem_index)
982 c8d80cef Aurelien Jarno
        tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
983 225b4376 balrog
                        (mem_index << (TLB_SHIFT & 1)) |
984 225b4376 balrog
                        ((16 - (TLB_SHIFT >> 1)) << 8));
985 c8d80cef Aurelien Jarno
    tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
986 225b4376 balrog
                    offsetof(CPUState, tlb_table[0][0].addr_read));
987 c8d80cef Aurelien Jarno
    tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
988 c8d80cef Aurelien Jarno
                    TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
989 3979144c pbrook
    /* Check alignment.  */
990 3979144c pbrook
    if (s_bits)
991 3979144c pbrook
        tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
992 3979144c pbrook
                        0, addr_reg, (1 << s_bits) - 1);
993 811d4cf4 balrog
#  if TARGET_LONG_BITS == 64
994 811d4cf4 balrog
    /* XXX: possibly we could use a block data load or writeback in
995 811d4cf4 balrog
     * the first access.  */
996 c8d80cef Aurelien Jarno
    tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
997 225b4376 balrog
                    offsetof(CPUState, tlb_table[0][0].addr_read) + 4);
998 c8d80cef Aurelien Jarno
    tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
999 c8d80cef Aurelien Jarno
                    TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
1000 811d4cf4 balrog
#  endif
1001 c8d80cef Aurelien Jarno
    tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
1002 225b4376 balrog
                    offsetof(CPUState, tlb_table[0][0].addend));
1003 811d4cf4 balrog
1004 811d4cf4 balrog
    switch (opc) {
1005 811d4cf4 balrog
    case 0:
1006 c8d80cef Aurelien Jarno
        tcg_out_ld8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1007 811d4cf4 balrog
        break;
1008 811d4cf4 balrog
    case 0 | 4:
1009 c8d80cef Aurelien Jarno
        tcg_out_ld8s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1010 811d4cf4 balrog
        break;
1011 811d4cf4 balrog
    case 1:
1012 c8d80cef Aurelien Jarno
        tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1013 67dcab73 Aurelien Jarno
        if (bswap) {
1014 67dcab73 Aurelien Jarno
            tcg_out_bswap16(s, COND_EQ, data_reg, data_reg);
1015 67dcab73 Aurelien Jarno
        }
1016 811d4cf4 balrog
        break;
1017 811d4cf4 balrog
    case 1 | 4:
1018 67dcab73 Aurelien Jarno
        if (bswap) {
1019 67dcab73 Aurelien Jarno
            tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1020 67dcab73 Aurelien Jarno
            tcg_out_bswap16s(s, COND_EQ, data_reg, data_reg);
1021 67dcab73 Aurelien Jarno
        } else {
1022 67dcab73 Aurelien Jarno
            tcg_out_ld16s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1023 67dcab73 Aurelien Jarno
        }
1024 811d4cf4 balrog
        break;
1025 811d4cf4 balrog
    case 2:
1026 811d4cf4 balrog
    default:
1027 c8d80cef Aurelien Jarno
        tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1028 67dcab73 Aurelien Jarno
        if (bswap) {
1029 67dcab73 Aurelien Jarno
            tcg_out_bswap32(s, COND_EQ, data_reg, data_reg);
1030 67dcab73 Aurelien Jarno
        }
1031 811d4cf4 balrog
        break;
1032 811d4cf4 balrog
    case 3:
1033 67dcab73 Aurelien Jarno
        if (bswap) {
1034 67dcab73 Aurelien Jarno
            tcg_out_ld32_rwb(s, COND_EQ, data_reg2, TCG_REG_R1, addr_reg);
1035 67dcab73 Aurelien Jarno
            tcg_out_ld32_12(s, COND_EQ, data_reg, TCG_REG_R1, 4);
1036 67dcab73 Aurelien Jarno
            tcg_out_bswap32(s, COND_EQ, data_reg2, data_reg2);
1037 67dcab73 Aurelien Jarno
            tcg_out_bswap32(s, COND_EQ, data_reg, data_reg);
1038 67dcab73 Aurelien Jarno
        } else {
1039 67dcab73 Aurelien Jarno
            tcg_out_ld32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
1040 67dcab73 Aurelien Jarno
            tcg_out_ld32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
1041 67dcab73 Aurelien Jarno
        }
1042 811d4cf4 balrog
        break;
1043 811d4cf4 balrog
    }
1044 811d4cf4 balrog
1045 811d4cf4 balrog
    label_ptr = (void *) s->code_ptr;
1046 c69806ab Aurelien Jarno
    tcg_out_b_noaddr(s, COND_EQ);
1047 811d4cf4 balrog
1048 811d4cf4 balrog
    /* TODO: move this code to where the constants pool will be */
1049 c8d80cef Aurelien Jarno
    if (addr_reg != TCG_REG_R0) {
1050 7e0d9562 Aurelien Jarno
        tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1051 c8d80cef Aurelien Jarno
                        TCG_REG_R0, 0, addr_reg, SHIFT_IMM_LSL(0));
1052 c8d80cef Aurelien Jarno
    }
1053 811d4cf4 balrog
# if TARGET_LONG_BITS == 32
1054 7e0d9562 Aurelien Jarno
    tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R1, 0, mem_index);
1055 811d4cf4 balrog
# else
1056 2633a2d0 Aurelien Jarno
    tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1057 2633a2d0 Aurelien Jarno
                    TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0));
1058 7e0d9562 Aurelien Jarno
    tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
1059 811d4cf4 balrog
# endif
1060 7e0d9562 Aurelien Jarno
    tcg_out_bl(s, COND_AL, (tcg_target_long) qemu_ld_helpers[s_bits] -
1061 811d4cf4 balrog
                    (tcg_target_long) s->code_ptr);
1062 811d4cf4 balrog
1063 811d4cf4 balrog
    switch (opc) {
1064 811d4cf4 balrog
    case 0 | 4:
1065 e854b6d3 Aurelien Jarno
        tcg_out_ext8s(s, COND_AL, data_reg, TCG_REG_R0);
1066 811d4cf4 balrog
        break;
1067 811d4cf4 balrog
    case 1 | 4:
1068 e854b6d3 Aurelien Jarno
        tcg_out_ext16s(s, COND_AL, data_reg, TCG_REG_R0);
1069 811d4cf4 balrog
        break;
1070 811d4cf4 balrog
    case 0:
1071 811d4cf4 balrog
    case 1:
1072 811d4cf4 balrog
    case 2:
1073 811d4cf4 balrog
    default:
1074 c8d80cef Aurelien Jarno
        if (data_reg != TCG_REG_R0) {
1075 7e0d9562 Aurelien Jarno
            tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1076 c8d80cef Aurelien Jarno
                            data_reg, 0, TCG_REG_R0, SHIFT_IMM_LSL(0));
1077 c8d80cef Aurelien Jarno
        }
1078 811d4cf4 balrog
        break;
1079 811d4cf4 balrog
    case 3:
1080 c8d80cef Aurelien Jarno
        if (data_reg != TCG_REG_R0) {
1081 7e0d9562 Aurelien Jarno
            tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1082 c8d80cef Aurelien Jarno
                            data_reg, 0, TCG_REG_R0, SHIFT_IMM_LSL(0));
1083 c8d80cef Aurelien Jarno
        }
1084 c8d80cef Aurelien Jarno
        if (data_reg2 != TCG_REG_R1) {
1085 7e0d9562 Aurelien Jarno
            tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1086 c8d80cef Aurelien Jarno
                            data_reg2, 0, TCG_REG_R1, SHIFT_IMM_LSL(0));
1087 c8d80cef Aurelien Jarno
        }
1088 811d4cf4 balrog
        break;
1089 811d4cf4 balrog
    }
1090 811d4cf4 balrog
1091 c69806ab Aurelien Jarno
    reloc_pc24(label_ptr, (tcg_target_long)s->code_ptr);
1092 379f6698 Paul Brook
#else /* !CONFIG_SOFTMMU */
1093 379f6698 Paul Brook
    if (GUEST_BASE) {
1094 379f6698 Paul Brook
        uint32_t offset = GUEST_BASE;
1095 379f6698 Paul Brook
        int i;
1096 379f6698 Paul Brook
        int rot;
1097 379f6698 Paul Brook
1098 379f6698 Paul Brook
        while (offset) {
1099 379f6698 Paul Brook
            i = ctz32(offset) & ~1;
1100 379f6698 Paul Brook
            rot = ((32 - i) << 7) & 0xf00;
1101 379f6698 Paul Brook
1102 c8d80cef Aurelien Jarno
            tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R8, addr_reg,
1103 379f6698 Paul Brook
                            ((offset >> i) & 0xff) | rot);
1104 c8d80cef Aurelien Jarno
            addr_reg = TCG_REG_R8;
1105 379f6698 Paul Brook
            offset &= ~(0xff << i);
1106 379f6698 Paul Brook
        }
1107 379f6698 Paul Brook
    }
1108 811d4cf4 balrog
    switch (opc) {
1109 811d4cf4 balrog
    case 0:
1110 811d4cf4 balrog
        tcg_out_ld8_12(s, COND_AL, data_reg, addr_reg, 0);
1111 811d4cf4 balrog
        break;
1112 811d4cf4 balrog
    case 0 | 4:
1113 811d4cf4 balrog
        tcg_out_ld8s_8(s, COND_AL, data_reg, addr_reg, 0);
1114 811d4cf4 balrog
        break;
1115 811d4cf4 balrog
    case 1:
1116 811d4cf4 balrog
        tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
1117 67dcab73 Aurelien Jarno
        if (bswap) {
1118 67dcab73 Aurelien Jarno
            tcg_out_bswap16(s, COND_AL, data_reg, data_reg);
1119 67dcab73 Aurelien Jarno
        }
1120 811d4cf4 balrog
        break;
1121 811d4cf4 balrog
    case 1 | 4:
1122 67dcab73 Aurelien Jarno
        if (bswap) {
1123 67dcab73 Aurelien Jarno
            tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
1124 67dcab73 Aurelien Jarno
            tcg_out_bswap16s(s, COND_AL, data_reg, data_reg);
1125 67dcab73 Aurelien Jarno
        } else {
1126 67dcab73 Aurelien Jarno
            tcg_out_ld16s_8(s, COND_AL, data_reg, addr_reg, 0);
1127 67dcab73 Aurelien Jarno
        }
1128 811d4cf4 balrog
        break;
1129 811d4cf4 balrog
    case 2:
1130 811d4cf4 balrog
    default:
1131 811d4cf4 balrog
        tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
1132 67dcab73 Aurelien Jarno
        if (bswap) {
1133 67dcab73 Aurelien Jarno
            tcg_out_bswap32(s, COND_AL, data_reg, data_reg);
1134 67dcab73 Aurelien Jarno
        }
1135 811d4cf4 balrog
        break;
1136 811d4cf4 balrog
    case 3:
1137 eae6ce52 balrog
        /* TODO: use block load -
1138 eae6ce52 balrog
         * check that data_reg2 > data_reg or the other way */
1139 419bafa5 aurel32
        if (data_reg == addr_reg) {
1140 67dcab73 Aurelien Jarno
            tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, bswap ? 0 : 4);
1141 67dcab73 Aurelien Jarno
            tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, bswap ? 4 : 0);
1142 419bafa5 aurel32
        } else {
1143 67dcab73 Aurelien Jarno
            tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, bswap ? 4 : 0);
1144 67dcab73 Aurelien Jarno
            tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, bswap ? 0 : 4);
1145 67dcab73 Aurelien Jarno
        }
1146 67dcab73 Aurelien Jarno
        if (bswap) {
1147 67dcab73 Aurelien Jarno
            tcg_out_bswap32(s, COND_AL, data_reg, data_reg);
1148 67dcab73 Aurelien Jarno
            tcg_out_bswap32(s, COND_AL, data_reg2, data_reg2);
1149 419bafa5 aurel32
        }
1150 811d4cf4 balrog
        break;
1151 811d4cf4 balrog
    }
1152 811d4cf4 balrog
#endif
1153 811d4cf4 balrog
}
1154 811d4cf4 balrog
1155 7e0d9562 Aurelien Jarno
static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
1156 811d4cf4 balrog
{
1157 67dcab73 Aurelien Jarno
    int addr_reg, data_reg, data_reg2, bswap;
1158 811d4cf4 balrog
#ifdef CONFIG_SOFTMMU
1159 811d4cf4 balrog
    int mem_index, s_bits;
1160 811d4cf4 balrog
# if TARGET_LONG_BITS == 64
1161 811d4cf4 balrog
    int addr_reg2;
1162 811d4cf4 balrog
# endif
1163 811d4cf4 balrog
    uint32_t *label_ptr;
1164 811d4cf4 balrog
#endif
1165 811d4cf4 balrog
1166 67dcab73 Aurelien Jarno
#ifdef TARGET_WORDS_BIGENDIAN
1167 67dcab73 Aurelien Jarno
    bswap = 1;
1168 67dcab73 Aurelien Jarno
#else
1169 67dcab73 Aurelien Jarno
    bswap = 0;
1170 67dcab73 Aurelien Jarno
#endif
1171 811d4cf4 balrog
    data_reg = *args++;
1172 811d4cf4 balrog
    if (opc == 3)
1173 811d4cf4 balrog
        data_reg2 = *args++;
1174 811d4cf4 balrog
    else
1175 d89c682f Stefan Weil
        data_reg2 = 0; /* suppress warning */
1176 811d4cf4 balrog
    addr_reg = *args++;
1177 811d4cf4 balrog
#ifdef CONFIG_SOFTMMU
1178 aef3a282 balrog
# if TARGET_LONG_BITS == 64
1179 aef3a282 balrog
    addr_reg2 = *args++;
1180 aef3a282 balrog
# endif
1181 811d4cf4 balrog
    mem_index = *args;
1182 811d4cf4 balrog
    s_bits = opc & 3;
1183 811d4cf4 balrog
1184 91a3c1b0 balrog
    /* Should generate something like the following:
1185 3979144c pbrook
     *  shr r8, addr_reg, #TARGET_PAGE_BITS
1186 91a3c1b0 balrog
     *  and r0, r8, #(CPU_TLB_SIZE - 1)   @ Assumption: CPU_TLB_BITS <= 8
1187 3979144c pbrook
     *  add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
1188 91a3c1b0 balrog
     */
1189 811d4cf4 balrog
    tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1190 c8d80cef Aurelien Jarno
                    TCG_REG_R8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
1191 811d4cf4 balrog
    tcg_out_dat_imm(s, COND_AL, ARITH_AND,
1192 c8d80cef Aurelien Jarno
                    TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
1193 c8d80cef Aurelien Jarno
    tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0,
1194 c8d80cef Aurelien Jarno
                    TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
1195 91a3c1b0 balrog
    /* In the
1196 91a3c1b0 balrog
     *  ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_write))]
1197 91a3c1b0 balrog
     * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1198 91a3c1b0 balrog
     * not exceed otherwise, so use an
1199 91a3c1b0 balrog
     *  add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
1200 91a3c1b0 balrog
     * before.
1201 91a3c1b0 balrog
     */
1202 225b4376 balrog
    if (mem_index)
1203 c8d80cef Aurelien Jarno
        tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
1204 225b4376 balrog
                        (mem_index << (TLB_SHIFT & 1)) |
1205 225b4376 balrog
                        ((16 - (TLB_SHIFT >> 1)) << 8));
1206 c8d80cef Aurelien Jarno
    tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0,
1207 225b4376 balrog
                    offsetof(CPUState, tlb_table[0][0].addr_write));
1208 c8d80cef Aurelien Jarno
    tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
1209 c8d80cef Aurelien Jarno
                    TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
1210 3979144c pbrook
    /* Check alignment.  */
1211 3979144c pbrook
    if (s_bits)
1212 3979144c pbrook
        tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
1213 3979144c pbrook
                        0, addr_reg, (1 << s_bits) - 1);
1214 811d4cf4 balrog
#  if TARGET_LONG_BITS == 64
1215 811d4cf4 balrog
    /* XXX: possibly we could use a block data load or writeback in
1216 811d4cf4 balrog
     * the first access.  */
1217 c8d80cef Aurelien Jarno
    tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
1218 c8d80cef Aurelien Jarno
                    offsetof(CPUState, tlb_table[0][0].addr_write) + 4);
1219 c8d80cef Aurelien Jarno
    tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1220 c8d80cef Aurelien Jarno
                    TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0));
1221 811d4cf4 balrog
#  endif
1222 c8d80cef Aurelien Jarno
    tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
1223 225b4376 balrog
                    offsetof(CPUState, tlb_table[0][0].addend));
1224 811d4cf4 balrog
1225 811d4cf4 balrog
    switch (opc) {
1226 811d4cf4 balrog
    case 0:
1227 c8d80cef Aurelien Jarno
        tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1228 811d4cf4 balrog
        break;
1229 811d4cf4 balrog
    case 1:
1230 67dcab73 Aurelien Jarno
        if (bswap) {
1231 67dcab73 Aurelien Jarno
            tcg_out_bswap16(s, COND_EQ, TCG_REG_R0, data_reg);
1232 67dcab73 Aurelien Jarno
            tcg_out_st16_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1);
1233 67dcab73 Aurelien Jarno
        } else {
1234 67dcab73 Aurelien Jarno
            tcg_out_st16_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1235 67dcab73 Aurelien Jarno
        }
1236 811d4cf4 balrog
        break;
1237 811d4cf4 balrog
    case 2:
1238 811d4cf4 balrog
    default:
1239 67dcab73 Aurelien Jarno
        if (bswap) {
1240 67dcab73 Aurelien Jarno
            tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg);
1241 67dcab73 Aurelien Jarno
            tcg_out_st32_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1);
1242 67dcab73 Aurelien Jarno
        } else {
1243 67dcab73 Aurelien Jarno
            tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
1244 67dcab73 Aurelien Jarno
        }
1245 811d4cf4 balrog
        break;
1246 811d4cf4 balrog
    case 3:
1247 67dcab73 Aurelien Jarno
        if (bswap) {
1248 67dcab73 Aurelien Jarno
            tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg2);
1249 67dcab73 Aurelien Jarno
            tcg_out_st32_rwb(s, COND_EQ, TCG_REG_R0, TCG_REG_R1, addr_reg);
1250 67dcab73 Aurelien Jarno
            tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg);
1251 9a3abc21 Aurelien Jarno
            tcg_out_st32_12(s, COND_EQ, TCG_REG_R0, TCG_REG_R1, 4);
1252 67dcab73 Aurelien Jarno
        } else {
1253 67dcab73 Aurelien Jarno
            tcg_out_st32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
1254 67dcab73 Aurelien Jarno
            tcg_out_st32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
1255 67dcab73 Aurelien Jarno
        }
1256 811d4cf4 balrog
        break;
1257 811d4cf4 balrog
    }
1258 811d4cf4 balrog
1259 811d4cf4 balrog
    label_ptr = (void *) s->code_ptr;
1260 c69806ab Aurelien Jarno
    tcg_out_b_noaddr(s, COND_EQ);
1261 811d4cf4 balrog
1262 811d4cf4 balrog
    /* TODO: move this code to where the constants pool will be */
1263 2633a2d0 Aurelien Jarno
    tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1264 2633a2d0 Aurelien Jarno
                    TCG_REG_R0, 0, addr_reg, SHIFT_IMM_LSL(0));
1265 811d4cf4 balrog
# if TARGET_LONG_BITS == 32
1266 811d4cf4 balrog
    switch (opc) {
1267 811d4cf4 balrog
    case 0:
1268 e854b6d3 Aurelien Jarno
        tcg_out_ext8u(s, COND_AL, TCG_REG_R1, data_reg);
1269 7e0d9562 Aurelien Jarno
        tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
1270 811d4cf4 balrog
        break;
1271 811d4cf4 balrog
    case 1:
1272 e854b6d3 Aurelien Jarno
        tcg_out_ext16u(s, COND_AL, TCG_REG_R1, data_reg);
1273 7e0d9562 Aurelien Jarno
        tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
1274 811d4cf4 balrog
        break;
1275 811d4cf4 balrog
    case 2:
1276 2633a2d0 Aurelien Jarno
        tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1277 2633a2d0 Aurelien Jarno
                        TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(0));
1278 7e0d9562 Aurelien Jarno
        tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
1279 811d4cf4 balrog
        break;
1280 811d4cf4 balrog
    case 3:
1281 bf5675ef Aurelien Jarno
        tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R8, 0, mem_index);
1282 bf5675ef Aurelien Jarno
        tcg_out32(s, (COND_AL << 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
1283 bf5675ef Aurelien Jarno
        if (data_reg != TCG_REG_R2) {
1284 7e0d9562 Aurelien Jarno
            tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1285 bf5675ef Aurelien Jarno
                            TCG_REG_R2, 0, data_reg, SHIFT_IMM_LSL(0));
1286 bf5675ef Aurelien Jarno
        }
1287 bf5675ef Aurelien Jarno
        if (data_reg2 != TCG_REG_R3) {
1288 bf5675ef Aurelien Jarno
            tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1289 bf5675ef Aurelien Jarno
                            TCG_REG_R3, 0, data_reg2, SHIFT_IMM_LSL(0));
1290 c8d80cef Aurelien Jarno
        }
1291 811d4cf4 balrog
        break;
1292 811d4cf4 balrog
    }
1293 811d4cf4 balrog
# else
1294 2633a2d0 Aurelien Jarno
    tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1295 2633a2d0 Aurelien Jarno
                    TCG_REG_R1, 0, addr_reg2, SHIFT_IMM_LSL(0));
1296 811d4cf4 balrog
    switch (opc) {
1297 811d4cf4 balrog
    case 0:
1298 e854b6d3 Aurelien Jarno
        tcg_out_ext8u(s, COND_AL, TCG_REG_R2, data_reg);
1299 7e0d9562 Aurelien Jarno
        tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R3, 0, mem_index);
1300 811d4cf4 balrog
        break;
1301 811d4cf4 balrog
    case 1:
1302 e854b6d3 Aurelien Jarno
        tcg_out_ext16u(s, COND_AL, TCG_REG_R2, data_reg);
1303 7e0d9562 Aurelien Jarno
        tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R3, 0, mem_index);
1304 811d4cf4 balrog
        break;
1305 811d4cf4 balrog
    case 2:
1306 c8d80cef Aurelien Jarno
        if (data_reg != TCG_REG_R2) {
1307 7e0d9562 Aurelien Jarno
            tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1308 c8d80cef Aurelien Jarno
                            TCG_REG_R2, 0, data_reg, SHIFT_IMM_LSL(0));
1309 c8d80cef Aurelien Jarno
        }
1310 7e0d9562 Aurelien Jarno
        tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R3, 0, mem_index);
1311 811d4cf4 balrog
        break;
1312 811d4cf4 balrog
    case 3:
1313 7e0d9562 Aurelien Jarno
        tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R8, 0, mem_index);
1314 7e0d9562 Aurelien Jarno
        tcg_out32(s, (COND_AL << 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
1315 c8d80cef Aurelien Jarno
        if (data_reg != TCG_REG_R2) {
1316 7e0d9562 Aurelien Jarno
            tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1317 c8d80cef Aurelien Jarno
                            TCG_REG_R2, 0, data_reg, SHIFT_IMM_LSL(0));
1318 c8d80cef Aurelien Jarno
        }
1319 c8d80cef Aurelien Jarno
        if (data_reg2 != TCG_REG_R3) {
1320 7e0d9562 Aurelien Jarno
            tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1321 c8d80cef Aurelien Jarno
                            TCG_REG_R3, 0, data_reg2, SHIFT_IMM_LSL(0));
1322 c8d80cef Aurelien Jarno
        }
1323 811d4cf4 balrog
        break;
1324 811d4cf4 balrog
    }
1325 811d4cf4 balrog
# endif
1326 811d4cf4 balrog
1327 7e0d9562 Aurelien Jarno
    tcg_out_bl(s, COND_AL, (tcg_target_long) qemu_st_helpers[s_bits] -
1328 811d4cf4 balrog
                    (tcg_target_long) s->code_ptr);
1329 811d4cf4 balrog
    if (opc == 3)
1330 7e0d9562 Aurelien Jarno
        tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R13, TCG_REG_R13, 0x10);
1331 811d4cf4 balrog
1332 c69806ab Aurelien Jarno
    reloc_pc24(label_ptr, (tcg_target_long)s->code_ptr);
1333 379f6698 Paul Brook
#else /* !CONFIG_SOFTMMU */
1334 379f6698 Paul Brook
    if (GUEST_BASE) {
1335 379f6698 Paul Brook
        uint32_t offset = GUEST_BASE;
1336 379f6698 Paul Brook
        int i;
1337 379f6698 Paul Brook
        int rot;
1338 379f6698 Paul Brook
1339 379f6698 Paul Brook
        while (offset) {
1340 379f6698 Paul Brook
            i = ctz32(offset) & ~1;
1341 379f6698 Paul Brook
            rot = ((32 - i) << 7) & 0xf00;
1342 379f6698 Paul Brook
1343 67dcab73 Aurelien Jarno
            tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R1, addr_reg,
1344 379f6698 Paul Brook
                            ((offset >> i) & 0xff) | rot);
1345 67dcab73 Aurelien Jarno
            addr_reg = TCG_REG_R1;
1346 379f6698 Paul Brook
            offset &= ~(0xff << i);
1347 379f6698 Paul Brook
        }
1348 379f6698 Paul Brook
    }
1349 811d4cf4 balrog
    switch (opc) {
1350 811d4cf4 balrog
    case 0:
1351 811d4cf4 balrog
        tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0);
1352 811d4cf4 balrog
        break;
1353 811d4cf4 balrog
    case 1:
1354 67dcab73 Aurelien Jarno
        if (bswap) {
1355 67dcab73 Aurelien Jarno
            tcg_out_bswap16(s, COND_AL, TCG_REG_R0, data_reg);
1356 67dcab73 Aurelien Jarno
            tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addr_reg, 0);
1357 67dcab73 Aurelien Jarno
        } else {
1358 67dcab73 Aurelien Jarno
            tcg_out_st16_8(s, COND_AL, data_reg, addr_reg, 0);
1359 67dcab73 Aurelien Jarno
        }
1360 811d4cf4 balrog
        break;
1361 811d4cf4 balrog
    case 2:
1362 811d4cf4 balrog
    default:
1363 67dcab73 Aurelien Jarno
        if (bswap) {
1364 67dcab73 Aurelien Jarno
            tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg);
1365 67dcab73 Aurelien Jarno
            tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 0);
1366 67dcab73 Aurelien Jarno
        } else {
1367 67dcab73 Aurelien Jarno
            tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1368 67dcab73 Aurelien Jarno
        }
1369 811d4cf4 balrog
        break;
1370 811d4cf4 balrog
    case 3:
1371 eae6ce52 balrog
        /* TODO: use block store -
1372 eae6ce52 balrog
         * check that data_reg2 > data_reg or the other way */
1373 67dcab73 Aurelien Jarno
        if (bswap) {
1374 67dcab73 Aurelien Jarno
            tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg2);
1375 67dcab73 Aurelien Jarno
            tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 0);
1376 67dcab73 Aurelien Jarno
            tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg);
1377 67dcab73 Aurelien Jarno
            tcg_out_st32_12(s, COND_AL, TCG_REG_R0, addr_reg, 4);
1378 67dcab73 Aurelien Jarno
        } else {
1379 67dcab73 Aurelien Jarno
            tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1380 67dcab73 Aurelien Jarno
            tcg_out_st32_12(s, COND_AL, data_reg2, addr_reg, 4);
1381 67dcab73 Aurelien Jarno
        }
1382 811d4cf4 balrog
        break;
1383 811d4cf4 balrog
    }
1384 811d4cf4 balrog
#endif
1385 811d4cf4 balrog
}
1386 811d4cf4 balrog
1387 811d4cf4 balrog
static uint8_t *tb_ret_addr;
1388 811d4cf4 balrog
1389 a9751609 Richard Henderson
static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
1390 811d4cf4 balrog
                const TCGArg *args, const int *const_args)
1391 811d4cf4 balrog
{
1392 811d4cf4 balrog
    int c;
1393 811d4cf4 balrog
1394 811d4cf4 balrog
    switch (opc) {
1395 811d4cf4 balrog
    case INDEX_op_exit_tb:
1396 fe33867b balrog
        {
1397 fe33867b balrog
            uint8_t *ld_ptr = s->code_ptr;
1398 fe33867b balrog
            if (args[0] >> 8)
1399 c8d80cef Aurelien Jarno
                tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0);
1400 fe33867b balrog
            else
1401 c8d80cef Aurelien Jarno
                tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R0, 0, args[0]);
1402 fe33867b balrog
            tcg_out_goto(s, COND_AL, (tcg_target_ulong) tb_ret_addr);
1403 fe33867b balrog
            if (args[0] >> 8) {
1404 fe33867b balrog
                *ld_ptr = (uint8_t) (s->code_ptr - ld_ptr) - 8;
1405 fe33867b balrog
                tcg_out32(s, args[0]);
1406 fe33867b balrog
            }
1407 fe33867b balrog
        }
1408 811d4cf4 balrog
        break;
1409 811d4cf4 balrog
    case INDEX_op_goto_tb:
1410 811d4cf4 balrog
        if (s->tb_jmp_offset) {
1411 811d4cf4 balrog
            /* Direct jump method */
1412 fe33867b balrog
#if defined(USE_DIRECT_JUMP)
1413 811d4cf4 balrog
            s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1414 c69806ab Aurelien Jarno
            tcg_out_b_noaddr(s, COND_AL);
1415 811d4cf4 balrog
#else
1416 c8d80cef Aurelien Jarno
            tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
1417 811d4cf4 balrog
            s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1418 811d4cf4 balrog
            tcg_out32(s, 0);
1419 811d4cf4 balrog
#endif
1420 811d4cf4 balrog
        } else {
1421 811d4cf4 balrog
            /* Indirect jump method */
1422 811d4cf4 balrog
#if 1
1423 811d4cf4 balrog
            c = (int) (s->tb_next + args[0]) - ((int) s->code_ptr + 8);
1424 811d4cf4 balrog
            if (c > 0xfff || c < -0xfff) {
1425 811d4cf4 balrog
                tcg_out_movi32(s, COND_AL, TCG_REG_R0,
1426 811d4cf4 balrog
                                (tcg_target_long) (s->tb_next + args[0]));
1427 c8d80cef Aurelien Jarno
                tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0);
1428 811d4cf4 balrog
            } else
1429 c8d80cef Aurelien Jarno
                tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, c);
1430 811d4cf4 balrog
#else
1431 c8d80cef Aurelien Jarno
            tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, TCG_REG_PC, 0);
1432 c8d80cef Aurelien Jarno
            tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, 0);
1433 811d4cf4 balrog
            tcg_out32(s, (tcg_target_long) (s->tb_next + args[0]));
1434 811d4cf4 balrog
#endif
1435 811d4cf4 balrog
        }
1436 811d4cf4 balrog
        s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1437 811d4cf4 balrog
        break;
1438 811d4cf4 balrog
    case INDEX_op_call:
1439 811d4cf4 balrog
        if (const_args[0])
1440 811d4cf4 balrog
            tcg_out_call(s, COND_AL, args[0]);
1441 811d4cf4 balrog
        else
1442 811d4cf4 balrog
            tcg_out_callr(s, COND_AL, args[0]);
1443 811d4cf4 balrog
        break;
1444 811d4cf4 balrog
    case INDEX_op_jmp:
1445 811d4cf4 balrog
        if (const_args[0])
1446 811d4cf4 balrog
            tcg_out_goto(s, COND_AL, args[0]);
1447 811d4cf4 balrog
        else
1448 811d4cf4 balrog
            tcg_out_bx(s, COND_AL, args[0]);
1449 811d4cf4 balrog
        break;
1450 811d4cf4 balrog
    case INDEX_op_br:
1451 811d4cf4 balrog
        tcg_out_goto_label(s, COND_AL, args[0]);
1452 811d4cf4 balrog
        break;
1453 811d4cf4 balrog
1454 811d4cf4 balrog
    case INDEX_op_ld8u_i32:
1455 811d4cf4 balrog
        tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
1456 811d4cf4 balrog
        break;
1457 811d4cf4 balrog
    case INDEX_op_ld8s_i32:
1458 811d4cf4 balrog
        tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
1459 811d4cf4 balrog
        break;
1460 811d4cf4 balrog
    case INDEX_op_ld16u_i32:
1461 811d4cf4 balrog
        tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
1462 811d4cf4 balrog
        break;
1463 811d4cf4 balrog
    case INDEX_op_ld16s_i32:
1464 811d4cf4 balrog
        tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
1465 811d4cf4 balrog
        break;
1466 811d4cf4 balrog
    case INDEX_op_ld_i32:
1467 811d4cf4 balrog
        tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
1468 811d4cf4 balrog
        break;
1469 811d4cf4 balrog
    case INDEX_op_st8_i32:
1470 f694a27e Aurelien Jarno
        tcg_out_st8(s, COND_AL, args[0], args[1], args[2]);
1471 811d4cf4 balrog
        break;
1472 811d4cf4 balrog
    case INDEX_op_st16_i32:
1473 f694a27e Aurelien Jarno
        tcg_out_st16(s, COND_AL, args[0], args[1], args[2]);
1474 811d4cf4 balrog
        break;
1475 811d4cf4 balrog
    case INDEX_op_st_i32:
1476 811d4cf4 balrog
        tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
1477 811d4cf4 balrog
        break;
1478 811d4cf4 balrog
1479 811d4cf4 balrog
    case INDEX_op_mov_i32:
1480 811d4cf4 balrog
        tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1481 811d4cf4 balrog
                        args[0], 0, args[1], SHIFT_IMM_LSL(0));
1482 811d4cf4 balrog
        break;
1483 811d4cf4 balrog
    case INDEX_op_movi_i32:
1484 811d4cf4 balrog
        tcg_out_movi32(s, COND_AL, args[0], args[1]);
1485 811d4cf4 balrog
        break;
1486 811d4cf4 balrog
    case INDEX_op_add_i32:
1487 811d4cf4 balrog
        c = ARITH_ADD;
1488 811d4cf4 balrog
        goto gen_arith;
1489 811d4cf4 balrog
    case INDEX_op_sub_i32:
1490 811d4cf4 balrog
        c = ARITH_SUB;
1491 811d4cf4 balrog
        goto gen_arith;
1492 811d4cf4 balrog
    case INDEX_op_and_i32:
1493 811d4cf4 balrog
        c = ARITH_AND;
1494 811d4cf4 balrog
        goto gen_arith;
1495 932234f6 Aurelien Jarno
    case INDEX_op_andc_i32:
1496 932234f6 Aurelien Jarno
        c = ARITH_BIC;
1497 932234f6 Aurelien Jarno
        goto gen_arith;
1498 811d4cf4 balrog
    case INDEX_op_or_i32:
1499 811d4cf4 balrog
        c = ARITH_ORR;
1500 811d4cf4 balrog
        goto gen_arith;
1501 811d4cf4 balrog
    case INDEX_op_xor_i32:
1502 811d4cf4 balrog
        c = ARITH_EOR;
1503 811d4cf4 balrog
        /* Fall through.  */
1504 811d4cf4 balrog
    gen_arith:
1505 94953e6d Laurent Desnogues
        if (const_args[2]) {
1506 94953e6d Laurent Desnogues
            int rot;
1507 94953e6d Laurent Desnogues
            rot = encode_imm(args[2]);
1508 cb4e581f Laurent Desnogues
            tcg_out_dat_imm(s, COND_AL, c,
1509 94953e6d Laurent Desnogues
                            args[0], args[1], rotl(args[2], rot) | (rot << 7));
1510 94953e6d Laurent Desnogues
        } else
1511 cb4e581f Laurent Desnogues
            tcg_out_dat_reg(s, COND_AL, c,
1512 cb4e581f Laurent Desnogues
                            args[0], args[1], args[2], SHIFT_IMM_LSL(0));
1513 811d4cf4 balrog
        break;
1514 811d4cf4 balrog
    case INDEX_op_add2_i32:
1515 811d4cf4 balrog
        tcg_out_dat_reg2(s, COND_AL, ARITH_ADD, ARITH_ADC,
1516 811d4cf4 balrog
                        args[0], args[1], args[2], args[3],
1517 811d4cf4 balrog
                        args[4], args[5], SHIFT_IMM_LSL(0));
1518 811d4cf4 balrog
        break;
1519 811d4cf4 balrog
    case INDEX_op_sub2_i32:
1520 811d4cf4 balrog
        tcg_out_dat_reg2(s, COND_AL, ARITH_SUB, ARITH_SBC,
1521 811d4cf4 balrog
                        args[0], args[1], args[2], args[3],
1522 811d4cf4 balrog
                        args[4], args[5], SHIFT_IMM_LSL(0));
1523 811d4cf4 balrog
        break;
1524 650bbb36 balrog
    case INDEX_op_neg_i32:
1525 650bbb36 balrog
        tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
1526 650bbb36 balrog
        break;
1527 f878d2d2 Laurent Desnogues
    case INDEX_op_not_i32:
1528 f878d2d2 Laurent Desnogues
        tcg_out_dat_reg(s, COND_AL,
1529 f878d2d2 Laurent Desnogues
                        ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
1530 f878d2d2 Laurent Desnogues
        break;
1531 811d4cf4 balrog
    case INDEX_op_mul_i32:
1532 811d4cf4 balrog
        tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
1533 811d4cf4 balrog
        break;
1534 811d4cf4 balrog
    case INDEX_op_mulu2_i32:
1535 811d4cf4 balrog
        tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1536 811d4cf4 balrog
        break;
1537 811d4cf4 balrog
    /* XXX: Perhaps args[2] & 0x1f is wrong */
1538 811d4cf4 balrog
    case INDEX_op_shl_i32:
1539 811d4cf4 balrog
        c = const_args[2] ?
1540 811d4cf4 balrog
                SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
1541 811d4cf4 balrog
        goto gen_shift32;
1542 811d4cf4 balrog
    case INDEX_op_shr_i32:
1543 811d4cf4 balrog
        c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
1544 811d4cf4 balrog
                SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
1545 811d4cf4 balrog
        goto gen_shift32;
1546 811d4cf4 balrog
    case INDEX_op_sar_i32:
1547 811d4cf4 balrog
        c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
1548 811d4cf4 balrog
                SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
1549 293579e5 Aurelien Jarno
        goto gen_shift32;
1550 293579e5 Aurelien Jarno
    case INDEX_op_rotr_i32:
1551 293579e5 Aurelien Jarno
        c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ROR(args[2] & 0x1f) :
1552 293579e5 Aurelien Jarno
                SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args[2]);
1553 811d4cf4 balrog
        /* Fall through.  */
1554 811d4cf4 balrog
    gen_shift32:
1555 811d4cf4 balrog
        tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
1556 811d4cf4 balrog
        break;
1557 811d4cf4 balrog
1558 293579e5 Aurelien Jarno
    case INDEX_op_rotl_i32:
1559 293579e5 Aurelien Jarno
        if (const_args[2]) {
1560 293579e5 Aurelien Jarno
            tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1561 293579e5 Aurelien Jarno
                            ((0x20 - args[2]) & 0x1f) ?
1562 293579e5 Aurelien Jarno
                            SHIFT_IMM_ROR((0x20 - args[2]) & 0x1f) :
1563 293579e5 Aurelien Jarno
                            SHIFT_IMM_LSL(0));
1564 293579e5 Aurelien Jarno
        } else {
1565 293579e5 Aurelien Jarno
            tcg_out_dat_imm(s, COND_AL, ARITH_RSB, TCG_REG_R8, args[1], 0x20);
1566 293579e5 Aurelien Jarno
            tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1],
1567 293579e5 Aurelien Jarno
                            SHIFT_REG_ROR(TCG_REG_R8));
1568 293579e5 Aurelien Jarno
        }
1569 293579e5 Aurelien Jarno
        break;
1570 293579e5 Aurelien Jarno
1571 811d4cf4 balrog
    case INDEX_op_brcond_i32:
1572 023e77f8 Aurelien Jarno
        if (const_args[1]) {
1573 023e77f8 Aurelien Jarno
            int rot;
1574 023e77f8 Aurelien Jarno
            rot = encode_imm(args[1]);
1575 c8d80cef Aurelien Jarno
            tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0,
1576 c8d80cef Aurelien Jarno
                            args[0], rotl(args[1], rot) | (rot << 7));
1577 023e77f8 Aurelien Jarno
        } else {
1578 023e77f8 Aurelien Jarno
            tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1579 023e77f8 Aurelien Jarno
                            args[0], args[1], SHIFT_IMM_LSL(0));
1580 023e77f8 Aurelien Jarno
        }
1581 811d4cf4 balrog
        tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]);
1582 811d4cf4 balrog
        break;
1583 811d4cf4 balrog
    case INDEX_op_brcond2_i32:
1584 811d4cf4 balrog
        /* The resulting conditions are:
1585 811d4cf4 balrog
         * TCG_COND_EQ    -->  a0 == a2 && a1 == a3,
1586 811d4cf4 balrog
         * TCG_COND_NE    --> (a0 != a2 && a1 == a3) ||  a1 != a3,
1587 811d4cf4 balrog
         * TCG_COND_LT(U) --> (a0 <  a2 && a1 == a3) ||  a1 <  a3,
1588 811d4cf4 balrog
         * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1589 811d4cf4 balrog
         * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1590 811d4cf4 balrog
         * TCG_COND_GT(U) --> (a0 >  a2 && a1 == a3) ||  a1 >  a3,
1591 811d4cf4 balrog
         */
1592 811d4cf4 balrog
        tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1593 811d4cf4 balrog
                        args[1], args[3], SHIFT_IMM_LSL(0));
1594 811d4cf4 balrog
        tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1595 811d4cf4 balrog
                        args[0], args[2], SHIFT_IMM_LSL(0));
1596 811d4cf4 balrog
        tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]);
1597 811d4cf4 balrog
        break;
1598 f72a6cd7 Aurelien Jarno
    case INDEX_op_setcond_i32:
1599 023e77f8 Aurelien Jarno
        if (const_args[2]) {
1600 023e77f8 Aurelien Jarno
            int rot;
1601 023e77f8 Aurelien Jarno
            rot = encode_imm(args[2]);
1602 c8d80cef Aurelien Jarno
            tcg_out_dat_imm(s, COND_AL, ARITH_CMP, 0,
1603 c8d80cef Aurelien Jarno
                            args[1], rotl(args[2], rot) | (rot << 7));
1604 023e77f8 Aurelien Jarno
        } else {
1605 023e77f8 Aurelien Jarno
            tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1606 023e77f8 Aurelien Jarno
                            args[1], args[2], SHIFT_IMM_LSL(0));
1607 023e77f8 Aurelien Jarno
        }
1608 f72a6cd7 Aurelien Jarno
        tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
1609 f72a6cd7 Aurelien Jarno
                        ARITH_MOV, args[0], 0, 1);
1610 f72a6cd7 Aurelien Jarno
        tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
1611 f72a6cd7 Aurelien Jarno
                        ARITH_MOV, args[0], 0, 0);
1612 f72a6cd7 Aurelien Jarno
        break;
1613 e0404769 Aurelien Jarno
    case INDEX_op_setcond2_i32:
1614 e0404769 Aurelien Jarno
        /* See brcond2_i32 comment */
1615 e0404769 Aurelien Jarno
        tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1616 e0404769 Aurelien Jarno
                        args[2], args[4], SHIFT_IMM_LSL(0));
1617 e0404769 Aurelien Jarno
        tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1618 e0404769 Aurelien Jarno
                        args[1], args[3], SHIFT_IMM_LSL(0));
1619 e0404769 Aurelien Jarno
        tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]],
1620 e0404769 Aurelien Jarno
                        ARITH_MOV, args[0], 0, 1);
1621 e0404769 Aurelien Jarno
        tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])],
1622 e0404769 Aurelien Jarno
                        ARITH_MOV, args[0], 0, 0);
1623 b525f0a9 Andrzej Zaborowski
        break;
1624 811d4cf4 balrog
1625 811d4cf4 balrog
    case INDEX_op_qemu_ld8u:
1626 7e0d9562 Aurelien Jarno
        tcg_out_qemu_ld(s, args, 0);
1627 811d4cf4 balrog
        break;
1628 811d4cf4 balrog
    case INDEX_op_qemu_ld8s:
1629 7e0d9562 Aurelien Jarno
        tcg_out_qemu_ld(s, args, 0 | 4);
1630 811d4cf4 balrog
        break;
1631 811d4cf4 balrog
    case INDEX_op_qemu_ld16u:
1632 7e0d9562 Aurelien Jarno
        tcg_out_qemu_ld(s, args, 1);
1633 811d4cf4 balrog
        break;
1634 811d4cf4 balrog
    case INDEX_op_qemu_ld16s:
1635 7e0d9562 Aurelien Jarno
        tcg_out_qemu_ld(s, args, 1 | 4);
1636 811d4cf4 balrog
        break;
1637 86feb1c8 Richard Henderson
    case INDEX_op_qemu_ld32:
1638 7e0d9562 Aurelien Jarno
        tcg_out_qemu_ld(s, args, 2);
1639 811d4cf4 balrog
        break;
1640 811d4cf4 balrog
    case INDEX_op_qemu_ld64:
1641 7e0d9562 Aurelien Jarno
        tcg_out_qemu_ld(s, args, 3);
1642 811d4cf4 balrog
        break;
1643 650bbb36 balrog
1644 811d4cf4 balrog
    case INDEX_op_qemu_st8:
1645 7e0d9562 Aurelien Jarno
        tcg_out_qemu_st(s, args, 0);
1646 811d4cf4 balrog
        break;
1647 811d4cf4 balrog
    case INDEX_op_qemu_st16:
1648 7e0d9562 Aurelien Jarno
        tcg_out_qemu_st(s, args, 1);
1649 811d4cf4 balrog
        break;
1650 811d4cf4 balrog
    case INDEX_op_qemu_st32:
1651 7e0d9562 Aurelien Jarno
        tcg_out_qemu_st(s, args, 2);
1652 811d4cf4 balrog
        break;
1653 811d4cf4 balrog
    case INDEX_op_qemu_st64:
1654 7e0d9562 Aurelien Jarno
        tcg_out_qemu_st(s, args, 3);
1655 811d4cf4 balrog
        break;
1656 811d4cf4 balrog
1657 244b1e81 Aurelien Jarno
    case INDEX_op_bswap16_i32:
1658 244b1e81 Aurelien Jarno
        tcg_out_bswap16(s, COND_AL, args[0], args[1]);
1659 244b1e81 Aurelien Jarno
        break;
1660 244b1e81 Aurelien Jarno
    case INDEX_op_bswap32_i32:
1661 244b1e81 Aurelien Jarno
        tcg_out_bswap32(s, COND_AL, args[0], args[1]);
1662 244b1e81 Aurelien Jarno
        break;
1663 244b1e81 Aurelien Jarno
1664 811d4cf4 balrog
    case INDEX_op_ext8s_i32:
1665 9517094f Aurelien Jarno
        tcg_out_ext8s(s, COND_AL, args[0], args[1]);
1666 811d4cf4 balrog
        break;
1667 811d4cf4 balrog
    case INDEX_op_ext16s_i32:
1668 9517094f Aurelien Jarno
        tcg_out_ext16s(s, COND_AL, args[0], args[1]);
1669 9517094f Aurelien Jarno
        break;
1670 9517094f Aurelien Jarno
    case INDEX_op_ext16u_i32:
1671 9517094f Aurelien Jarno
        tcg_out_ext16u(s, COND_AL, args[0], args[1]);
1672 811d4cf4 balrog
        break;
1673 811d4cf4 balrog
1674 811d4cf4 balrog
    default:
1675 811d4cf4 balrog
        tcg_abort();
1676 811d4cf4 balrog
    }
1677 811d4cf4 balrog
}
1678 811d4cf4 balrog
1679 811d4cf4 balrog
static const TCGTargetOpDef arm_op_defs[] = {
1680 811d4cf4 balrog
    { INDEX_op_exit_tb, { } },
1681 811d4cf4 balrog
    { INDEX_op_goto_tb, { } },
1682 811d4cf4 balrog
    { INDEX_op_call, { "ri" } },
1683 811d4cf4 balrog
    { INDEX_op_jmp, { "ri" } },
1684 811d4cf4 balrog
    { INDEX_op_br, { } },
1685 811d4cf4 balrog
1686 811d4cf4 balrog
    { INDEX_op_mov_i32, { "r", "r" } },
1687 811d4cf4 balrog
    { INDEX_op_movi_i32, { "r" } },
1688 811d4cf4 balrog
1689 811d4cf4 balrog
    { INDEX_op_ld8u_i32, { "r", "r" } },
1690 811d4cf4 balrog
    { INDEX_op_ld8s_i32, { "r", "r" } },
1691 811d4cf4 balrog
    { INDEX_op_ld16u_i32, { "r", "r" } },
1692 811d4cf4 balrog
    { INDEX_op_ld16s_i32, { "r", "r" } },
1693 811d4cf4 balrog
    { INDEX_op_ld_i32, { "r", "r" } },
1694 811d4cf4 balrog
    { INDEX_op_st8_i32, { "r", "r" } },
1695 811d4cf4 balrog
    { INDEX_op_st16_i32, { "r", "r" } },
1696 811d4cf4 balrog
    { INDEX_op_st_i32, { "r", "r" } },
1697 811d4cf4 balrog
1698 811d4cf4 balrog
    /* TODO: "r", "r", "ri" */
1699 cb4e581f Laurent Desnogues
    { INDEX_op_add_i32, { "r", "r", "rI" } },
1700 cb4e581f Laurent Desnogues
    { INDEX_op_sub_i32, { "r", "r", "rI" } },
1701 811d4cf4 balrog
    { INDEX_op_mul_i32, { "r", "r", "r" } },
1702 811d4cf4 balrog
    { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1703 cb4e581f Laurent Desnogues
    { INDEX_op_and_i32, { "r", "r", "rI" } },
1704 932234f6 Aurelien Jarno
    { INDEX_op_andc_i32, { "r", "r", "rI" } },
1705 cb4e581f Laurent Desnogues
    { INDEX_op_or_i32, { "r", "r", "rI" } },
1706 cb4e581f Laurent Desnogues
    { INDEX_op_xor_i32, { "r", "r", "rI" } },
1707 650bbb36 balrog
    { INDEX_op_neg_i32, { "r", "r" } },
1708 f878d2d2 Laurent Desnogues
    { INDEX_op_not_i32, { "r", "r" } },
1709 811d4cf4 balrog
1710 811d4cf4 balrog
    { INDEX_op_shl_i32, { "r", "r", "ri" } },
1711 811d4cf4 balrog
    { INDEX_op_shr_i32, { "r", "r", "ri" } },
1712 811d4cf4 balrog
    { INDEX_op_sar_i32, { "r", "r", "ri" } },
1713 293579e5 Aurelien Jarno
    { INDEX_op_rotl_i32, { "r", "r", "ri" } },
1714 293579e5 Aurelien Jarno
    { INDEX_op_rotr_i32, { "r", "r", "ri" } },
1715 811d4cf4 balrog
1716 023e77f8 Aurelien Jarno
    { INDEX_op_brcond_i32, { "r", "rI" } },
1717 023e77f8 Aurelien Jarno
    { INDEX_op_setcond_i32, { "r", "r", "rI" } },
1718 811d4cf4 balrog
1719 811d4cf4 balrog
    /* TODO: "r", "r", "r", "r", "ri", "ri" */
1720 811d4cf4 balrog
    { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1721 811d4cf4 balrog
    { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1722 811d4cf4 balrog
    { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1723 e0404769 Aurelien Jarno
    { INDEX_op_setcond2_i32, { "r", "r", "r", "r", "r" } },
1724 811d4cf4 balrog
1725 26c5d372 Aurelien Jarno
#if TARGET_LONG_BITS == 32
1726 67dcab73 Aurelien Jarno
    { INDEX_op_qemu_ld8u, { "r", "l" } },
1727 67dcab73 Aurelien Jarno
    { INDEX_op_qemu_ld8s, { "r", "l" } },
1728 67dcab73 Aurelien Jarno
    { INDEX_op_qemu_ld16u, { "r", "l" } },
1729 67dcab73 Aurelien Jarno
    { INDEX_op_qemu_ld16s, { "r", "l" } },
1730 67dcab73 Aurelien Jarno
    { INDEX_op_qemu_ld32, { "r", "l" } },
1731 67dcab73 Aurelien Jarno
    { INDEX_op_qemu_ld64, { "L", "L", "l" } },
1732 67dcab73 Aurelien Jarno
1733 67dcab73 Aurelien Jarno
    { INDEX_op_qemu_st8, { "s", "s" } },
1734 67dcab73 Aurelien Jarno
    { INDEX_op_qemu_st16, { "s", "s" } },
1735 67dcab73 Aurelien Jarno
    { INDEX_op_qemu_st32, { "s", "s" } },
1736 bf5675ef Aurelien Jarno
    { INDEX_op_qemu_st64, { "S", "S", "s" } },
1737 26c5d372 Aurelien Jarno
#else
1738 67dcab73 Aurelien Jarno
    { INDEX_op_qemu_ld8u, { "r", "l", "l" } },
1739 67dcab73 Aurelien Jarno
    { INDEX_op_qemu_ld8s, { "r", "l", "l" } },
1740 67dcab73 Aurelien Jarno
    { INDEX_op_qemu_ld16u, { "r", "l", "l" } },
1741 67dcab73 Aurelien Jarno
    { INDEX_op_qemu_ld16s, { "r", "l", "l" } },
1742 67dcab73 Aurelien Jarno
    { INDEX_op_qemu_ld32, { "r", "l", "l" } },
1743 67dcab73 Aurelien Jarno
    { INDEX_op_qemu_ld64, { "L", "L", "l", "l" } },
1744 67dcab73 Aurelien Jarno
1745 67dcab73 Aurelien Jarno
    { INDEX_op_qemu_st8, { "s", "s", "s" } },
1746 67dcab73 Aurelien Jarno
    { INDEX_op_qemu_st16, { "s", "s", "s" } },
1747 67dcab73 Aurelien Jarno
    { INDEX_op_qemu_st32, { "s", "s", "s" } },
1748 bf5675ef Aurelien Jarno
    { INDEX_op_qemu_st64, { "S", "S", "s", "s" } },
1749 26c5d372 Aurelien Jarno
#endif
1750 811d4cf4 balrog
1751 244b1e81 Aurelien Jarno
    { INDEX_op_bswap16_i32, { "r", "r" } },
1752 244b1e81 Aurelien Jarno
    { INDEX_op_bswap32_i32, { "r", "r" } },
1753 244b1e81 Aurelien Jarno
1754 811d4cf4 balrog
    { INDEX_op_ext8s_i32, { "r", "r" } },
1755 811d4cf4 balrog
    { INDEX_op_ext16s_i32, { "r", "r" } },
1756 9517094f Aurelien Jarno
    { INDEX_op_ext16u_i32, { "r", "r" } },
1757 811d4cf4 balrog
1758 811d4cf4 balrog
    { -1 },
1759 811d4cf4 balrog
};
1760 811d4cf4 balrog
1761 e4d58b41 Richard Henderson
static void tcg_target_init(TCGContext *s)
1762 811d4cf4 balrog
{
1763 20cb400d Paul Brook
#if !defined(CONFIG_USER_ONLY)
1764 811d4cf4 balrog
    /* fail safe */
1765 811d4cf4 balrog
    if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1766 811d4cf4 balrog
        tcg_abort();
1767 20cb400d Paul Brook
#endif
1768 811d4cf4 balrog
1769 e4a7d5e8 Aurelien Jarno
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
1770 811d4cf4 balrog
    tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1771 e4a7d5e8 Aurelien Jarno
                     (1 << TCG_REG_R0) |
1772 e4a7d5e8 Aurelien Jarno
                     (1 << TCG_REG_R1) |
1773 e4a7d5e8 Aurelien Jarno
                     (1 << TCG_REG_R2) |
1774 e4a7d5e8 Aurelien Jarno
                     (1 << TCG_REG_R3) |
1775 e4a7d5e8 Aurelien Jarno
                     (1 << TCG_REG_R12) |
1776 e4a7d5e8 Aurelien Jarno
                     (1 << TCG_REG_R14));
1777 811d4cf4 balrog
1778 811d4cf4 balrog
    tcg_regset_clear(s->reserved_regs);
1779 811d4cf4 balrog
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
1780 811d4cf4 balrog
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8);
1781 e4a7d5e8 Aurelien Jarno
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
1782 811d4cf4 balrog
1783 811d4cf4 balrog
    tcg_add_target_add_op_defs(arm_op_defs);
1784 811d4cf4 balrog
}
1785 811d4cf4 balrog
1786 811d4cf4 balrog
static inline void tcg_out_ld(TCGContext *s, TCGType type, int arg,
1787 811d4cf4 balrog
                int arg1, tcg_target_long arg2)
1788 811d4cf4 balrog
{
1789 811d4cf4 balrog
    tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
1790 811d4cf4 balrog
}
1791 811d4cf4 balrog
1792 811d4cf4 balrog
static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
1793 811d4cf4 balrog
                int arg1, tcg_target_long arg2)
1794 811d4cf4 balrog
{
1795 811d4cf4 balrog
    tcg_out_st32(s, COND_AL, arg, arg1, arg2);
1796 811d4cf4 balrog
}
1797 811d4cf4 balrog
1798 2d69f359 Paul Brook
static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
1799 811d4cf4 balrog
{
1800 811d4cf4 balrog
    if (val > 0)
1801 811d4cf4 balrog
        if (val < 0x100)
1802 811d4cf4 balrog
            tcg_out_dat_imm(s, COND_AL, ARITH_ADD, reg, reg, val);
1803 811d4cf4 balrog
        else
1804 811d4cf4 balrog
            tcg_abort();
1805 811d4cf4 balrog
    else if (val < 0) {
1806 811d4cf4 balrog
        if (val > -0x100)
1807 811d4cf4 balrog
            tcg_out_dat_imm(s, COND_AL, ARITH_SUB, reg, reg, -val);
1808 811d4cf4 balrog
        else
1809 811d4cf4 balrog
            tcg_abort();
1810 811d4cf4 balrog
    }
1811 811d4cf4 balrog
}
1812 811d4cf4 balrog
1813 3b6dac34 Richard Henderson
static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg)
1814 811d4cf4 balrog
{
1815 811d4cf4 balrog
    tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
1816 811d4cf4 balrog
}
1817 811d4cf4 balrog
1818 811d4cf4 balrog
static inline void tcg_out_movi(TCGContext *s, TCGType type,
1819 811d4cf4 balrog
                int ret, tcg_target_long arg)
1820 811d4cf4 balrog
{
1821 811d4cf4 balrog
    tcg_out_movi32(s, COND_AL, ret, arg);
1822 811d4cf4 balrog
}
1823 811d4cf4 balrog
1824 e4d58b41 Richard Henderson
static void tcg_target_qemu_prologue(TCGContext *s)
1825 811d4cf4 balrog
{
1826 9e97d8e9 Aurelien Jarno
    /* There is no need to save r7, it is used to store the address
1827 9e97d8e9 Aurelien Jarno
       of the env structure and is not modified by GCC. */
1828 4e17eae9 Aurelien Jarno
1829 9e97d8e9 Aurelien Jarno
    /* stmdb sp!, { r4 - r6, r8 - r11, lr } */
1830 9e97d8e9 Aurelien Jarno
    tcg_out32(s, (COND_AL << 28) | 0x092d4f70);
1831 811d4cf4 balrog
1832 811d4cf4 balrog
    tcg_out_bx(s, COND_AL, TCG_REG_R0);
1833 811d4cf4 balrog
    tb_ret_addr = s->code_ptr;
1834 811d4cf4 balrog
1835 9e97d8e9 Aurelien Jarno
    /* ldmia sp!, { r4 - r6, r8 - r11, pc } */
1836 9e97d8e9 Aurelien Jarno
    tcg_out32(s, (COND_AL << 28) | 0x08bd8f70);
1837 811d4cf4 balrog
}