Revision 9a64fbe4 target-ppc/cpu.h
| b/target-ppc/cpu.h | ||
|---|---|---|
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#include "cpu-defs.h" |
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//#define USE_OPEN_FIRMWARE |
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|
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/*** Sign extend constants ***/ |
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/* 8 to 32 bits */ |
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static inline int32_t s_ext8 (uint8_t value) |
| ... | ... | |
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#include "config.h" |
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#include <setjmp.h> |
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/* Floting point status and control register */ |
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#define FPSCR_FX 31 |
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#define FPSCR_FEX 30 |
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#define FPSCR_VX 29 |
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#define FPSCR_OX 28 |
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#define FPSCR_UX 27 |
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#define FPSCR_ZX 26 |
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#define FPSCR_XX 25 |
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#define FPSCR_VXSNAN 24 |
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#define FPSCR_VXISI 26 |
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#define FPSCR_VXIDI 25 |
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#define FPSCR_VXZDZ 21 |
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#define FPSCR_VXIMZ 20 |
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/* Instruction types */ |
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enum {
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PPC_NONE = 0x0000, |
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PPC_INTEGER = 0x0001, /* CPU has integer operations instructions */ |
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PPC_FLOAT = 0x0002, /* CPU has floating point operations instructions */ |
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PPC_FLOW = 0x0004, /* CPU has flow control instructions */ |
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PPC_MEM = 0x0008, /* CPU has virtual memory instructions */ |
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PPC_RES = 0x0010, /* CPU has ld/st with reservation instructions */ |
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PPC_CACHE = 0x0020, /* CPU has cache control instructions */ |
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PPC_MISC = 0x0040, /* CPU has spr/msr access instructions */ |
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PPC_EXTERN = 0x0080, /* CPU has external control instructions */ |
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PPC_SEGMENT = 0x0100, /* CPU has memory segment instructions */ |
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PPC_CACHE_OPT= 0x0200, |
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PPC_FLOAT_OPT= 0x0400, |
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PPC_MEM_OPT = 0x0800, |
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}; |
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#define FPSCR_VXVC 18 |
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#define FPSCR_FR 17 |
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#define FPSCR_FI 16 |
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#define FPSCR_FPRF 11 |
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#define FPSCR_VXSOFT 9 |
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#define FPSCR_VXSQRT 8 |
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#define FPSCR_VXCVI 7 |
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#define FPSCR_OE 6 |
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#define FPSCR_UE 5 |
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#define FPSCR_ZE 4 |
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#define FPSCR_XE 3 |
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#define FPSCR_NI 2 |
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#define FPSCR_RN 0 |
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#define fpscr_fx env->fpscr[FPSCR_FX] |
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#define fpscr_fex env->fpscr[FPSCR_FEX] |
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#define fpscr_vx env->fpscr[FPSCR_VX] |
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#define fpscr_ox env->fpscr[FPSCR_OX] |
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#define fpscr_ux env->fpscr[FPSCR_UX] |
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#define fpscr_zx env->fpscr[FPSCR_ZX] |
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#define fpscr_xx env->fpscr[FPSCR_XX] |
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#define fpscr_vsxnan env->fpscr[FPSCR_VXSNAN] |
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#define fpscr_vxisi env->fpscr[FPSCR_VXISI] |
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#define fpscr_vxidi env->fpscr[FPSCR_VXIDI] |
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#define fpscr_vxzdz env->fpscr[FPSCR_VXZDZ] |
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#define fpscr_vximz env->fpscr[FPSCR_VXIMZ] |
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#define fpscr_fr env->fpscr[FPSCR_FR] |
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#define fpscr_fi env->fpscr[FPSCR_FI] |
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#define fpscr_fprf env->fpscr[FPSCR_FPRF] |
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#define fpscr_vxsoft env->fpscr[FPSCR_VXSOFT] |
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#define fpscr_vxsqrt env->fpscr[FPSCR_VXSQRT] |
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#define fpscr_oe env->fpscr[FPSCR_OE] |
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#define fpscr_ue env->fpscr[FPSCR_UE] |
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#define fpscr_ze env->fpscr[FPSCR_ZE] |
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#define fpscr_xe env->fpscr[FPSCR_XE] |
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#define fpscr_ni env->fpscr[FPSCR_NI] |
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#define fpscr_rn env->fpscr[FPSCR_RN] |
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#define PPC_COMMON (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \ |
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PPC_RES | PPC_CACHE | PPC_MISC | PPC_SEGMENT) |
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/* PPC 740/745/750/755 (aka G3) has external access instructions */ |
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#define PPC_750 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \ |
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PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT) |
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/* Supervisor mode registers */ |
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/* Machine state register */ |
| ... | ... | |
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#define msr_le env->msr[MSR_LE] |
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|
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/* Segment registers */ |
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typedef struct ppc_sr_t {
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uint32_t t:1; |
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uint32_t ks:1; |
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uint32_t kp:1; |
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uint32_t n:1; |
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uint32_t res:4; |
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uint32_t vsid:24; |
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} ppc_sr_t; |
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typedef struct CPUPPCState {
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/* general purpose registers */ |
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uint32_t gpr[32]; |
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/* floating point registers */ |
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double fpr[32]; |
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/* segment registers */ |
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ppc_sr_t sr[16]; |
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/* special purpose registers */ |
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uint32_t spr[1024]; |
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uint32_t sdr1; |
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uint32_t sr[16]; |
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/* XER */ |
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uint8_t xer[32];
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uint8_t xer[4];
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|
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/* Reservation address */ |
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uint32_t reserve; |
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/* machine state register */ |
| ... | ... | |
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/* condition register */ |
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uint8_t crf[8]; |
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/* floating point status and control register */ |
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uint8_t fpscr[32];
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uint8_t fpscr[8];
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uint32_t nip; |
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/* CPU exception code */ |
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uint32_t exception; |
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|
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/* special purpose registers */ |
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uint32_t lr; |
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uint32_t ctr; |
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/* Time base */ |
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uint32_t tb[2]; |
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/* decrementer */ |
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uint32_t decr; |
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/* BATs */ |
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uint32_t DBAT[2][8]; |
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uint32_t IBAT[2][8]; |
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/* all others */ |
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uint32_t spr[1024]; |
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/* qemu dedicated */ |
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/* temporary float registers */ |
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double ft0; |
| ... | ... | |
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jmp_buf jmp_env; |
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int exception_index; |
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int error_code; |
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uint32_t exceptions; /* exception queue */ |
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uint32_t errors[16]; |
|
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int user_mode_only; /* user mode only simulation */ |
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struct TranslationBlock *current_tb; /* currently executing TB */ |
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|
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/* soft mmu support */ |
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/* 0 = kernel, 1 = user */ |
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CPUTLBEntry tlb_read[2][CPU_TLB_SIZE]; |
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CPUTLBEntry tlb_write[2][CPU_TLB_SIZE]; |
|
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/* user data */ |
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void *opaque; |
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} CPUPPCState; |
| ... | ... | |
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void *puc); |
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|
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void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags); |
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void cpu_loop_exit(void); |
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void dump_stack (CPUPPCState *env); |
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uint32_t _load_xer (void); |
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void _store_xer (uint32_t value); |
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uint32_t _load_msr (void); |
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void _store_msr (uint32_t value); |
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void do_interrupt (CPUPPCState *env); |
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#define TARGET_PAGE_BITS 12 |
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#include "cpu-all.h" |
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|
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#define ugpr(n) (env->gpr[n]) |
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#define fpr(n) (env->fpr[n]) |
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#define fprd(n) (env->fpr[n]) |
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#define fprs(n) ((float)env->fpr[n]) |
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#define fpru(n) ((uint32_t)env->fpr[n]) |
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#define fpri(n) ((int32_t)env->fpr[n]) |
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#define SPR_ENCODE(sprn) \ |
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(((sprn) >> 5) | (((sprn) & 0x1F) << 5)) |
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|
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/* User mode SPR */ |
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#define spr(n) env->spr[n] |
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//#define XER spr[1] |
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#define XER env->xer |
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#define XER_SO 31 |
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#define XER_OV 30 |
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#define XER_CA 29 |
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#define XER_BC 0 |
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#define xer_so env->xer[XER_SO]
|
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#define xer_ov env->xer[XER_OV]
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#define xer_ca env->xer[XER_CA]
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#define xer_bc env->xer[XER_BC]
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#define xer_so env->xer[3]
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#define xer_ov env->xer[2]
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#define xer_ca env->xer[1]
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#define xer_bc env->xer[0]
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#define LR spr[SPR_ENCODE(8)] |
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#define CTR spr[SPR_ENCODE(9)] |
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#define XER SPR_ENCODE(1) |
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#define LR SPR_ENCODE(8) |
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#define CTR SPR_ENCODE(9) |
|
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/* VEA mode SPR */ |
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#define V_TBL spr[SPR_ENCODE(268)]
|
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#define V_TBU spr[SPR_ENCODE(269)]
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#define V_TBL SPR_ENCODE(268)
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#define V_TBU SPR_ENCODE(269)
|
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/* supervisor mode SPR */ |
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#define DSISR spr[SPR_ENCODE(18)] |
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#define DAR spr[SPR_ENCODE(19)] |
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#define DEC spr[SPR_ENCODE(22)] |
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#define SDR1 spr[SPR_ENCODE(25)] |
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typedef struct ppc_sdr1_t {
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uint32_t htaborg:16; |
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uint32_t res:7; |
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uint32_t htabmask:9; |
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} ppc_sdr1_t; |
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#define SRR0 spr[SPR_ENCODE(26)] |
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#define SRR0_MASK 0xFFFFFFFC |
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#define SRR1 spr[SPR_ENCODE(27)] |
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#define SPRG0 spr[SPR_ENCODE(272)] |
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#define SPRG1 spr[SPR_ENCODE(273)] |
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#define SPRG2 spr[SPR_ENCODE(274)] |
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#define SPRG3 spr[SPR_ENCODE(275)] |
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#define EAR spr[SPR_ENCODE(282)] |
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typedef struct ppc_ear_t {
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uint32_t e:1; |
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uint32_t res:25; |
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uint32_t rid:6; |
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} ppc_ear_t; |
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#define TBL spr[SPR_ENCODE(284)] |
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#define TBU spr[SPR_ENCODE(285)] |
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#define PVR spr[SPR_ENCODE(287)] |
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typedef struct ppc_pvr_t {
|
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uint32_t version:16; |
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uint32_t revision:16; |
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} ppc_pvr_t; |
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#define IBAT0U spr[SPR_ENCODE(528)] |
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#define IBAT0L spr[SPR_ENCODE(529)] |
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#define IBAT1U spr[SPR_ENCODE(530)] |
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#define IBAT1L spr[SPR_ENCODE(531)] |
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#define IBAT2U spr[SPR_ENCODE(532)] |
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#define IBAT2L spr[SPR_ENCODE(533)] |
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#define IBAT3U spr[SPR_ENCODE(534)] |
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#define IBAT3L spr[SPR_ENCODE(535)] |
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#define DBAT0U spr[SPR_ENCODE(536)] |
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#define DBAT0L spr[SPR_ENCODE(537)] |
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#define DBAT1U spr[SPR_ENCODE(538)] |
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#define DBAT1L spr[SPR_ENCODE(539)] |
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#define DBAT2U spr[SPR_ENCODE(540)] |
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#define DBAT2L spr[SPR_ENCODE(541)] |
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#define DBAT3U spr[SPR_ENCODE(542)] |
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#define DBAT3L spr[SPR_ENCODE(543)] |
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typedef struct ppc_ubat_t {
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uint32_t bepi:15; |
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uint32_t res:4; |
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uint32_t bl:11; |
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uint32_t vs:1; |
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uint32_t vp:1; |
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} ppc_ubat_t; |
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typedef struct ppc_lbat_t {
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uint32_t brpn:15; |
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uint32_t res0:10; |
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uint32_t w:1; |
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uint32_t i:1; |
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uint32_t m:1; |
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uint32_t g:1; |
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uint32_t res1:1; |
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uint32_t pp:2; |
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} ppc_lbat_t; |
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#define DABR spr[SPR_ENCODE(1013)] |
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#define DSISR SPR_ENCODE(18) |
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#define DAR SPR_ENCODE(19) |
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#define DECR SPR_ENCODE(22) |
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#define SDR1 SPR_ENCODE(25) |
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#define SRR0 SPR_ENCODE(26) |
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#define SRR1 SPR_ENCODE(27) |
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#define SPRG0 SPR_ENCODE(272) |
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#define SPRG1 SPR_ENCODE(273) |
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#define SPRG2 SPR_ENCODE(274) |
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#define SPRG3 SPR_ENCODE(275) |
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#define SPRG4 SPR_ENCODE(276) |
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#define SPRG5 SPR_ENCODE(277) |
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#define SPRG6 SPR_ENCODE(278) |
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#define SPRG7 SPR_ENCODE(279) |
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#define ASR SPR_ENCODE(280) |
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#define EAR SPR_ENCODE(282) |
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#define O_TBL SPR_ENCODE(284) |
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#define O_TBU SPR_ENCODE(285) |
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#define PVR SPR_ENCODE(287) |
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#define IBAT0U SPR_ENCODE(528) |
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#define IBAT0L SPR_ENCODE(529) |
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#define IBAT1U SPR_ENCODE(530) |
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#define IBAT1L SPR_ENCODE(531) |
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#define IBAT2U SPR_ENCODE(532) |
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#define IBAT2L SPR_ENCODE(533) |
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#define IBAT3U SPR_ENCODE(534) |
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#define IBAT3L SPR_ENCODE(535) |
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#define DBAT0U SPR_ENCODE(536) |
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#define DBAT0L SPR_ENCODE(537) |
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#define DBAT1U SPR_ENCODE(538) |
|
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#define DBAT1L SPR_ENCODE(539) |
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#define DBAT2U SPR_ENCODE(540) |
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#define DBAT2L SPR_ENCODE(541) |
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#define DBAT3U SPR_ENCODE(542) |
|
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#define DBAT3L SPR_ENCODE(543) |
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#define IBAT4U SPR_ENCODE(560) |
|
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#define IBAT4L SPR_ENCODE(561) |
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#define IBAT5U SPR_ENCODE(562) |
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#define IBAT5L SPR_ENCODE(563) |
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#define IBAT6U SPR_ENCODE(564) |
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#define IBAT6L SPR_ENCODE(565) |
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#define IBAT7U SPR_ENCODE(566) |
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#define IBAT7L SPR_ENCODE(567) |
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#define DBAT4U SPR_ENCODE(568) |
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#define DBAT4L SPR_ENCODE(569) |
|
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#define DBAT5U SPR_ENCODE(570) |
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#define DBAT5L SPR_ENCODE(571) |
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#define DBAT6U SPR_ENCODE(572) |
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#define DBAT6L SPR_ENCODE(573) |
|
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#define DBAT7U SPR_ENCODE(574) |
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#define DBAT7L SPR_ENCODE(575) |
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#define DABR SPR_ENCODE(1013) |
|
| 293 | 269 |
#define DABR_MASK 0xFFFFFFF8 |
| 294 |
typedef struct ppc_dabr_t {
|
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| 295 |
uint32_t dab:29; |
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uint32_t bt:1; |
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uint32_t dw:1; |
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uint32_t dr:1; |
|
| 299 |
} ppc_dabr_t; |
|
| 300 |
#define FPECR spr[SPR_ENCODE(1022)] |
|
| 301 |
#define PIR spr[SPR_ENCODE(1023)] |
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| 270 |
#define FPECR SPR_ENCODE(1022) |
|
| 271 |
#define PIR SPR_ENCODE(1023) |
|
| 302 | 272 |
|
| 303 | 273 |
#define TARGET_PAGE_BITS 12 |
| 304 | 274 |
#include "cpu-all.h" |
| ... | ... | |
| 307 | 277 |
int cpu_ppc_exec(CPUPPCState *s); |
| 308 | 278 |
void cpu_ppc_close(CPUPPCState *s); |
| 309 | 279 |
void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags); |
| 280 |
void PPC_init_hw (CPUPPCState *env, uint32_t mem_size, |
|
| 281 |
uint32_t kernel_addr, uint32_t kernel_size, |
|
| 282 |
uint32_t stack_addr, int boot_device); |
|
| 310 | 283 |
|
| 311 |
/* Exeptions */ |
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/* Memory access type : |
|
| 285 |
* may be needed for precise access rights control and precise exceptions. |
|
| 286 |
*/ |
|
| 312 | 287 |
enum {
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EXCP_NONE = 0x00, |
|
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/* 1 bit to define user level / supervisor access */ |
|
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ACCESS_USER = 0x00, |
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ACCESS_SUPER = 0x01, |
|
| 291 |
/* Type of instruction that generated the access */ |
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ACCESS_CODE = 0x10, /* Code fetch access */ |
|
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ACCESS_INT = 0x20, /* Integer load/store access */ |
|
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ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
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ACCESS_RES = 0x40, /* load/store with reservation */ |
|
| 296 |
ACCESS_EXT = 0x50, /* external access */ |
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| 297 |
ACCESS_CACHE = 0x60, /* Cache manipulation */ |
|
| 298 |
}; |
|
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|
|
| 300 |
/*****************************************************************************/ |
|
| 301 |
/* Exceptions */ |
|
| 302 |
enum {
|
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EXCP_NONE = -1, |
|
| 314 | 304 |
/* PPC hardware exceptions : exception vector / 0x100 */ |
| 315 | 305 |
EXCP_RESET = 0x01, /* System reset */ |
| 316 | 306 |
EXCP_MACHINE_CHECK = 0x02, /* Machine check exception */ |
| ... | ... | |
| 326 | 316 |
EXCP_SYSCALL = 0x0C, /* System call */ |
| 327 | 317 |
EXCP_TRACE = 0x0D, /* Trace exception (optional) */ |
| 328 | 318 |
EXCP_FP_ASSIST = 0x0E, /* Floating-point assist (optional) */ |
| 329 |
#if 0 |
|
| 330 |
/* Exeption subtypes for EXCP_DSI */ |
|
| 331 |
EXCP_DSI_TRANSLATE = 0x10301, /* Data address can't be translated */ |
|
| 332 |
EXCP_DSI_NOTSUP = 0x10302, /* Access type not supported */ |
|
| 333 |
EXCP_DSI_PROT = 0x10303, /* Memory protection violation */ |
|
| 334 |
EXCP_DSI_EXTERNAL = 0x10304, /* External access disabled */ |
|
| 335 |
EXCP_DSI_DABR = 0x10305, /* Data address breakpoint */ |
|
| 336 |
/* Exeption subtypes for EXCP_ISI */ |
|
| 337 |
EXCP_ISI_TRANSLATE = 0x10401, /* Code address can't be translated */ |
|
| 338 |
EXCP_ISI_NOTSUP = 0x10402, /* Access type not supported */ |
|
| 339 |
EXCP_ISI_PROT = 0x10403, /* Memory protection violation */ |
|
| 340 |
EXCP_ISI_GUARD = 0x10404, /* Fetch into guarded memory */ |
|
| 341 |
/* Exeption subtypes for EXCP_ALIGN */ |
|
| 342 |
EXCP_ALIGN_FP = 0x10601, /* FP alignment exception */ |
|
| 343 |
EXCP_ALIGN_LST = 0x10602, /* Unaligned memory load/store */ |
|
| 344 |
EXCP_ALIGN_LE = 0x10603, /* Unaligned little-endian access */ |
|
| 345 |
EXCP_ALIGN_PROT = 0x10604, /* Access cross protection boundary */ |
|
| 346 |
EXCP_ALIGN_BAT = 0x10605, /* Access cross a BAT/seg boundary */ |
|
| 347 |
EXCP_ALIGN_CACHE = 0x10606, /* Impossible dcbz access */ |
|
| 348 |
/* Exeption subtypes for EXCP_PROGRAM */ |
|
| 319 |
/* MPC740/745/750 & IBM 750 */ |
|
| 320 |
EXCP_PERF = 0x0F, /* Performance monitor */ |
|
| 321 |
EXCP_IABR = 0x13, /* Instruction address breakpoint */ |
|
| 322 |
EXCP_SMI = 0x14, /* System management interrupt */ |
|
| 323 |
EXCP_THRM = 0x15, /* Thermal management interrupt */ |
|
| 324 |
/* MPC755 */ |
|
| 325 |
EXCP_TLBMISS = 0x10, /* Instruction TLB miss */ |
|
| 326 |
EXCP_TLBMISS_DL = 0x11, /* Data TLB miss for load */ |
|
| 327 |
EXCP_TLBMISS_DS = 0x12, /* Data TLB miss for store */ |
|
| 328 |
EXCP_PPC_MAX = 0x16, |
|
| 329 |
/* Qemu exception */ |
|
| 330 |
EXCP_OFCALL = 0x20, /* Call open-firmware emulator */ |
|
| 331 |
EXCP_RTASCALL = 0x21, /* Call RTAS emulator */ |
|
| 332 |
/* Special cases where we want to stop translation */ |
|
| 333 |
EXCP_MTMSR = 0x104, /* mtmsr instruction: */ |
|
| 334 |
/* may change privilege level */ |
|
| 335 |
EXCP_BRANCH = 0x108, /* branch instruction */ |
|
| 336 |
EXCP_RFI = 0x10C, /* return from interrupt */ |
|
| 337 |
EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */ |
|
| 338 |
}; |
|
| 339 |
/* Error codes */ |
|
| 340 |
enum {
|
|
| 341 |
/* Exception subtypes for EXCP_DSI */ |
|
| 342 |
EXCP_DSI_TRANSLATE = 0x01, /* Data address can't be translated */ |
|
| 343 |
EXCP_DSI_NOTSUP = 0x02, /* Access type not supported */ |
|
| 344 |
EXCP_DSI_PROT = 0x03, /* Memory protection violation */ |
|
| 345 |
EXCP_DSI_EXTERNAL = 0x04, /* External access disabled */ |
|
| 346 |
EXCP_DSI_DABR = 0x05, /* Data address breakpoint */ |
|
| 347 |
/* flags for EXCP_DSI */ |
|
| 348 |
EXCP_DSI_DIRECT = 0x10, |
|
| 349 |
EXCP_DSI_STORE = 0x20, |
|
| 350 |
EXCP_ECXW = 0x40, |
|
| 351 |
/* Exception subtypes for EXCP_ISI */ |
|
| 352 |
EXCP_ISI_TRANSLATE = 0x01, /* Code address can't be translated */ |
|
| 353 |
EXCP_ISI_NOEXEC = 0x02, /* Try to fetch from a data segment */ |
|
| 354 |
EXCP_ISI_GUARD = 0x03, /* Fetch from guarded memory */ |
|
| 355 |
EXCP_ISI_PROT = 0x04, /* Memory protection violation */ |
|
| 356 |
/* Exception subtypes for EXCP_ALIGN */ |
|
| 357 |
EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ |
|
| 358 |
EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ |
|
| 359 |
EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ |
|
| 360 |
EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ |
|
| 361 |
EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ |
|
| 362 |
EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ |
|
| 363 |
/* Exception subtypes for EXCP_PROGRAM */ |
|
| 349 | 364 |
/* FP exceptions */ |
| 350 |
EXCP_FP_OX = 0x10701, /* FP overflow */ |
|
| 351 |
EXCP_FP_UX = 0x10702, /* FP underflow */ |
|
| 352 |
EXCP_FP_ZX = 0x10703, /* FP divide by zero */ |
|
| 353 |
EXCP_FP_XX = 0x10704, /* FP inexact */ |
|
| 354 |
EXCP_FP_VXNAN = 0x10705, /* FP invalid SNaN op */ |
|
| 355 |
EXCP_FP_VXISI = 0x10706, /* FP invalid infinite substraction */ |
|
| 356 |
EXCP_FP_VXIDI = 0x10707, /* FP invalid infinite divide */ |
|
| 357 |
EXCP_FP_VXZDZ = 0x10708, /* FP invalid zero divide */ |
|
| 358 |
EXCP_FP_VXIMZ = 0x10709, /* FP invalid infinite * zero */ |
|
| 359 |
EXCP_FP_VXVC = 0x1070A, /* FP invalid compare */ |
|
| 360 |
EXCP_FP_VXSOFT = 0x1070B, /* FP invalid operation */ |
|
| 361 |
EXCP_FP_VXSQRT = 0x1070C, /* FP invalid square root */ |
|
| 362 |
EXCP_FP_VXCVI = 0x1070D, /* FP invalid integer conversion */ |
|
| 365 |
EXCP_FP = 0x10, |
|
| 366 |
EXCP_FP_OX = 0x01, /* FP overflow */ |
|
| 367 |
EXCP_FP_UX = 0x02, /* FP underflow */ |
|
| 368 |
EXCP_FP_ZX = 0x03, /* FP divide by zero */ |
|
| 369 |
EXCP_FP_XX = 0x04, /* FP inexact */ |
|
| 370 |
EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */ |
|
| 371 |
EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */ |
|
| 372 |
EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ |
|
| 373 |
EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ |
|
| 374 |
EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ |
|
| 375 |
EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ |
|
| 376 |
EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ |
|
| 377 |
EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ |
|
| 378 |
EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ |
|
| 363 | 379 |
/* Invalid instruction */ |
| 364 |
EXCP_INVAL_INVAL = 0x10711, /* Invalid instruction */ |
|
| 365 |
EXCP_INVAL_LSWX = 0x10712, /* Invalid lswx instruction */ |
|
| 366 |
EXCP_INVAL_SPR = 0x10713, /* Invalid SPR access */ |
|
| 367 |
EXCP_INVAL_FP = 0x10714, /* Unimplemented mandatory fp instr */ |
|
| 368 |
#endif |
|
| 369 |
EXCP_INVAL = 0x70, /* Invalid instruction */ |
|
| 380 |
EXCP_INVAL = 0x20, |
|
| 381 |
EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ |
|
| 382 |
EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ |
|
| 383 |
EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ |
|
| 384 |
EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ |
|
| 370 | 385 |
/* Privileged instruction */ |
| 371 |
EXCP_PRIV = 0x71, /* Privileged instruction */ |
|
| 386 |
EXCP_PRIV = 0x30, |
|
| 387 |
EXCP_PRIV_OPC = 0x01, |
|
| 388 |
EXCP_PRIV_REG = 0x02, |
|
| 372 | 389 |
/* Trap */ |
| 373 |
EXCP_TRAP = 0x72, /* Trap */ |
|
| 374 |
/* Special cases where we want to stop translation */ |
|
| 375 |
EXCP_MTMSR = 0x103, /* mtmsr instruction: */ |
|
| 376 |
/* may change privilege level */ |
|
| 377 |
EXCP_BRANCH = 0x104, /* branch instruction */ |
|
| 390 |
EXCP_TRAP = 0x40, |
|
| 378 | 391 |
}; |
| 379 | 392 |
|
| 393 |
/*****************************************************************************/ |
|
| 394 |
|
|
| 380 | 395 |
#endif /* !defined (__CPU_PPC_H__) */ |
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