Revision 9a64fbe4 target-ppc/cpu.h

b/target-ppc/cpu.h
25 25

  
26 26
#include "cpu-defs.h"
27 27

  
28
//#define USE_OPEN_FIRMWARE
29

  
28 30
/***                          Sign extend constants                        ***/
29 31
/* 8 to 32 bits */
30 32
static inline int32_t s_ext8 (uint8_t value)
......
54 56
#include "config.h"
55 57
#include <setjmp.h>
56 58

  
57
/* Floting point status and control register */
58
#define FPSCR_FX     31
59
#define FPSCR_FEX    30
60
#define FPSCR_VX     29
61
#define FPSCR_OX     28
62
#define FPSCR_UX     27
63
#define FPSCR_ZX     26
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#define FPSCR_XX     25
65
#define FPSCR_VXSNAN 24
66
#define FPSCR_VXISI  26
67
#define FPSCR_VXIDI  25
68
#define FPSCR_VXZDZ  21
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#define FPSCR_VXIMZ  20
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/* Instruction types */
60
enum {
61
    PPC_NONE     = 0x0000,
62
    PPC_INTEGER  = 0x0001, /* CPU has integer operations instructions        */
63
    PPC_FLOAT    = 0x0002, /* CPU has floating point operations instructions */
64
    PPC_FLOW     = 0x0004, /* CPU has flow control instructions              */
65
    PPC_MEM      = 0x0008, /* CPU has virtual memory instructions            */
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    PPC_RES      = 0x0010, /* CPU has ld/st with reservation instructions    */
67
    PPC_CACHE    = 0x0020, /* CPU has cache control instructions             */
68
    PPC_MISC     = 0x0040, /* CPU has spr/msr access instructions            */
69
    PPC_EXTERN   = 0x0080, /* CPU has external control instructions          */
70
    PPC_SEGMENT  = 0x0100, /* CPU has memory segment instructions            */
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    PPC_CACHE_OPT= 0x0200,
72
    PPC_FLOAT_OPT= 0x0400,
73
    PPC_MEM_OPT  = 0x0800,
74
};
70 75

  
71
#define FPSCR_VXVC   18
72
#define FPSCR_FR     17
73
#define FPSCR_FI     16
74
#define FPSCR_FPRF   11
75
#define FPSCR_VXSOFT 9
76
#define FPSCR_VXSQRT 8
77
#define FPSCR_VXCVI  7
78
#define FPSCR_OE     6
79
#define FPSCR_UE     5
80
#define FPSCR_ZE     4
81
#define FPSCR_XE     3
82
#define FPSCR_NI     2
83
#define FPSCR_RN     0
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#define fpscr_fx     env->fpscr[FPSCR_FX]
85
#define fpscr_fex    env->fpscr[FPSCR_FEX]
86
#define fpscr_vx     env->fpscr[FPSCR_VX]
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#define fpscr_ox     env->fpscr[FPSCR_OX]
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#define fpscr_ux     env->fpscr[FPSCR_UX]
89
#define fpscr_zx     env->fpscr[FPSCR_ZX]
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#define fpscr_xx     env->fpscr[FPSCR_XX]
91
#define fpscr_vsxnan env->fpscr[FPSCR_VXSNAN]
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#define fpscr_vxisi  env->fpscr[FPSCR_VXISI]
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#define fpscr_vxidi  env->fpscr[FPSCR_VXIDI]
94
#define fpscr_vxzdz  env->fpscr[FPSCR_VXZDZ]
95
#define fpscr_vximz  env->fpscr[FPSCR_VXIMZ]
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#define fpscr_fr     env->fpscr[FPSCR_FR]
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#define fpscr_fi     env->fpscr[FPSCR_FI]
98
#define fpscr_fprf   env->fpscr[FPSCR_FPRF]
99
#define fpscr_vxsoft env->fpscr[FPSCR_VXSOFT]
100
#define fpscr_vxsqrt env->fpscr[FPSCR_VXSQRT]
101
#define fpscr_oe     env->fpscr[FPSCR_OE]
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#define fpscr_ue     env->fpscr[FPSCR_UE]
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#define fpscr_ze     env->fpscr[FPSCR_ZE]
104
#define fpscr_xe     env->fpscr[FPSCR_XE]
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#define fpscr_ni     env->fpscr[FPSCR_NI]
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#define fpscr_rn     env->fpscr[FPSCR_RN]
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#define PPC_COMMON  (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM |           \
77
                     PPC_RES | PPC_CACHE | PPC_MISC | PPC_SEGMENT)
78
/* PPC 740/745/750/755 (aka G3) has external access instructions */
79
#define PPC_750 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM |               \
80
                 PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT)
107 81

  
108 82
/* Supervisor mode registers */
109 83
/* Machine state register */
......
139 113
#define msr_le  env->msr[MSR_LE]
140 114

  
141 115
/* Segment registers */
142
typedef struct ppc_sr_t {
143
    uint32_t t:1;
144
    uint32_t ks:1;
145
    uint32_t kp:1;
146
    uint32_t n:1;
147
    uint32_t res:4;
148
    uint32_t vsid:24;
149
} ppc_sr_t;
150

  
151 116
typedef struct CPUPPCState {
152 117
    /* general purpose registers */
153 118
    uint32_t gpr[32];
154 119
    /* floating point registers */
155 120
    double fpr[32];
156 121
    /* segment registers */
157
    ppc_sr_t sr[16];
158
    /* special purpose registers */
159
    uint32_t spr[1024];
122
    uint32_t sdr1;
123
    uint32_t sr[16];
160 124
    /* XER */
161
    uint8_t xer[32];
125
    uint8_t xer[4];
162 126
    /* Reservation address */
163 127
    uint32_t reserve;
164 128
    /* machine state register */
......
166 130
    /* condition register */
167 131
    uint8_t crf[8];
168 132
    /* floating point status and control register */
169
    uint8_t fpscr[32];
133
    uint8_t fpscr[8];
170 134
    uint32_t nip;
171
    /* CPU exception code */
172
    uint32_t exception;
173

  
135
    /* special purpose registers */
136
    uint32_t lr;
137
    uint32_t ctr;
138
    /* Time base */
139
    uint32_t tb[2];
140
    /* decrementer */
141
    uint32_t decr;
142
    /* BATs */
143
    uint32_t DBAT[2][8];
144
    uint32_t IBAT[2][8];
145
    /* all others */
146
    uint32_t spr[1024];
174 147
    /* qemu dedicated */
175 148
     /* temporary float registers */
176 149
    double ft0;
......
180 153
    jmp_buf jmp_env;
181 154
    int exception_index;
182 155
    int error_code;
156
    uint32_t exceptions; /* exception queue */
157
    uint32_t errors[16];
183 158
    int user_mode_only; /* user mode only simulation */
184 159
    struct TranslationBlock *current_tb; /* currently executing TB */
185

  
160
    /* soft mmu support */
161
    /* 0 = kernel, 1 = user */
162
    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
163
    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
186 164
    /* user data */
187 165
    void *opaque;
188 166
} CPUPPCState;
......
198 176
                           void *puc);
199 177

  
200 178
void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags);
179
void cpu_loop_exit(void);
180
void dump_stack (CPUPPCState *env);
181
uint32_t _load_xer (void);
182
void _store_xer (uint32_t value);
183
uint32_t _load_msr (void);
184
void _store_msr (uint32_t value);
185
void do_interrupt (CPUPPCState *env);
201 186

  
202 187
#define TARGET_PAGE_BITS 12
203 188
#include "cpu-all.h"
204 189

  
205 190
#define ugpr(n) (env->gpr[n])
206
#define fpr(n) (env->fpr[n])
191
#define fprd(n) (env->fpr[n])
192
#define fprs(n) ((float)env->fpr[n])
193
#define fpru(n) ((uint32_t)env->fpr[n])
194
#define fpri(n) ((int32_t)env->fpr[n])
207 195

  
208 196
#define SPR_ENCODE(sprn)                               \
209 197
(((sprn) >> 5) | (((sprn) & 0x1F) << 5))
210 198

  
211 199
/* User mode SPR */
212 200
#define spr(n) env->spr[n]
213
//#define XER    spr[1]
214
#define XER env->xer
215 201
#define XER_SO 31
216 202
#define XER_OV 30
217 203
#define XER_CA 29
218 204
#define XER_BC 0
219
#define xer_so env->xer[XER_SO]
220
#define xer_ov env->xer[XER_OV]
221
#define xer_ca env->xer[XER_CA]
222
#define xer_bc env->xer[XER_BC]
205
#define xer_so env->xer[3]
206
#define xer_ov env->xer[2]
207
#define xer_ca env->xer[1]
208
#define xer_bc env->xer[0]
223 209

  
224
#define LR     spr[SPR_ENCODE(8)]
225
#define CTR    spr[SPR_ENCODE(9)]
210
#define XER    SPR_ENCODE(1)
211
#define LR     SPR_ENCODE(8)
212
#define CTR    SPR_ENCODE(9)
226 213
/* VEA mode SPR */
227
#define V_TBL  spr[SPR_ENCODE(268)]
228
#define V_TBU  spr[SPR_ENCODE(269)]
214
#define V_TBL  SPR_ENCODE(268)
215
#define V_TBU  SPR_ENCODE(269)
229 216
/* supervisor mode SPR */
230
#define DSISR  spr[SPR_ENCODE(18)]
231
#define DAR    spr[SPR_ENCODE(19)]
232
#define DEC    spr[SPR_ENCODE(22)]
233
#define SDR1   spr[SPR_ENCODE(25)]
234
typedef struct ppc_sdr1_t {
235
    uint32_t htaborg:16;
236
    uint32_t res:7;
237
    uint32_t htabmask:9;
238
} ppc_sdr1_t;
239
#define SRR0   spr[SPR_ENCODE(26)]
240
#define SRR0_MASK 0xFFFFFFFC
241
#define SRR1   spr[SPR_ENCODE(27)]
242
#define SPRG0  spr[SPR_ENCODE(272)]
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#define SPRG1  spr[SPR_ENCODE(273)]
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#define SPRG2  spr[SPR_ENCODE(274)]
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#define SPRG3  spr[SPR_ENCODE(275)]
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#define EAR    spr[SPR_ENCODE(282)]
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typedef struct ppc_ear_t {
248
    uint32_t e:1;
249
    uint32_t res:25;
250
    uint32_t rid:6;
251
} ppc_ear_t;
252
#define TBL    spr[SPR_ENCODE(284)]
253
#define TBU    spr[SPR_ENCODE(285)]
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#define PVR    spr[SPR_ENCODE(287)]
255
typedef struct ppc_pvr_t {
256
    uint32_t version:16;
257
    uint32_t revision:16;
258
} ppc_pvr_t;
259
#define IBAT0U spr[SPR_ENCODE(528)]
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#define IBAT0L spr[SPR_ENCODE(529)]
261
#define IBAT1U spr[SPR_ENCODE(530)]
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#define IBAT1L spr[SPR_ENCODE(531)]
263
#define IBAT2U spr[SPR_ENCODE(532)]
264
#define IBAT2L spr[SPR_ENCODE(533)]
265
#define IBAT3U spr[SPR_ENCODE(534)]
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#define IBAT3L spr[SPR_ENCODE(535)]
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#define DBAT0U spr[SPR_ENCODE(536)]
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#define DBAT0L spr[SPR_ENCODE(537)]
269
#define DBAT1U spr[SPR_ENCODE(538)]
270
#define DBAT1L spr[SPR_ENCODE(539)]
271
#define DBAT2U spr[SPR_ENCODE(540)]
272
#define DBAT2L spr[SPR_ENCODE(541)]
273
#define DBAT3U spr[SPR_ENCODE(542)]
274
#define DBAT3L spr[SPR_ENCODE(543)]
275
typedef struct ppc_ubat_t {
276
    uint32_t bepi:15;
277
    uint32_t res:4;
278
    uint32_t bl:11;
279
    uint32_t vs:1;
280
    uint32_t vp:1;
281
} ppc_ubat_t;
282
typedef struct ppc_lbat_t {
283
    uint32_t brpn:15;
284
    uint32_t res0:10;
285
    uint32_t w:1;
286
    uint32_t i:1;
287
    uint32_t m:1;
288
    uint32_t g:1;
289
    uint32_t res1:1;
290
    uint32_t pp:2;
291
} ppc_lbat_t;
292
#define DABR   spr[SPR_ENCODE(1013)]
217
#define DSISR  SPR_ENCODE(18)
218
#define DAR    SPR_ENCODE(19)
219
#define DECR   SPR_ENCODE(22)
220
#define SDR1   SPR_ENCODE(25)
221
#define SRR0   SPR_ENCODE(26)
222
#define SRR1   SPR_ENCODE(27)
223
#define SPRG0  SPR_ENCODE(272)
224
#define SPRG1  SPR_ENCODE(273)
225
#define SPRG2  SPR_ENCODE(274)
226
#define SPRG3  SPR_ENCODE(275)
227
#define SPRG4  SPR_ENCODE(276)
228
#define SPRG5  SPR_ENCODE(277)
229
#define SPRG6  SPR_ENCODE(278)
230
#define SPRG7  SPR_ENCODE(279)
231
#define ASR    SPR_ENCODE(280)
232
#define EAR    SPR_ENCODE(282)
233
#define O_TBL  SPR_ENCODE(284)
234
#define O_TBU  SPR_ENCODE(285)
235
#define PVR    SPR_ENCODE(287)
236
#define IBAT0U SPR_ENCODE(528)
237
#define IBAT0L SPR_ENCODE(529)
238
#define IBAT1U SPR_ENCODE(530)
239
#define IBAT1L SPR_ENCODE(531)
240
#define IBAT2U SPR_ENCODE(532)
241
#define IBAT2L SPR_ENCODE(533)
242
#define IBAT3U SPR_ENCODE(534)
243
#define IBAT3L SPR_ENCODE(535)
244
#define DBAT0U SPR_ENCODE(536)
245
#define DBAT0L SPR_ENCODE(537)
246
#define DBAT1U SPR_ENCODE(538)
247
#define DBAT1L SPR_ENCODE(539)
248
#define DBAT2U SPR_ENCODE(540)
249
#define DBAT2L SPR_ENCODE(541)
250
#define DBAT3U SPR_ENCODE(542)
251
#define DBAT3L SPR_ENCODE(543)
252
#define IBAT4U SPR_ENCODE(560)
253
#define IBAT4L SPR_ENCODE(561)
254
#define IBAT5U SPR_ENCODE(562)
255
#define IBAT5L SPR_ENCODE(563)
256
#define IBAT6U SPR_ENCODE(564)
257
#define IBAT6L SPR_ENCODE(565)
258
#define IBAT7U SPR_ENCODE(566)
259
#define IBAT7L SPR_ENCODE(567)
260
#define DBAT4U SPR_ENCODE(568)
261
#define DBAT4L SPR_ENCODE(569)
262
#define DBAT5U SPR_ENCODE(570)
263
#define DBAT5L SPR_ENCODE(571)
264
#define DBAT6U SPR_ENCODE(572)
265
#define DBAT6L SPR_ENCODE(573)
266
#define DBAT7U SPR_ENCODE(574)
267
#define DBAT7L SPR_ENCODE(575)
268
#define DABR   SPR_ENCODE(1013)
293 269
#define DABR_MASK 0xFFFFFFF8
294
typedef struct ppc_dabr_t {
295
    uint32_t dab:29;
296
    uint32_t bt:1;
297
    uint32_t dw:1;
298
    uint32_t dr:1;
299
} ppc_dabr_t;
300
#define FPECR  spr[SPR_ENCODE(1022)]
301
#define PIR    spr[SPR_ENCODE(1023)]
270
#define FPECR  SPR_ENCODE(1022)
271
#define PIR    SPR_ENCODE(1023)
302 272

  
303 273
#define TARGET_PAGE_BITS 12
304 274
#include "cpu-all.h"
......
307 277
int cpu_ppc_exec(CPUPPCState *s);
308 278
void cpu_ppc_close(CPUPPCState *s);
309 279
void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags);
280
void PPC_init_hw (CPUPPCState *env, uint32_t mem_size,
281
                  uint32_t kernel_addr, uint32_t kernel_size,
282
                  uint32_t stack_addr, int boot_device);
310 283

  
311
/* Exeptions */
284
/* Memory access type :
285
 * may be needed for precise access rights control and precise exceptions.
286
 */
312 287
enum {
313
    EXCP_NONE          = 0x00,
288
    /* 1 bit to define user level / supervisor access */
289
    ACCESS_USER  = 0x00,
290
    ACCESS_SUPER = 0x01,
291
    /* Type of instruction that generated the access */
292
    ACCESS_CODE  = 0x10, /* Code fetch access                */
293
    ACCESS_INT   = 0x20, /* Integer load/store access        */
294
    ACCESS_FLOAT = 0x30, /* floating point load/store access */
295
    ACCESS_RES   = 0x40, /* load/store with reservation      */
296
    ACCESS_EXT   = 0x50, /* external access                  */
297
    ACCESS_CACHE = 0x60, /* Cache manipulation               */
298
};
299

  
300
/*****************************************************************************/
301
/* Exceptions */
302
enum {
303
    EXCP_NONE          = -1,
314 304
    /* PPC hardware exceptions : exception vector / 0x100 */
315 305
    EXCP_RESET         = 0x01, /* System reset                     */
316 306
    EXCP_MACHINE_CHECK = 0x02, /* Machine check exception          */
......
326 316
    EXCP_SYSCALL       = 0x0C, /* System call                      */
327 317
    EXCP_TRACE         = 0x0D, /* Trace exception (optional)       */
328 318
    EXCP_FP_ASSIST     = 0x0E, /* Floating-point assist (optional) */
329
#if 0
330
    /* Exeption subtypes for EXCP_DSI */
331
    EXCP_DSI_TRANSLATE = 0x10301, /* Data address can't be translated */
332
    EXCP_DSI_NOTSUP    = 0x10302, /* Access type not supported        */
333
    EXCP_DSI_PROT      = 0x10303, /* Memory protection violation      */
334
    EXCP_DSI_EXTERNAL  = 0x10304, /* External access disabled         */
335
    EXCP_DSI_DABR      = 0x10305, /* Data address breakpoint          */
336
    /* Exeption subtypes for EXCP_ISI */
337
    EXCP_ISI_TRANSLATE = 0x10401, /* Code address can't be translated */
338
    EXCP_ISI_NOTSUP    = 0x10402, /* Access type not supported        */
339
    EXCP_ISI_PROT      = 0x10403, /* Memory protection violation      */
340
    EXCP_ISI_GUARD     = 0x10404, /* Fetch into guarded memory        */
341
    /* Exeption subtypes for EXCP_ALIGN */
342
    EXCP_ALIGN_FP      = 0x10601, /* FP alignment exception           */
343
    EXCP_ALIGN_LST     = 0x10602, /* Unaligned memory load/store      */
344
    EXCP_ALIGN_LE      = 0x10603, /* Unaligned little-endian access   */
345
    EXCP_ALIGN_PROT    = 0x10604, /* Access cross protection boundary */
346
    EXCP_ALIGN_BAT     = 0x10605, /* Access cross a BAT/seg boundary  */
347
    EXCP_ALIGN_CACHE   = 0x10606, /* Impossible dcbz access           */
348
    /* Exeption subtypes for EXCP_PROGRAM */
319
    /* MPC740/745/750 & IBM 750 */
320
    EXCP_PERF          = 0x0F,  /* Performance monitor              */
321
    EXCP_IABR          = 0x13,  /* Instruction address breakpoint   */
322
    EXCP_SMI           = 0x14,  /* System management interrupt      */
323
    EXCP_THRM          = 0x15,  /* Thermal management interrupt     */
324
    /* MPC755 */
325
    EXCP_TLBMISS       = 0x10,  /* Instruction TLB miss             */
326
    EXCP_TLBMISS_DL    = 0x11,  /* Data TLB miss for load           */
327
    EXCP_TLBMISS_DS    = 0x12,  /* Data TLB miss for store          */
328
    EXCP_PPC_MAX       = 0x16,
329
    /* Qemu exception */
330
    EXCP_OFCALL        = 0x20,  /* Call open-firmware emulator      */
331
    EXCP_RTASCALL      = 0x21,  /* Call RTAS emulator               */
332
    /* Special cases where we want to stop translation */
333
    EXCP_MTMSR         = 0x104, /* mtmsr instruction:               */
334
                                /* may change privilege level       */
335
    EXCP_BRANCH        = 0x108, /* branch instruction               */
336
    EXCP_RFI           = 0x10C, /* return from interrupt            */
337
    EXCP_SYSCALL_USER  = 0x110, /* System call in user mode only    */
338
};
339
/* Error codes */
340
enum {
341
    /* Exception subtypes for EXCP_DSI                              */
342
    EXCP_DSI_TRANSLATE = 0x01,  /* Data address can't be translated */
343
    EXCP_DSI_NOTSUP    = 0x02,  /* Access type not supported        */
344
    EXCP_DSI_PROT      = 0x03,  /* Memory protection violation      */
345
    EXCP_DSI_EXTERNAL  = 0x04,  /* External access disabled         */
346
    EXCP_DSI_DABR      = 0x05,  /* Data address breakpoint          */
347
    /* flags for EXCP_DSI */
348
    EXCP_DSI_DIRECT    = 0x10,
349
    EXCP_DSI_STORE     = 0x20,
350
    EXCP_ECXW          = 0x40,
351
    /* Exception subtypes for EXCP_ISI                              */
352
    EXCP_ISI_TRANSLATE = 0x01,  /* Code address can't be translated */
353
    EXCP_ISI_NOEXEC    = 0x02,  /* Try to fetch from a data segment */
354
    EXCP_ISI_GUARD     = 0x03,  /* Fetch from guarded memory        */
355
    EXCP_ISI_PROT      = 0x04,  /* Memory protection violation      */
356
    /* Exception subtypes for EXCP_ALIGN                            */
357
    EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception           */
358
    EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store */
359
    EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access    */
360
    EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary */
361
    EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary  */
362
    EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access           */
363
    /* Exception subtypes for EXCP_PROGRAM                          */
349 364
    /* FP exceptions */
350
    EXCP_FP_OX         = 0x10701, /* FP overflow                      */
351
    EXCP_FP_UX         = 0x10702, /* FP underflow                     */
352
    EXCP_FP_ZX         = 0x10703, /* FP divide by zero                */
353
    EXCP_FP_XX         = 0x10704, /* FP inexact                       */
354
    EXCP_FP_VXNAN      = 0x10705, /* FP invalid SNaN op               */
355
    EXCP_FP_VXISI      = 0x10706, /* FP invalid infinite substraction */
356
    EXCP_FP_VXIDI      = 0x10707, /* FP invalid infinite divide       */
357
    EXCP_FP_VXZDZ      = 0x10708, /* FP invalid zero divide           */
358
    EXCP_FP_VXIMZ      = 0x10709, /* FP invalid infinite * zero       */
359
    EXCP_FP_VXVC       = 0x1070A, /* FP invalid compare               */
360
    EXCP_FP_VXSOFT     = 0x1070B, /* FP invalid operation             */
361
    EXCP_FP_VXSQRT     = 0x1070C, /* FP invalid square root           */
362
    EXCP_FP_VXCVI      = 0x1070D, /* FP invalid integer conversion    */
365
    EXCP_FP            = 0x10,
366
    EXCP_FP_OX         = 0x01,  /* FP overflow                      */
367
    EXCP_FP_UX         = 0x02,  /* FP underflow                     */
368
    EXCP_FP_ZX         = 0x03,  /* FP divide by zero                */
369
    EXCP_FP_XX         = 0x04,  /* FP inexact                       */
370
    EXCP_FP_VXNAN      = 0x05,  /* FP invalid SNaN op               */
371
    EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite substraction */
372
    EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide       */
373
    EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide           */
374
    EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero       */
375
    EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare               */
376
    EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation             */
377
    EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root           */
378
    EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion    */
363 379
    /* Invalid instruction */
364
    EXCP_INVAL_INVAL   = 0x10711, /* Invalid instruction              */
365
    EXCP_INVAL_LSWX    = 0x10712, /* Invalid lswx instruction         */
366
    EXCP_INVAL_SPR     = 0x10713, /* Invalid SPR access               */
367
    EXCP_INVAL_FP      = 0x10714, /* Unimplemented mandatory fp instr */
368
#endif
369
    EXCP_INVAL         = 0x70,    /* Invalid instruction              */
380
    EXCP_INVAL         = 0x20,
381
    EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction              */
382
    EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction         */
383
    EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access               */
384
    EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr */
370 385
    /* Privileged instruction */
371
    EXCP_PRIV          = 0x71,    /* Privileged instruction           */
386
    EXCP_PRIV          = 0x30,
387
    EXCP_PRIV_OPC      = 0x01,
388
    EXCP_PRIV_REG      = 0x02,
372 389
    /* Trap */
373
    EXCP_TRAP          = 0x72,    /* Trap                             */
374
    /* Special cases where we want to stop translation */
375
    EXCP_MTMSR         = 0x103,   /* mtmsr instruction:               */
376
                                  /* may change privilege level       */
377
    EXCP_BRANCH        = 0x104,   /* branch instruction               */
390
    EXCP_TRAP          = 0x40,
378 391
};
379 392

  
393
/*****************************************************************************/
394

  
380 395
#endif /* !defined (__CPU_PPC_H__) */

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