root / target-mips / translate_init.c @ 9a78eead
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1 | 33d68b5f | ths | /*
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2 | 33d68b5f | ths | * MIPS emulation for qemu: CPU initialisation routines.
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3 | 33d68b5f | ths | *
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4 | 33d68b5f | ths | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 33d68b5f | ths | * Copyright (c) 2007 Herve Poussineau
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6 | 33d68b5f | ths | *
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7 | 33d68b5f | ths | * This library is free software; you can redistribute it and/or
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8 | 33d68b5f | ths | * modify it under the terms of the GNU Lesser General Public
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9 | 33d68b5f | ths | * License as published by the Free Software Foundation; either
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10 | 33d68b5f | ths | * version 2 of the License, or (at your option) any later version.
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11 | 33d68b5f | ths | *
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12 | 33d68b5f | ths | * This library is distributed in the hope that it will be useful,
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13 | 33d68b5f | ths | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 33d68b5f | ths | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 33d68b5f | ths | * Lesser General Public License for more details.
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16 | 33d68b5f | ths | *
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17 | 33d68b5f | ths | * You should have received a copy of the GNU Lesser General Public
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18 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | 33d68b5f | ths | */
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20 | 33d68b5f | ths | |
21 | 3953d786 | ths | /* CPU / CPU family specific config register values. */
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22 | 3953d786 | ths | |
23 | 6d35524c | ths | /* Have config1, uncached coherency */
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24 | 3953d786 | ths | #define MIPS_CONFIG0 \
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25 | 6d35524c | ths | ((1 << CP0C0_M) | (0x2 << CP0C0_K0)) |
26 | 3953d786 | ths | |
27 | ae5d8053 | ths | /* Have config2, no coprocessor2 attached, no MDMX support attached,
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28 | 3953d786 | ths | no performance counters, watch registers present,
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29 | 3953d786 | ths | no code compression, EJTAG present, no FPU */
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30 | 3953d786 | ths | #define MIPS_CONFIG1 \
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31 | fcb4a419 | ths | ((1 << CP0C1_M) | \
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32 | 3953d786 | ths | (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ |
33 | 3953d786 | ths | (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ |
34 | 3953d786 | ths | (0 << CP0C1_FP))
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35 | 3953d786 | ths | |
36 | 3953d786 | ths | /* Have config3, no tertiary/secondary caches implemented */
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37 | 3953d786 | ths | #define MIPS_CONFIG2 \
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38 | 3953d786 | ths | ((1 << CP0C2_M))
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39 | 3953d786 | ths | |
40 | 6d35524c | ths | /* No config4, no DSP ASE, no large physaddr (PABITS),
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41 | 3953d786 | ths | no external interrupt controller, no vectored interupts,
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42 | ead9360e | ths | no 1kb pages, no SmartMIPS ASE, no trace logic */
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43 | 3953d786 | ths | #define MIPS_CONFIG3 \
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44 | 3953d786 | ths | ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ |
45 | 3953d786 | ths | (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ |
46 | ead9360e | ths | (0 << CP0C3_SM) | (0 << CP0C3_TL)) |
47 | 3953d786 | ths | |
48 | 6d35524c | ths | /* MMU types, the first four entries have the same layout as the
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49 | 6d35524c | ths | CP0C0_MT field. */
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50 | 6d35524c | ths | enum mips_mmu_types {
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51 | 6d35524c | ths | MMU_TYPE_NONE, |
52 | 6d35524c | ths | MMU_TYPE_R4000, |
53 | 6d35524c | ths | MMU_TYPE_RESERVED, |
54 | 6d35524c | ths | MMU_TYPE_FMT, |
55 | 6d35524c | ths | MMU_TYPE_R3000, |
56 | 6d35524c | ths | MMU_TYPE_R6000, |
57 | 6d35524c | ths | MMU_TYPE_R8000 |
58 | 6d35524c | ths | }; |
59 | 6d35524c | ths | |
60 | c227f099 | Anthony Liguori | struct mips_def_t {
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61 | 50366fe9 | ths | const char *name; |
62 | 33d68b5f | ths | int32_t CP0_PRid; |
63 | 33d68b5f | ths | int32_t CP0_Config0; |
64 | 33d68b5f | ths | int32_t CP0_Config1; |
65 | 3953d786 | ths | int32_t CP0_Config2; |
66 | 3953d786 | ths | int32_t CP0_Config3; |
67 | 34ee2ede | ths | int32_t CP0_Config6; |
68 | 34ee2ede | ths | int32_t CP0_Config7; |
69 | 2a6e32dd | Aurelien Jarno | target_ulong CP0_LLAddr_rw_bitmask; |
70 | 2a6e32dd | Aurelien Jarno | int CP0_LLAddr_shift;
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71 | 2f644545 | ths | int32_t SYNCI_Step; |
72 | 2f644545 | ths | int32_t CCRes; |
73 | ead9360e | ths | int32_t CP0_Status_rw_bitmask; |
74 | ead9360e | ths | int32_t CP0_TCStatus_rw_bitmask; |
75 | ead9360e | ths | int32_t CP0_SRSCtl; |
76 | 3953d786 | ths | int32_t CP1_fcr0; |
77 | e034e2c3 | ths | int32_t SEGBITS; |
78 | 6d35524c | ths | int32_t PABITS; |
79 | ead9360e | ths | int32_t CP0_SRSConf0_rw_bitmask; |
80 | ead9360e | ths | int32_t CP0_SRSConf0; |
81 | ead9360e | ths | int32_t CP0_SRSConf1_rw_bitmask; |
82 | ead9360e | ths | int32_t CP0_SRSConf1; |
83 | ead9360e | ths | int32_t CP0_SRSConf2_rw_bitmask; |
84 | ead9360e | ths | int32_t CP0_SRSConf2; |
85 | ead9360e | ths | int32_t CP0_SRSConf3_rw_bitmask; |
86 | ead9360e | ths | int32_t CP0_SRSConf3; |
87 | ead9360e | ths | int32_t CP0_SRSConf4_rw_bitmask; |
88 | ead9360e | ths | int32_t CP0_SRSConf4; |
89 | e189e748 | ths | int insn_flags;
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90 | 6d35524c | ths | enum mips_mmu_types mmu_type;
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91 | 33d68b5f | ths | }; |
92 | 33d68b5f | ths | |
93 | 33d68b5f | ths | /*****************************************************************************/
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94 | 33d68b5f | ths | /* MIPS CPU definitions */
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95 | c227f099 | Anthony Liguori | static const mips_def_t mips_defs[] = |
96 | 33d68b5f | ths | { |
97 | 33d68b5f | ths | { |
98 | 33d68b5f | ths | .name = "4Kc",
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99 | 33d68b5f | ths | .CP0_PRid = 0x00018000,
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100 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
101 | ae5d8053 | ths | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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102 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
103 | d19954f4 | Nathan Froyd | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
104 | ab3aee26 | Stefan Weil | (0 << CP0C1_CA),
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105 | 3953d786 | ths | .CP0_Config2 = MIPS_CONFIG2, |
106 | 3953d786 | ths | .CP0_Config3 = MIPS_CONFIG3, |
107 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
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108 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
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109 | 2f644545 | ths | .SYNCI_Step = 32,
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110 | 2f644545 | ths | .CCRes = 2,
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111 | ead9360e | ths | .CP0_Status_rw_bitmask = 0x1278FF17,
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112 | 6d35524c | ths | .SEGBITS = 32,
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113 | 6d35524c | ths | .PABITS = 32,
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114 | 73642f5b | Stefan Weil | .insn_flags = CPU_MIPS32, |
115 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
116 | 33d68b5f | ths | }, |
117 | 33d68b5f | ths | { |
118 | 8d162c2b | ths | .name = "4Km",
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119 | 8d162c2b | ths | .CP0_PRid = 0x00018300,
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120 | 8d162c2b | ths | /* Config1 implemented, fixed mapping MMU,
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121 | 8d162c2b | ths | no virtual icache, uncached coherency. */
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122 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |
123 | 8d162c2b | ths | .CP0_Config1 = MIPS_CONFIG1 | |
124 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
125 | d19954f4 | Nathan Froyd | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
126 | d19954f4 | Nathan Froyd | (1 << CP0C1_CA),
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127 | 8d162c2b | ths | .CP0_Config2 = MIPS_CONFIG2, |
128 | 8d162c2b | ths | .CP0_Config3 = MIPS_CONFIG3, |
129 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
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130 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
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131 | 8d162c2b | ths | .SYNCI_Step = 32,
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132 | 8d162c2b | ths | .CCRes = 2,
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133 | 8d162c2b | ths | .CP0_Status_rw_bitmask = 0x1258FF17,
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134 | 6d35524c | ths | .SEGBITS = 32,
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135 | 6d35524c | ths | .PABITS = 32,
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136 | 8d162c2b | ths | .insn_flags = CPU_MIPS32 | ASE_MIPS16, |
137 | 6d35524c | ths | .mmu_type = MMU_TYPE_FMT, |
138 | 8d162c2b | ths | }, |
139 | 8d162c2b | ths | { |
140 | 34ee2ede | ths | .name = "4KEcR1",
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141 | 33d68b5f | ths | .CP0_PRid = 0x00018400,
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142 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
143 | ae5d8053 | ths | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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144 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
145 | d19954f4 | Nathan Froyd | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
146 | ab3aee26 | Stefan Weil | (0 << CP0C1_CA),
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147 | 34ee2ede | ths | .CP0_Config2 = MIPS_CONFIG2, |
148 | 34ee2ede | ths | .CP0_Config3 = MIPS_CONFIG3, |
149 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
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150 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
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151 | 2f644545 | ths | .SYNCI_Step = 32,
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152 | 2f644545 | ths | .CCRes = 2,
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153 | ead9360e | ths | .CP0_Status_rw_bitmask = 0x1278FF17,
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154 | 6d35524c | ths | .SEGBITS = 32,
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155 | 6d35524c | ths | .PABITS = 32,
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156 | 73642f5b | Stefan Weil | .insn_flags = CPU_MIPS32, |
157 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
158 | 34ee2ede | ths | }, |
159 | 34ee2ede | ths | { |
160 | 8d162c2b | ths | .name = "4KEmR1",
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161 | 8d162c2b | ths | .CP0_PRid = 0x00018500,
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162 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |
163 | 8d162c2b | ths | .CP0_Config1 = MIPS_CONFIG1 | |
164 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
165 | d19954f4 | Nathan Froyd | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
166 | d19954f4 | Nathan Froyd | (1 << CP0C1_CA),
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167 | 8d162c2b | ths | .CP0_Config2 = MIPS_CONFIG2, |
168 | 8d162c2b | ths | .CP0_Config3 = MIPS_CONFIG3, |
169 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
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170 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
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171 | 8d162c2b | ths | .SYNCI_Step = 32,
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172 | 8d162c2b | ths | .CCRes = 2,
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173 | 8d162c2b | ths | .CP0_Status_rw_bitmask = 0x1258FF17,
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174 | 6d35524c | ths | .SEGBITS = 32,
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175 | 6d35524c | ths | .PABITS = 32,
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176 | 8d162c2b | ths | .insn_flags = CPU_MIPS32 | ASE_MIPS16, |
177 | 6d35524c | ths | .mmu_type = MMU_TYPE_FMT, |
178 | 8d162c2b | ths | }, |
179 | 8d162c2b | ths | { |
180 | 34ee2ede | ths | .name = "4KEc",
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181 | 34ee2ede | ths | .CP0_PRid = 0x00019000,
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182 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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183 | 6d35524c | ths | (MMU_TYPE_R4000 << CP0C0_MT), |
184 | ae5d8053 | ths | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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185 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
186 | d19954f4 | Nathan Froyd | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
187 | ab3aee26 | Stefan Weil | (0 << CP0C1_CA),
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188 | 34ee2ede | ths | .CP0_Config2 = MIPS_CONFIG2, |
189 | ead9360e | ths | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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190 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
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191 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
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192 | 2f644545 | ths | .SYNCI_Step = 32,
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193 | 2f644545 | ths | .CCRes = 2,
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194 | ead9360e | ths | .CP0_Status_rw_bitmask = 0x1278FF17,
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195 | 6d35524c | ths | .SEGBITS = 32,
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196 | 6d35524c | ths | .PABITS = 32,
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197 | 73642f5b | Stefan Weil | .insn_flags = CPU_MIPS32R2, |
198 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
199 | 34ee2ede | ths | }, |
200 | 34ee2ede | ths | { |
201 | 3e4587d5 | ths | .name = "4KEm",
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202 | 3e4587d5 | ths | .CP0_PRid = 0x00019100,
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203 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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204 | 6958549d | aurel32 | (MMU_TYPE_FMT << CP0C0_MT), |
205 | 3e4587d5 | ths | .CP0_Config1 = MIPS_CONFIG1 | |
206 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
207 | d19954f4 | Nathan Froyd | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
208 | d19954f4 | Nathan Froyd | (1 << CP0C1_CA),
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209 | 3e4587d5 | ths | .CP0_Config2 = MIPS_CONFIG2, |
210 | 3e4587d5 | ths | .CP0_Config3 = MIPS_CONFIG3, |
211 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
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212 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
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213 | 3e4587d5 | ths | .SYNCI_Step = 32,
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214 | 3e4587d5 | ths | .CCRes = 2,
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215 | 3e4587d5 | ths | .CP0_Status_rw_bitmask = 0x1258FF17,
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216 | 6d35524c | ths | .SEGBITS = 32,
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217 | 6d35524c | ths | .PABITS = 32,
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218 | 3e4587d5 | ths | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
219 | 6d35524c | ths | .mmu_type = MMU_TYPE_FMT, |
220 | 3e4587d5 | ths | }, |
221 | 3e4587d5 | ths | { |
222 | 34ee2ede | ths | .name = "24Kc",
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223 | 34ee2ede | ths | .CP0_PRid = 0x00019300,
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224 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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225 | 6958549d | aurel32 | (MMU_TYPE_R4000 << CP0C0_MT), |
226 | ae5d8053 | ths | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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227 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
228 | d19954f4 | Nathan Froyd | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
229 | d19954f4 | Nathan Froyd | (1 << CP0C1_CA),
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230 | 3953d786 | ths | .CP0_Config2 = MIPS_CONFIG2, |
231 | ead9360e | ths | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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232 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
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233 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
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234 | 2f644545 | ths | .SYNCI_Step = 32,
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235 | 2f644545 | ths | .CCRes = 2,
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236 | ead9360e | ths | /* No DSP implemented. */
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237 | 671880e6 | ths | .CP0_Status_rw_bitmask = 0x1278FF1F,
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238 | 6d35524c | ths | .SEGBITS = 32,
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239 | 6d35524c | ths | .PABITS = 32,
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240 | 3e4587d5 | ths | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
241 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
242 | 33d68b5f | ths | }, |
243 | 33d68b5f | ths | { |
244 | 33d68b5f | ths | .name = "24Kf",
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245 | 33d68b5f | ths | .CP0_PRid = 0x00019300,
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246 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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247 | 6d35524c | ths | (MMU_TYPE_R4000 << CP0C0_MT), |
248 | ae5d8053 | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
249 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
250 | d19954f4 | Nathan Froyd | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
251 | d19954f4 | Nathan Froyd | (1 << CP0C1_CA),
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252 | 3953d786 | ths | .CP0_Config2 = MIPS_CONFIG2, |
253 | ead9360e | ths | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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254 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
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255 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
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256 | 2f644545 | ths | .SYNCI_Step = 32,
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257 | 2f644545 | ths | .CCRes = 2,
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258 | ead9360e | ths | /* No DSP implemented. */
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259 | 671880e6 | ths | .CP0_Status_rw_bitmask = 0x3678FF1F,
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260 | 5a5012ec | ths | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
261 | 5a5012ec | ths | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
262 | 6d35524c | ths | .SEGBITS = 32,
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263 | 6d35524c | ths | .PABITS = 32,
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264 | 3e4587d5 | ths | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
265 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
266 | 33d68b5f | ths | }, |
267 | ead9360e | ths | { |
268 | ead9360e | ths | .name = "34Kf",
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269 | ead9360e | ths | .CP0_PRid = 0x00019500,
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270 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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271 | 6958549d | aurel32 | (MMU_TYPE_R4000 << CP0C0_MT), |
272 | ead9360e | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
273 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
274 | d19954f4 | Nathan Froyd | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
275 | d19954f4 | Nathan Froyd | (1 << CP0C1_CA),
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276 | ead9360e | ths | .CP0_Config2 = MIPS_CONFIG2, |
277 | ead9360e | ths | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT), |
278 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
|
279 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 0,
|
280 | ead9360e | ths | .SYNCI_Step = 32,
|
281 | ead9360e | ths | .CCRes = 2,
|
282 | ead9360e | ths | /* No DSP implemented. */
|
283 | 671880e6 | ths | .CP0_Status_rw_bitmask = 0x3678FF1F,
|
284 | ead9360e | ths | /* No DSP implemented. */
|
285 | ead9360e | ths | .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | |
286 | ead9360e | ths | (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | |
287 | ead9360e | ths | (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | |
288 | ead9360e | ths | (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) | |
289 | ead9360e | ths | (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) | |
290 | ead9360e | ths | (0xff << CP0TCSt_TASID),
|
291 | ead9360e | ths | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
292 | ead9360e | ths | (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), |
293 | ead9360e | ths | .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
|
294 | ead9360e | ths | .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
|
295 | ead9360e | ths | .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | |
296 | ead9360e | ths | (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), |
297 | ead9360e | ths | .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
|
298 | ead9360e | ths | .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | |
299 | ead9360e | ths | (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), |
300 | ead9360e | ths | .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
|
301 | ead9360e | ths | .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | |
302 | ead9360e | ths | (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), |
303 | ead9360e | ths | .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
|
304 | ead9360e | ths | .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | |
305 | ead9360e | ths | (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), |
306 | ead9360e | ths | .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
|
307 | ead9360e | ths | .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
|
308 | ead9360e | ths | (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), |
309 | 6d35524c | ths | .SEGBITS = 32,
|
310 | 6d35524c | ths | .PABITS = 32,
|
311 | 7385ac0b | ths | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, |
312 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
313 | ead9360e | ths | }, |
314 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
315 | 33d68b5f | ths | { |
316 | 33d68b5f | ths | .name = "R4000",
|
317 | 33d68b5f | ths | .CP0_PRid = 0x00000400,
|
318 | 6d35524c | ths | /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
|
319 | 6d35524c | ths | .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), |
320 | 6958549d | aurel32 | /* Note: Config1 is only used internally, the R4000 has only Config0. */
|
321 | 6d35524c | ths | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
322 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
|
323 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
|
324 | 2f644545 | ths | .SYNCI_Step = 16,
|
325 | 2f644545 | ths | .CCRes = 2,
|
326 | ead9360e | ths | .CP0_Status_rw_bitmask = 0x3678FFFF,
|
327 | 6958549d | aurel32 | /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
|
328 | c9c1a064 | ths | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), |
329 | e034e2c3 | ths | .SEGBITS = 40,
|
330 | 6d35524c | ths | .PABITS = 36,
|
331 | e189e748 | ths | .insn_flags = CPU_MIPS3, |
332 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
333 | c9c1a064 | ths | }, |
334 | e9c71dd1 | ths | { |
335 | e9c71dd1 | ths | .name = "VR5432",
|
336 | e9c71dd1 | ths | .CP0_PRid = 0x00005400,
|
337 | e9c71dd1 | ths | /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
|
338 | e9c71dd1 | ths | .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), |
339 | e9c71dd1 | ths | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
340 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
|
341 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
|
342 | e9c71dd1 | ths | .SYNCI_Step = 16,
|
343 | e9c71dd1 | ths | .CCRes = 2,
|
344 | e9c71dd1 | ths | .CP0_Status_rw_bitmask = 0x3678FFFF,
|
345 | e9c71dd1 | ths | /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
|
346 | e9c71dd1 | ths | .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), |
347 | e9c71dd1 | ths | .SEGBITS = 40,
|
348 | e9c71dd1 | ths | .PABITS = 32,
|
349 | e9c71dd1 | ths | .insn_flags = CPU_VR54XX, |
350 | e9c71dd1 | ths | .mmu_type = MMU_TYPE_R4000, |
351 | e9c71dd1 | ths | }, |
352 | c9c1a064 | ths | { |
353 | c9c1a064 | ths | .name = "5Kc",
|
354 | c9c1a064 | ths | .CP0_PRid = 0x00018100,
|
355 | 29fe0e34 | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
|
356 | 6958549d | aurel32 | (MMU_TYPE_R4000 << CP0C0_MT), |
357 | c9c1a064 | ths | .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
|
358 | 6958549d | aurel32 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
359 | 6958549d | aurel32 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
360 | 6958549d | aurel32 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
361 | c9c1a064 | ths | .CP0_Config2 = MIPS_CONFIG2, |
362 | c9c1a064 | ths | .CP0_Config3 = MIPS_CONFIG3, |
363 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
|
364 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
|
365 | c9c1a064 | ths | .SYNCI_Step = 32,
|
366 | c9c1a064 | ths | .CCRes = 2,
|
367 | ead9360e | ths | .CP0_Status_rw_bitmask = 0x32F8FFFF,
|
368 | e034e2c3 | ths | .SEGBITS = 42,
|
369 | 6d35524c | ths | .PABITS = 36,
|
370 | e189e748 | ths | .insn_flags = CPU_MIPS64, |
371 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
372 | c9c1a064 | ths | }, |
373 | c9c1a064 | ths | { |
374 | c9c1a064 | ths | .name = "5Kf",
|
375 | c9c1a064 | ths | .CP0_PRid = 0x00018100,
|
376 | 29fe0e34 | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
|
377 | 6958549d | aurel32 | (MMU_TYPE_R4000 << CP0C0_MT), |
378 | c9c1a064 | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | |
379 | 6958549d | aurel32 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
380 | 6958549d | aurel32 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
381 | 6958549d | aurel32 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
382 | c9c1a064 | ths | .CP0_Config2 = MIPS_CONFIG2, |
383 | c9c1a064 | ths | .CP0_Config3 = MIPS_CONFIG3, |
384 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
|
385 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
|
386 | c9c1a064 | ths | .SYNCI_Step = 32,
|
387 | c9c1a064 | ths | .CCRes = 2,
|
388 | ead9360e | ths | .CP0_Status_rw_bitmask = 0x36F8FFFF,
|
389 | 6958549d | aurel32 | /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
|
390 | c9c1a064 | ths | .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | |
391 | c9c1a064 | ths | (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), |
392 | e034e2c3 | ths | .SEGBITS = 42,
|
393 | 6d35524c | ths | .PABITS = 36,
|
394 | e189e748 | ths | .insn_flags = CPU_MIPS64, |
395 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
396 | c9c1a064 | ths | }, |
397 | c9c1a064 | ths | { |
398 | c9c1a064 | ths | .name = "20Kc",
|
399 | 6958549d | aurel32 | /* We emulate a later version of the 20Kc, earlier ones had a broken
|
400 | bd04c6fe | ths | WAIT instruction. */
|
401 | bd04c6fe | ths | .CP0_PRid = 0x000182a0,
|
402 | 29fe0e34 | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
|
403 | 6d35524c | ths | (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
|
404 | c9c1a064 | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | |
405 | 6958549d | aurel32 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
406 | 6958549d | aurel32 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
407 | 6958549d | aurel32 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
408 | c9c1a064 | ths | .CP0_Config2 = MIPS_CONFIG2, |
409 | c9c1a064 | ths | .CP0_Config3 = MIPS_CONFIG3, |
410 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
|
411 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 0,
|
412 | c9c1a064 | ths | .SYNCI_Step = 32,
|
413 | a1daafd8 | ths | .CCRes = 1,
|
414 | ead9360e | ths | .CP0_Status_rw_bitmask = 0x36FBFFFF,
|
415 | 6958549d | aurel32 | /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
|
416 | c9c1a064 | ths | .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | |
417 | 5a5012ec | ths | (1 << FCR0_D) | (1 << FCR0_S) | |
418 | c9c1a064 | ths | (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), |
419 | e034e2c3 | ths | .SEGBITS = 40,
|
420 | 6d35524c | ths | .PABITS = 36,
|
421 | e189e748 | ths | .insn_flags = CPU_MIPS64 | ASE_MIPS3D, |
422 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
423 | 33d68b5f | ths | }, |
424 | d2123ead | ths | { |
425 | 6958549d | aurel32 | /* A generic CPU providing MIPS64 Release 2 features.
|
426 | d2123ead | ths | FIXME: Eventually this should be replaced by a real CPU model. */
|
427 | d2123ead | ths | .name = "MIPS64R2-generic",
|
428 | 8c89395e | ths | .CP0_PRid = 0x00010000,
|
429 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
430 | 6958549d | aurel32 | (MMU_TYPE_R4000 << CP0C0_MT), |
431 | d2123ead | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | |
432 | 6958549d | aurel32 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
433 | 6958549d | aurel32 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
434 | 6958549d | aurel32 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
435 | d2123ead | ths | .CP0_Config2 = MIPS_CONFIG2, |
436 | 6d35524c | ths | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
|
437 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
|
438 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 0,
|
439 | d2123ead | ths | .SYNCI_Step = 32,
|
440 | d2123ead | ths | .CCRes = 2,
|
441 | d2123ead | ths | .CP0_Status_rw_bitmask = 0x36FBFFFF,
|
442 | ea4b07f7 | ths | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | |
443 | ea4b07f7 | ths | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
444 | ea4b07f7 | ths | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), |
445 | 6d35524c | ths | .SEGBITS = 42,
|
446 | 6d35524c | ths | /* The architectural limit is 59, but we have hardcoded 36 bit
|
447 | 6d35524c | ths | in some places...
|
448 | 6d35524c | ths | .PABITS = 59, */ /* the architectural limit */ |
449 | 6d35524c | ths | .PABITS = 36,
|
450 | d2123ead | ths | .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, |
451 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
452 | d2123ead | ths | }, |
453 | 5bc6fba8 | Huacai Chen | { |
454 | 5bc6fba8 | Huacai Chen | .name = "Loongson-2E",
|
455 | 5bc6fba8 | Huacai Chen | .CP0_PRid = 0x6302,
|
456 | 5bc6fba8 | Huacai Chen | /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
|
457 | 5bc6fba8 | Huacai Chen | .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) | |
458 | 5bc6fba8 | Huacai Chen | (0x1<<4) | (0x1<<1), |
459 | 5bc6fba8 | Huacai Chen | /* Note: Config1 is only used internally, Loongson-2E has only Config0. */
|
460 | 5bc6fba8 | Huacai Chen | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
461 | 5bc6fba8 | Huacai Chen | .SYNCI_Step = 16,
|
462 | 5bc6fba8 | Huacai Chen | .CCRes = 2,
|
463 | 5bc6fba8 | Huacai Chen | .CP0_Status_rw_bitmask = 0x35D0FFFF,
|
464 | 5bc6fba8 | Huacai Chen | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), |
465 | 5bc6fba8 | Huacai Chen | .SEGBITS = 40,
|
466 | 5bc6fba8 | Huacai Chen | .PABITS = 40,
|
467 | 5bc6fba8 | Huacai Chen | .insn_flags = CPU_LOONGSON2E, |
468 | 5bc6fba8 | Huacai Chen | .mmu_type = MMU_TYPE_R4000, |
469 | 5bc6fba8 | Huacai Chen | }, |
470 | 5bc6fba8 | Huacai Chen | { |
471 | 5bc6fba8 | Huacai Chen | .name = "Loongson-2F",
|
472 | 5bc6fba8 | Huacai Chen | .CP0_PRid = 0x6303,
|
473 | 5bc6fba8 | Huacai Chen | /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
|
474 | 5bc6fba8 | Huacai Chen | .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) | |
475 | 5bc6fba8 | Huacai Chen | (0x1<<4) | (0x1<<1), |
476 | 5bc6fba8 | Huacai Chen | /* Note: Config1 is only used internally, Loongson-2F has only Config0. */
|
477 | 5bc6fba8 | Huacai Chen | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
478 | 5bc6fba8 | Huacai Chen | .SYNCI_Step = 16,
|
479 | 5bc6fba8 | Huacai Chen | .CCRes = 2,
|
480 | 5bc6fba8 | Huacai Chen | .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writeable*/ |
481 | 5bc6fba8 | Huacai Chen | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), |
482 | 5bc6fba8 | Huacai Chen | .SEGBITS = 40,
|
483 | 5bc6fba8 | Huacai Chen | .PABITS = 40,
|
484 | 5bc6fba8 | Huacai Chen | .insn_flags = CPU_LOONGSON2F, |
485 | 5bc6fba8 | Huacai Chen | .mmu_type = MMU_TYPE_R4000, |
486 | 5bc6fba8 | Huacai Chen | }, |
487 | 5bc6fba8 | Huacai Chen | |
488 | 33d68b5f | ths | #endif
|
489 | 33d68b5f | ths | }; |
490 | 33d68b5f | ths | |
491 | c227f099 | Anthony Liguori | static const mips_def_t *cpu_mips_find_by_name (const char *name) |
492 | 33d68b5f | ths | { |
493 | aaed909a | bellard | int i;
|
494 | 33d68b5f | ths | |
495 | b1503cda | malc | for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { |
496 | 33d68b5f | ths | if (strcasecmp(name, mips_defs[i].name) == 0) { |
497 | aaed909a | bellard | return &mips_defs[i];
|
498 | 33d68b5f | ths | } |
499 | 33d68b5f | ths | } |
500 | aaed909a | bellard | return NULL; |
501 | 33d68b5f | ths | } |
502 | 33d68b5f | ths | |
503 | 9a78eead | Stefan Weil | void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
|
504 | 33d68b5f | ths | { |
505 | 33d68b5f | ths | int i;
|
506 | 33d68b5f | ths | |
507 | b1503cda | malc | for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { |
508 | 33d68b5f | ths | (*cpu_fprintf)(f, "MIPS '%s'\n",
|
509 | 33d68b5f | ths | mips_defs[i].name); |
510 | 33d68b5f | ths | } |
511 | 33d68b5f | ths | } |
512 | 33d68b5f | ths | |
513 | f8a6ec58 | ths | #ifndef CONFIG_USER_ONLY
|
514 | c227f099 | Anthony Liguori | static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
515 | 29929e34 | ths | { |
516 | ead9360e | ths | env->tlb->nb_tlb = 1;
|
517 | ead9360e | ths | env->tlb->map_address = &no_mmu_map_address; |
518 | 29929e34 | ths | } |
519 | 29929e34 | ths | |
520 | c227f099 | Anthony Liguori | static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
521 | 29929e34 | ths | { |
522 | ead9360e | ths | env->tlb->nb_tlb = 1;
|
523 | ead9360e | ths | env->tlb->map_address = &fixed_mmu_map_address; |
524 | 29929e34 | ths | } |
525 | 29929e34 | ths | |
526 | c227f099 | Anthony Liguori | static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
527 | 29929e34 | ths | { |
528 | ead9360e | ths | env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); |
529 | ead9360e | ths | env->tlb->map_address = &r4k_map_address; |
530 | c01fccd2 | aurel32 | env->tlb->helper_tlbwi = r4k_helper_tlbwi; |
531 | c01fccd2 | aurel32 | env->tlb->helper_tlbwr = r4k_helper_tlbwr; |
532 | c01fccd2 | aurel32 | env->tlb->helper_tlbp = r4k_helper_tlbp; |
533 | c01fccd2 | aurel32 | env->tlb->helper_tlbr = r4k_helper_tlbr; |
534 | ead9360e | ths | } |
535 | ead9360e | ths | |
536 | c227f099 | Anthony Liguori | static void mmu_init (CPUMIPSState *env, const mips_def_t *def) |
537 | ead9360e | ths | { |
538 | ead9360e | ths | env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext));
|
539 | ead9360e | ths | |
540 | 6d35524c | ths | switch (def->mmu_type) {
|
541 | 6d35524c | ths | case MMU_TYPE_NONE:
|
542 | ead9360e | ths | no_mmu_init(env, def); |
543 | ead9360e | ths | break;
|
544 | 6d35524c | ths | case MMU_TYPE_R4000:
|
545 | ead9360e | ths | r4k_mmu_init(env, def); |
546 | ead9360e | ths | break;
|
547 | 6d35524c | ths | case MMU_TYPE_FMT:
|
548 | ead9360e | ths | fixed_mmu_init(env, def); |
549 | ead9360e | ths | break;
|
550 | 6d35524c | ths | case MMU_TYPE_R3000:
|
551 | 6d35524c | ths | case MMU_TYPE_R6000:
|
552 | 6d35524c | ths | case MMU_TYPE_R8000:
|
553 | ead9360e | ths | default:
|
554 | ead9360e | ths | cpu_abort(env, "MMU type not supported\n");
|
555 | ead9360e | ths | } |
556 | 29929e34 | ths | } |
557 | f8a6ec58 | ths | #endif /* CONFIG_USER_ONLY */ |
558 | 29929e34 | ths | |
559 | c227f099 | Anthony Liguori | static void fpu_init (CPUMIPSState *env, const mips_def_t *def) |
560 | ead9360e | ths | { |
561 | f01be154 | ths | int i;
|
562 | f01be154 | ths | |
563 | f01be154 | ths | for (i = 0; i < MIPS_FPU_MAX; i++) |
564 | f01be154 | ths | env->fpus[i].fcr0 = def->CP1_fcr0; |
565 | ead9360e | ths | |
566 | f01be154 | ths | memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); |
567 | ead9360e | ths | } |
568 | ead9360e | ths | |
569 | c227f099 | Anthony Liguori | static void mvp_init (CPUMIPSState *env, const mips_def_t *def) |
570 | ead9360e | ths | { |
571 | ead9360e | ths | env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext));
|
572 | ead9360e | ths | |
573 | ead9360e | ths | /* MVPConf1 implemented, TLB sharable, no gating storage support,
|
574 | ead9360e | ths | programmable cache partitioning implemented, number of allocatable
|
575 | ead9360e | ths | and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
|
576 | ead9360e | ths | implemented, 5 TCs implemented. */
|
577 | ead9360e | ths | env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | |
578 | ead9360e | ths | (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | |
579 | ead9360e | ths | // TODO: actually do 2 VPEs.
|
580 | ead9360e | ths | // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
|
581 | ead9360e | ths | // (0x04 << CP0MVPC0_PTC);
|
582 | ead9360e | ths | (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | |
583 | ead9360e | ths | (0x04 << CP0MVPC0_PTC);
|
584 | 932e71cd | aurel32 | #if !defined(CONFIG_USER_ONLY)
|
585 | 0eaef5aa | ths | /* Usermode has no TLB support */
|
586 | 932e71cd | aurel32 | env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); |
587 | 932e71cd | aurel32 | #endif
|
588 | 0eaef5aa | ths | |
589 | ead9360e | ths | /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
|
590 | ead9360e | ths | no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
|
591 | ead9360e | ths | env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | |
592 | ead9360e | ths | (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | |
593 | ead9360e | ths | (0x1 << CP0MVPC1_PCP1);
|
594 | ead9360e | ths | } |