target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
mips: avoid write only variables
Compiling with GCC 4.6.0 20100925 produced a lot of warnings like:/src/qemu/target-mips/translate.c: In function 'gen_ld':/src/qemu/target-mips/translate.c:1039:17: error: variable 'opn' set but not used [-Werror=unused-but-set-variable]...
MIPS: fix yield handling
The parameter for yield should be handled as a signed integerfor the comparisons to have any effect.
This also avoids a gcc warning with -Wtype-limits.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
mips: Add support for VInt and VEIC irq modes
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
Correctly identify multiple cpus in SMP systems
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Remove unused constant
Remove unused constant MIPS_FCR0
mips: more fixes to the MIPS interrupt glue logic
Commit 36388314febad3d7675ab919287f03733a560ff6 moved most of theinterrupt logic to cpu-exec.c. Remove the remaining useless codeand fix software interrupts.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
mips: Correct MIPS interrupt glue logic for icount
When hw interrupt pending bits in CP0_Cause are set, the CPU shouldsee the hw interrupt line as active. The CPU may or may not take theinterrupt based on internal state (global irq mask etc) but the glue...
target-mips: fix xtlb exception for loongson
Loongson 2E and 2F use the same entry for xtlb and tlb exception, atoffset 0x000.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: add loongson 2E & 2F integer instructions
This patch adds support for loongson 2E & 2F instructions. They are thesame instructions, but differ by the opcode encoding.
remove exec-all.h inclusion from cpu.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
move cpu_pc_from_tb to target-*/exec.h
remove unused stuff from */exec.h
target-mips: add Loongson support prefetch
Loongson CPU uses a load to zero register for prefetch.Emulate it as a NOP.
target-mips: split load and store
target-mips: fix DINSU instruction
target-mips: enable movn/movz on loongson 2E & 2F
MIPS: Initial support of fulong mini pc (CPU definition)
Signed-off-by: Huacai Chen <zltjiangshi@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Fix compilation
TCGv t1 needs tcg_temp_free instead of tcg_temp_free_i32.
Cc: Nathan Froyd <froydnj@codesourcery.com>Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: add microMIPS exception handler support
Unlike MIPS16, microMIPS lets you choose the ISA mode for your exceptionhandlers. The ISA mode is selectable via a user-writable CP0.Config3flag.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>...
target-mips: define constants for magic numbers
Add FMT_* constants for the floating-point format field in opcodes andtweak a few places to use them. Add enums for various invocations ofFOP and tweak gen_farith and its lone caller accordingly.
target-mips: move FP FMT comments closer to the definitions
target-mips: refactor c{, abs}.cond.fmt insns
Move all knowledge about coprocessor-checking and register numberinginto the gen_cmp* helper functions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: mips16 cleanups
Change code handling mips16-specific branches to use ISA-neutral specialopcodes. Since there are several places where the delay slotrequirements for microMIPS branches differ from mips16 branches, usingopcodes is easier than checking hflags, then checking mips16...
target-mips: microMIPS ASE support
Add instruction decoding for the microMIPS ASE. All we do is decode andthen forward to the existing gen_* routines.
target-mips: break out [ls][wd]c1 and rdhwr insn generation
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Acked-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Remove duplicate CPU log.
Logging for -d cpu is done in generic code.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Fix format specifiers for fpu_fprintf
In the previous patch which introduced fprintf_function toallow parameter checking by gcc some compiler warningsremained unfixed.
These warnings are fixed here.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
target-mips: Fix one more format specifier for cpu_fprintf
env->bcond must be printed using TARGET_FMT_ld.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
remove TARGET_* defines from translate-all.c
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Large page TLB flush
QEMU uses a fixed page size for the CPU TLB. If the guest uses largepages then we effectively split these into multiple smaller pages, andpopulate the corresponding TLB entries on demand.
When the guest invalidates the TLB by virtual address we must invalidate...
target-mips: update address space definitions
Target specific usermode cleanup
Disable various target specific code that is only relevant to system emulation.
Signed-off-by: Paul Brook <paul@codesourcery.com>
Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.
Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.
Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets otherthan Alpha. This will be used for page_find_alloc, which issupposed to be using virtual addresses in the first place....
target-mips: use newer logical ops
target-mips: use setcond when possible
target-mips: fix ROTR and DROTR by zero
target-mips: remove useless sign extension
target-mips: fix CpU exception for coprocessor 0
When we signal a CpU exception for coprocessor 0, we should indicatethat it's for coprocessor 0 instead of coprocessor 1.
target-mips: don't call cpu_loop_exit() from helper.c
In helper.c AREG0 may not correspond do env, so it's not possible tocall cpu_loop_exit() here. Call it from op_helper.c instead.
kill regs_to_env and env_to_regs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
target-mips: No MIPS16 support for 4Kc, 4KEc cores
Fix regression introduced by d19954f46dfc262612c30e9534e660e953049487.
4Kc and 4KEc don't support MIPS16.
target-mips: 4Kc, 4KEc cores do not support MIPS16
4Kc, 4KEc cores do not support MIPS16, so not only theCP0_Config1 had to be fixed (see previous patch),but also MIPS16 instructions must not be executed.
(Hint from Nathan Froyd, thanks).
target-mips: fix user-mode emulation startup
Running programs with the MIPS user-mode emulator fails during dynamicloading, as floating-point instructions are not enabled in inenv->hflags. Move the code for doing so from fpu_init to cpu_reset sothe MIPS_HFLAG_{FPU,F64} setting doesn't get clobbered by cpu_reset...
target-mips: add enums for MIPS16 opcodes
target-mips: add mips16 instruction decoding
There's no good way to add this incrementally, so we do it all at once.The only changes to shared code are in handle_delay_slot. We need toflip ISAMode when doing a jump-and-exchange. We also need to setISAMode the low bit of the target address for jump-to-register....
target-mips: add copyright notice for mips16 work
Also cross off mips16 ASE in TODO.
target-mips: set Config1.CA for MIPS16-aware CPUs
target-mips: add new HFLAGs for JALX and 16/32-bit delay slots
We create separate masks for the "basic" branch hflags and the"extended" branch hflags and define MIPS_HFLAG_BMASK as the logical orof those two. This is done to avoid churning the codebase in lots of...
target-mips: change interrupt bits to be mips16-aware
We need to stash the operating mode into the low bit of the error PC andrestore it on return from interrupts.
target-mips: move ROTR and ROTRV inside gen_shift_{imm, }
It's easier to implement mips16 shift instructions if we're notexamining the opcode inside gen_shift_{imm,}. So move ROTR and ROTRVand do the special-case handling of SRL and SRLV inside decode_opc....
target-mips: make gen_compute_branch 16/32-bit-aware
target-mips: add gen_base_offset_addr
This is a common pattern in existing code. We'll also use it toimplement the mips16 SAVE/RESTORE instructions.
target-mips: split out delay slot handling
Move delay slot handling to common code whose invocation can becontrolled from gen_intermediate_code_internal.
target-mips: use physical address in lladdr
Currently the ll/sc instructions use the virtual address in bothuser and system mode. Use the physical address insteead in systemmode.
target-mips: add a function to do virtual -> physical translations
target-mips: split code raising MMU exception in a separate function
target-mips: factorize load/store code in op_helper.c
target-mips: fix physical address type in MMU functions
target-mips: make CP0_LLAddr register CPU dependent
Depending on the CPU, CP0_LLAddr is either read-only or read-write,and the returned value can be shifted by a variable amount of bits.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
target-mips: rename CP0_LLAddr into lladdr
The variable CP0_LLAddr represent the full lladdr, not the actualregister value, which is only part of this value and depends on theCPU.
target-mips: fix indentation
mips: fix cpu_reset memory leak
Remove cpu_mips_register()- move mmu_init(), fpu_init() and mvp_init() into cpu_mips_init()- move the other parts in cpu_mips_init()
Reported-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
target-mips: make sure constants are in the second argument
mips: Fix spelling in comment
inofficial -> unofficial
Thanks to Blue Swirl.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-mips: unmatched brackets in if 0
Fix unmatched braket in commented out code
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-mips: log instructions start in TCG code
target-mips: remove MAX_OP_PER_INSTR workaround
Now that MAX_OP_PER_INSTR has been increased to a safer value, removedthe target-mips specific workaround.
Add 'static' to please Sparse
target-mips: fix single-stepping
Single-stepping branches on MIPS didn't work right, because thegeneration of EXCP_DEBUG happened after the generation of the code toexit the current TB. That is, given the code:
bne v0,v1,target nop ... target:...
Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there aresome additions and it's not entirely compatible. Because of that, there havebeen conflicts with system headers on BSD systems. Some hacks have beenintroduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...
target-mips: fix conditional moves off fp condition codes
Conditional moves off fp condition codes were using the result ofget_fp_bit to isolate and test the relevant condition code. However,get_fp_bit returns the bit number of the condition code, not a...
cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with afew minor variations. This patch sets up appropriate defaults for ageneric handle_cpu_signal and provides overrides for particular targets...
rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
change HOST_SOLARIS to CONFIG_SOLARIS{_VERSION}
Update to a hopefully more future proof FSF address
target-mips: remove useless code in gen_st_cond()
Fix MIPS SC
Fix botched merge of op_ldst_sc calls to match actual implementation.Thanks to Aurelien Jarno for diagnosing this.
MIPS atomic instructions
Implement MIPS ll/sc instructions using atomic compare+exchange.
MIPS usermode TLS register
Implement cpu_set_tls for MIPS.
target-mips: fix MADD and MSUB/MSUBU instructions
MADD was not correctly writing to HI.
MSUB/MSUBU are specified as `HI||LO - product', not `product - HI||LO'.
Fix a warning: uint_fast8_t is not 8 bits on OpenBSD/Sparc64
Convert machine registration to use module init functions
This cleans up quite a lot of #ifdefs, extern variables, and other ugliness.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Hardware convenience library
The only target dependency for most hardware is sizeof(target_phys_addr_t).Build these files into a convenience library, and use that instead ofbuilding for every target.
Remove and poison various target specific macros to avoid bogus target...
Include assert.h from qemu-common.h
Include assert.h from qemu-common.h and remove other direct uses.cpu-all.h still need to include it because of the dyngen-exec.h hacks
Replace gcc variadic macro extension with C99 version
target-mips: proper sign extension for 'SUBU rd, zero, rt'
target-mips: fix comments about SUB/DSUB
qemu: introduce qemu_init_vcpu (Marcelo Tosatti)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
qemu: per-arch cpu_has_work (Marcelo Tosatti)
Blue Swirl: fix Sparc32 breakage
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7238 c046a42c-6fe2-441c-8c8c-71466251a162
Enable access to SYNCI_Step register in usermode emulation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7191 c046a42c-6fe2-441c-8c8c-71466251a162
Revert "target-mips: fix call to check_*() functions"
This reverts commit r7127, r7132 is a better fix for that.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7133 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: simplify exception generation
There is no need to exit the tb after a call to helper_raise_exceptionas it already calls cpu_loop_exit().
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7132 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: fix revision r7126
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7128 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: fix call to check_*() functions
check_*() functions may in fine call generate_exception(), which endsby a call to tcg_gen_exit_tb(). As a consequence, we have to make surethat no TCG temp variables are crossing a check_*() function.
target-mips: optimize gen_flt3_ldst()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7126 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: optimize gen_flt_ldst()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7125 c046a42c-6fe2-441c-8c8c-71466251a162