target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
remove exec-all.h inclusion from cpu.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
move cpu_pc_from_tb to target-*/exec.h
sparc64: fix umul and smul insns
- truncate and sign or zero extend operands before multiplication- factor out common code to gen_op_multiply() with parameter to sign/zero extend- call gen_op_multiply from gen_op_umul and gen_op_smul
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>...
sparc64: fix udiv and sdiv insns
- truncate second operand to 32bit
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc64: improve ldf and stf insns
- implemented block load/store primary/secondary with user privilege
sparc64: use symbolic name for MMU index v1
- use symbolic name for MMU indexv0->v1:- change debug traces to DPRINTF_MMU- fix debug trace function names
sparc64: fix ldxfsr insn
- rearrange code to break from switch when appropriate- allow deprecated ldfsr insn
sparc64: fix missing address masking v1
- address masking for ldqf and stqf insns- address masking for lddf and stdf insns- address masking for translating ASI (Ultrasparc IIi)v0->v1:- move arch-specific code to helpers and drop more ifdefs at call sites...
sparc64: fix tag access register on mmu traps
- set mmu tag access register on FAULT and PROT traps as well
sparc32 SuperSPARC MMU Breakpoint Action register (SS-20 OBP fix)
SuperSPARC MMU Breakpoint Action register is used by OBP at boot
The patch allows booting Solaris and some other OS withSPARCStation-20 OBP.
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>...
sparc64: fix user emulator build
Accesses with _nucleus prefix are not available when building useremulators: CC sparc64-linux-user/op_helper.occ1: warnings being treated as errors/src/qemu/target-sparc/op_helper.c: In function 'helper_ldda_asi':...
sparc64: fix 128-bit atomic load from nucleus context v1
- change 128-bit atomic loads to reference nucleus contextv0->v1: dropped disassembler changeSigned-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc64: flush translations on mmu context change
- two pairs of softmmu indexes bind softmmu tlb to cpu tlb in fault handlers using value of DMMU primary and secondary context registers, so we need to flush softmmu translations when context registers are changed...
sparc64: fix mmu context at trap levels above zero
- cpu_mmu_index return MMU_NUCLEUS_IDX if trap level is not zero- cpu_get_tb_cpu_state: store trap level and primary context in flags this allows to restart code translation when address translation is changed...
sparc64: fix dump_mmu to look for global bit in tte value instead of tag
sparc64: fix pstate privilege bits
- refactor code to handle hpstate only if available for current cpu- conditionally set hypervisor bit in hpstate register- reorder softmmu indices so user accessable ones go first, translation context macros supervisor() and hypervisor() adjusted as well...
sparc64: generate data access exception on RW violation
- separate PRIV and PROT handling- DPRINTF_MMU macro to clean up debug code- dump mmu_idx, trap level and mmu context registers along with address translation values
Fix %lld or %llx printf format use
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sparc: Inline some generation of carry for ADDX/SUBX.
Computing carry is trivial for some inputs. By avoiding anexternal function call, we generate near-optimal code forthe common cases of add+addx (double-word arithmetic) andcmp+addx (a setcc pattern)....
target-sparc: Simplify ICC generation.
Use int32 types instead of target_ulong when computing ICC. Thissimplifies the generated code for 32-bit host and 64-bit guest.Use the same simplified expressions for ICC as were already usedfor XCC in carry flag generation....
target-sparc: Fix compilation with --enable-debug.
Return a target_ulong from compute_C_icc to match the width of the users.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc: move DT and QT defines to op_helper.c
sparc64: fix TT_WOTHER value
- fix off by one error in spill trap number bit for other window (must be bit 5)- fixes invalid instruction issue with HelenOS
sparc64: fix mmu demap operand typo
- must use store address operand to demap, not store value
target-sparc: Fix wrong printf argument
cpu_get_ccr() returns a target_ulong, so a type cast is needed to avoidwrong output on big endian hosts. We could also use TARGET_FMT_lx,but that would print 8 instead of 2 digits.
Cc: Blue Swirl <blauwirbel@gmail.com>...
sparc: Fix lazy flag calculation on interrupts, refactor
Recalculate Sparc64 CPU flags on interrupts, otherwise some earlierflags could be stored to pstate.
Refactor PSR/CCR/CWP handling: concentrate the actualfunctions to op_helper.c.
Thanks to Igor Kovalenko for reporting....
sparc: lazy C flag calculation
Calculate only the carry flag for ADDX/SUBX instead of fullset of flags.
Thanks to Igor Kovalenko for spotting a bug with an earlierversion.
sparc64: fix build with older gccs
Fix errors missed in 2065061ede22d401aae2ce995c3af54db9d28639: CC sparc64-softmmu/helper.occ1: warnings being treated as errors/src/qemu/target-sparc/helper.c: In function 'get_physical_address':/src/qemu/target-sparc/helper.c:426: warning: 'context' may be used uninitialized in this function...
sparc64: handle asi referencing nucleus and secondary MMU contexts
- increase max supported MMU modes to 6- handle nucleus context asi- handle secondary context asi- handle non-faulting loads from secondary context
sparc64: implement global translation table entries v1
- match global tte against any context- show global tte in MMU dump
v0->v1: added default case to switch statement in demap_tlb- should fix gcc warning about uninitialized context variable
target-sparc: Fix -singlestep.
Single-stepping was not properly updating npc, resulting in someinstructions being executed twice. In addition, we were emittingdead code at the end of the TB.
Fix both by teaching gen_goto_tb to avoid goto_tb for single-step...
target-sparc: Fix address masking in ldqf and stqf.
Use address_mask on both addr and addr+8 in both these routines,rather than explicit masking with 0xffffffff.
Reformulate address_mask to return a result, rather than maskinga pass-by-reference argument....
Fix harmless if statements with empty body, spotted by clang
These clang errors are harmless but worth fixing: CC ppc-softmmu/usb-ohci.o/src/qemu/hw/usb-ohci.c:1104:59: error: if statement has empty body [-Wempty-body] ohci->ctrl_head, ohci->ctrl_cur);...
target-sparc: Free instruction temporaries.
Rather than creating new temporaries for constants, use theones created in disas_sparc_insn. Remember the temps createdthere so that they can be freed at the end of the function.
Profile data collected by TCG while booting sparc-test kernel:...
target-sparc: Fix TARGET_{PHYS,VIRT}_ADDR_SPACE_BITS.
The 32 and 64-bit definitions were swapped in the ifdef.
Sparc: fix PC/NPC during FPU traps
All FPU instructions can trap, so save PC/NPC state beforeexecuting them.
Sparc: fix exceptions in delay slot
Fix a case where an exception happens with theinstruction in the delay slot.
Recovery of branch condition in the exception handlingcode was not converted to TCG. Because the conditionwas bogus, wrong NPC could be selected from the two...
remove TARGET_* defines from translate-all.c
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Large page TLB flush
QEMU uses a fixed page size for the CPU TLB. If the guest uses largepages then we effectively split these into multiple smaller pages, andpopulate the corresponding TLB entries on demand.
When the guest invalidates the TLB by virtual address we must invalidate...
Target specific usermode cleanup
Disable various target specific code that is only relevant to system emulation.
Signed-off-by: Paul Brook <paul@codesourcery.com>
Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.
Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.
Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets otherthan Alpha. This will be used for page_find_alloc, which issupposed to be using virtual addresses in the first place....
target-sparc: fix --enable-debug build for 64 bit host
b551ec04ca45d1925417dd2ec7c1b7f115c84f1d fixedthe compilation for 32 bit hosts, but introduceda new error for 64 bit hosts:
tcg_temp_new_ptr needs a matching tcg_temp_free_ptr.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
target-sparc: fix --enable-debug build
Use 32-bit arithmetic for the address offset calculation to fix abuild failure on 32-bit hosts.
Signed-off-by: Jay Foad <jay.foad@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc32 don't mark page dirty when failing
if the access check fails, the page can not be modifiedand shouldn't be marked dirty.The patch fixes the "hsfs_putpage: dirty HSFS page" error in Solaris guests.
sparc64: reimplement tick timers v4
sparc64 timer has tick counter which can be set and read,and tick compare value used as deadline to fire timer interrupt.The timer is not used as periodic timer, instead deadlineis set each time new timer interrupt is needed....
sparc64: correct write extra bits to cwp
- correctly fit to cwp if provided window number is out of range
sparc32 fix np dereference in do_unassigned_access
fix a potential null pointer dereference introduced incommit 576c2cdc767ab9e2dc038fa4c99f22e53287a3de
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
kill regs_to_env and env_to_regs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Sparc: improve CPU register dump
Common: * Remove unnecessary 0x prefix * Print %y * Fix NZVC flag print order to match CPU bit order
Sparc64 specific: * Print registers without line wrapping * Print %f40-%f63 * Pretty print CCR flags * Print %fsr and %fprs in full precision...
sparc32 do_unassigned_access overhaul v2
According to pages 9-31 - 9-34 of "SuperSPARC & MultiCache ControllerUser's Manual":
1. "A lower priority fault may not overwrite the MFSR status of a higher priority fault." 2. The MFAR is overwritten according to the policy defined for the MFSR...
Sparc32: remove unused variable, spotted by clang
sparc64: interrupt trap handling
cpu_check_irqs- handle SOFTINT register TICK and STICK timer bits- only check interrupt levels greater than PIL value- handle preemption by higher level traps
cpu_exec- handle CPU_INTERRUPT_HARD only if interrupts are enabled...
sparc64: move cpu_interrupts_enabled to cpu.h
- to be used by cpu_check_irqs
sparc64: add macros to deal with softint and timer interrupt
sparc64: check for pending irq when pil, pstate or softint is changed
sparc64: use helper_wrpil to check pending irq on write
sparc64: add PIL to cpu state dump
sparc64: trace pstate and global register set changes
sparc64: change_pstate should have 32bit argument
- pstate is 32bit variable, no need to pass 64bit value around
Sparc32: clear exception_index with -1 value
See also 821b19fe923ac49a24cdb4af902584fdd019cee6.
Spotted by Artyom Tarasenko and Igor Kovalenko.
sparc64: clear exception_index with -1 value
pass env to raise_exception if called outside of op_helper code
- this fixes stepping with gdb, where do_unassigned_access may be called from gdb handler, outside of generated code
sparc64: switch to MMU global registers in more MMU related traps
- extended range of MMU related traps which use MMU global registers, as listed in Ultrasparc-IIi document- no visible changes, since emulation do not cause added traps
Sparc64: handle MMU global bit and nucleus context
Sparc64: fix compilation with DEBUG_MMU
user: move CPU reset call to main.c for x86/PPC/Sparc
sparc32 (mostly): remove unneeded calls to device reset
Sparc: fix carry flag handling (Solaris bootblk fix)
The page 108 of the SPARC Version 8 Architecture Manual describesthat addcc and addxcc shall compute carry flag the same way.The page 110 claims the same about subcc and subxcc instructions.This patch fixes carry computation in corner cases and removes redundant code....
sparc64: fix done instruction pc
Fix done instruction to resume with pc=tnpc, npc=tnpc+4
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
sparc64-8bit-asi
Sparc64 alternate space load/store helpers expect 8 bit ASI value,while wrasi implementation sign-extends ASI operand causingfor example 0x80 to appear as 0xFFFFFF80. Resulting value fallsout of switch in helpers and causes obscure load/store faults....
Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there aresome additions and it's not entirely compatible. Because of that, there havebeen conflicts with system headers on BSD systems. Some hacks have beenintroduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...
cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with afew minor variations. This patch sets up appropriate defaults for ageneric handle_cpu_signal and provides overrides for particular targets...
sparc32 remove an unnecessary cpu irq set
Sparc32/64: fix jmpl followed by branch
Fix a case where 'jmpl' instruction followed by a branch instruction washandled incorrectly.
Sparc32/64: Fix user emulator breakage
Fix desynchronization of condition code state when a memory access traps
Sparc64: replace tsptr with helper routine
tl and tsptr of members sparc64 cpu state must be changedsimultaneously to keep trap state window in sync with currenttrap level. Currently translation of store to tl does not changetsptr, which leads to corrupt trap state on corresponding...
sparc64 flush pending conditional evaluations before exposing cpu state
If translation block is interrupted by e.g. mmu exceptionwe need to compute conditional flags for inclusion intosaved cpu state. Otherwise after return from trapconditional instructions would use stale psr/xcc data....
rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
sparc64 really implement itlb/dtlb automatic replacement writes
- implement "used" bit in tlb translation entry- mark tlb entry used if qemu code/data translation succeeds- fold i/d mmu replacement writes code into replace_tlb_1bit_lru whichadds 1bit lru replacement algorithm; previously code tried to replace...
sparc64 name mmu registers and general cleanup
- add names to mmu registers, this helps understanding the code whichuses/modifies them.- fold i/d mmu tlb entries tag and tte arrays into arrays of tlb entries- extract demap_tlb routine (code duplication)...
Fix most warnings (errors with -Werror) when debugging is enabled
I used the following command to enable debugging:perl -p -i -e 's/^\/\/#define DEBUG/#define DEBUG/g' * /* *//*
Update to a hopefully more future proof FSF address
sparc64: trap handling corrections
On Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl<blauwirbel@gmail.com> wrote:
On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote: Good trap handling is required to process interrupts. This patch fixes the following:...
On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote:
Good trap handling is required to process interrupts. This patch fixes the following:...
sparc64: fix helper_st_asi little endian case typo
On Sun, Jul 12, 2009 at 12:43 AM, Stuart Brady<sdbrady@ntlworld.com> wrote:
On Sat, Jul 11, 2009 at 10:22:18PM +0400, Igor Kovalenko wrote: It is clear that intention is to byte-swap value to be written, not...
On Sat, Jul 11, 2009 at 10:22:18PM +0400, Igor Kovalenko wrote:
It is clear that intention is to byte-swap value to be written, not...
sparc64: mmu bypass mode correction
This Implement physical address truncation in mmu bypass mode.IMMU bypass is also active when cpu enters RED_STATE
Signed-off-by: igor.v.kovalenko@gmail.com
--Kind regards,Igor V. Kovalenko
sparc64: unify mmu tag matching code
This patch extracts common part of sparc64 tagmatching code used by IMMU and DMMU lookups.
Use correct type for SPARC cpu_cc_op
Convert machine registration to use module init functions
This cleans up quite a lot of #ifdefs, extern variables, and other ugliness.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Hardware convenience library
The only target dependency for most hardware is sizeof(target_phys_addr_t).Build these files into a convenience library, and use that instead ofbuilding for every target.
Remove and poison various target specific macros to avoid bogus target...
Include assert.h from qemu-common.h
Include assert.h from qemu-common.h and remove other direct uses.cpu-all.h still need to include it because of the dyngen-exec.h hacks
Replace gcc variadic macro extension with C99 version
Convert mulscc
Convert udiv/sdiv
Convert tagged ops
Convert subx