Revision 9b595395

b/hw/mipsnet.c
11 11 
/* MIPSnet register offsets */
12 12 

  		





  13
  13
  
    
#define MIPSNET_DEV_ID		0x00


  		





  14
  
  
    
# define MIPSNET_DEV_ID_STRING	"MIPSNET0"


  		





  15
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#define MIPSNET_BUSY		0x08


  		





  16
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#define MIPSNET_RX_DATA_COUNT	0x0c


  		





  17
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#define MIPSNET_TX_DATA_COUNT	0x10


  		





  ......




  105
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{


  		





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    MIPSnetState *s = opaque;


  		





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    int ret = 0;


  		





  108
  
  
    
    const char *devid = MIPSNET_DEV_ID_STRING;


  		





  109
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    addr &= 0x3f;


  		





  111
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    switch (addr) {


  		





  112
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    case MIPSNET_DEV_ID:


  		





  113
  
  
    
	ret = *((uint32_t *)&devid);


  		





  
  111
  
    
	ret = be32_to_cpu(0x4d495053);		/* MIPS */


  		





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        break;


  		





  115
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    case MIPSNET_DEV_ID + 4:


  		





  116
  
  
    
	ret = *((uint32_t *)(&devid + 4));


  		





  
  114
  
    
	ret = be32_to_cpu(0x4e455430);		/* NET0 */


  		





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        break;


  		





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    case MIPSNET_BUSY:


  		





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	ret = s->busy;


  		












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