Revision 9b595395 hw/mipsnet.c

b/hw/mipsnet.c
11 11
/* MIPSnet register offsets */
12 12

  
13 13
#define MIPSNET_DEV_ID		0x00
14
# define MIPSNET_DEV_ID_STRING	"MIPSNET0"
15 14
#define MIPSNET_BUSY		0x08
16 15
#define MIPSNET_RX_DATA_COUNT	0x0c
17 16
#define MIPSNET_TX_DATA_COUNT	0x10
......
105 104
{
106 105
    MIPSnetState *s = opaque;
107 106
    int ret = 0;
108
    const char *devid = MIPSNET_DEV_ID_STRING;
109 107

  
110 108
    addr &= 0x3f;
111 109
    switch (addr) {
112 110
    case MIPSNET_DEV_ID:
113
	ret = *((uint32_t *)&devid);
111
	ret = be32_to_cpu(0x4d495053);		/* MIPS */
114 112
        break;
115 113
    case MIPSNET_DEV_ID + 4:
116
	ret = *((uint32_t *)(&devid + 4));
114
	ret = be32_to_cpu(0x4e455430);		/* NET0 */
117 115
        break;
118 116
    case MIPSNET_BUSY:
119 117
	ret = s->busy;

Also available in: Unified diff