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/*
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 * QEMU USB OHCI Emulation
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 * Copyright (c) 2004 Gianni Tedesco
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 * Copyright (c) 2006 CodeSourcery
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 * Copyright (c) 2006 Openedhand Ltd.
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 *
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 * TODO:
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 *  o Isochronous transfers
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 *  o Allocate bandwidth in frames properly
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 *  o Disable timers when nothing needs to be done, or remove timer usage
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 *    all together.
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 *  o Handle unrecoverable errors properly
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 *  o BIOS work to boot from USB storage
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*/
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#include "hw.h"
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#include "qemu-timer.h"
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#include "usb.h"
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#include "pci.h"
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#include "usb-ohci.h"
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#include "sysbus.h"
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#include "qdev-addr.h"
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//#define DEBUG_OHCI
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/* Dump packet contents.  */
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//#define DEBUG_PACKET
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//#define DEBUG_ISOCH
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/* This causes frames to occur 1000x slower */
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//#define OHCI_TIME_WARP 1
43

    
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#ifdef DEBUG_OHCI
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#define DPRINTF printf
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#else
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#define DPRINTF(...)
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#endif
49

    
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/* Number of Downstream Ports on the root hub.  */
51

    
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#define OHCI_MAX_PORTS 15
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static int64_t usb_frame_time;
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static int64_t usb_bit_time;
56

    
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typedef struct OHCIPort {
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    USBPort port;
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    uint32_t ctrl;
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} OHCIPort;
61

    
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typedef struct {
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    USBBus bus;
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    qemu_irq irq;
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    int mem;
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    int num_ports;
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    const char *name;
68

    
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    QEMUTimer *eof_timer;
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    int64_t sof_time;
71

    
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    /* OHCI state */
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    /* Control partition */
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    uint32_t ctl, status;
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    uint32_t intr_status;
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    uint32_t intr;
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    /* memory pointer partition */
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    uint32_t hcca;
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    uint32_t ctrl_head, ctrl_cur;
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    uint32_t bulk_head, bulk_cur;
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    uint32_t per_cur;
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    uint32_t done;
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    int done_count;
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86
    /* Frame counter partition */
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    uint32_t fsmps:15;
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    uint32_t fit:1;
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    uint32_t fi:14;
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    uint32_t frt:1;
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    uint16_t frame_number;
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    uint16_t padding;
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    uint32_t pstart;
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    uint32_t lst;
95

    
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    /* Root Hub partition */
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    uint32_t rhdesc_a, rhdesc_b;
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    uint32_t rhstatus;
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    OHCIPort rhport[OHCI_MAX_PORTS];
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101
    /* PXA27x Non-OHCI events */
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    uint32_t hstatus;
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    uint32_t hmask;
104
    uint32_t hreset;
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    uint32_t htest;
106

    
107
    /* SM501 local memory offset */
108
    target_phys_addr_t localmem_base;
109

    
110
    /* Active packets.  */
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    uint32_t old_ctl;
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    USBPacket usb_packet;
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    uint8_t usb_buf[8192];
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    uint32_t async_td;
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    int async_complete;
116

    
117
} OHCIState;
118

    
119
/* Host Controller Communications Area */
120
struct ohci_hcca {
121
    uint32_t intr[32];
122
    uint16_t frame, pad;
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    uint32_t done;
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};
125

    
126
static void ohci_bus_stop(OHCIState *ohci);
127

    
128
/* Bitfields for the first word of an Endpoint Desciptor.  */
129
#define OHCI_ED_FA_SHIFT  0
130
#define OHCI_ED_FA_MASK   (0x7f<<OHCI_ED_FA_SHIFT)
131
#define OHCI_ED_EN_SHIFT  7
132
#define OHCI_ED_EN_MASK   (0xf<<OHCI_ED_EN_SHIFT)
133
#define OHCI_ED_D_SHIFT   11
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#define OHCI_ED_D_MASK    (3<<OHCI_ED_D_SHIFT)
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#define OHCI_ED_S         (1<<13)
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#define OHCI_ED_K         (1<<14)
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#define OHCI_ED_F         (1<<15)
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#define OHCI_ED_MPS_SHIFT 16
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#define OHCI_ED_MPS_MASK  (0x7ff<<OHCI_ED_MPS_SHIFT)
140

    
141
/* Flags in the head field of an Endpoint Desciptor.  */
142
#define OHCI_ED_H         1
143
#define OHCI_ED_C         2
144

    
145
/* Bitfields for the first word of a Transfer Desciptor.  */
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#define OHCI_TD_R         (1<<18)
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#define OHCI_TD_DP_SHIFT  19
148
#define OHCI_TD_DP_MASK   (3<<OHCI_TD_DP_SHIFT)
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#define OHCI_TD_DI_SHIFT  21
150
#define OHCI_TD_DI_MASK   (7<<OHCI_TD_DI_SHIFT)
151
#define OHCI_TD_T0        (1<<24)
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#define OHCI_TD_T1        (1<<24)
153
#define OHCI_TD_EC_SHIFT  26
154
#define OHCI_TD_EC_MASK   (3<<OHCI_TD_EC_SHIFT)
155
#define OHCI_TD_CC_SHIFT  28
156
#define OHCI_TD_CC_MASK   (0xf<<OHCI_TD_CC_SHIFT)
157

    
158
/* Bitfields for the first word of an Isochronous Transfer Desciptor.  */
159
/* CC & DI - same as in the General Transfer Desciptor */
160
#define OHCI_TD_SF_SHIFT  0
161
#define OHCI_TD_SF_MASK   (0xffff<<OHCI_TD_SF_SHIFT)
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#define OHCI_TD_FC_SHIFT  24
163
#define OHCI_TD_FC_MASK   (7<<OHCI_TD_FC_SHIFT)
164

    
165
/* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
166
#define OHCI_TD_PSW_CC_SHIFT 12
167
#define OHCI_TD_PSW_CC_MASK  (0xf<<OHCI_TD_PSW_CC_SHIFT)
168
#define OHCI_TD_PSW_SIZE_SHIFT 0
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#define OHCI_TD_PSW_SIZE_MASK  (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
170

    
171
#define OHCI_PAGE_MASK    0xfffff000
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#define OHCI_OFFSET_MASK  0xfff
173

    
174
#define OHCI_DPTR_MASK    0xfffffff0
175

    
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#define OHCI_BM(val, field) \
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  (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
178

    
179
#define OHCI_SET_BM(val, field, newval) do { \
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    val &= ~OHCI_##field##_MASK; \
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    val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
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    } while(0)
183

    
184
/* endpoint descriptor */
185
struct ohci_ed {
186
    uint32_t flags;
187
    uint32_t tail;
188
    uint32_t head;
189
    uint32_t next;
190
};
191

    
192
/* General transfer descriptor */
193
struct ohci_td {
194
    uint32_t flags;
195
    uint32_t cbp;
196
    uint32_t next;
197
    uint32_t be;
198
};
199

    
200
/* Isochronous transfer descriptor */
201
struct ohci_iso_td {
202
    uint32_t flags;
203
    uint32_t bp;
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    uint32_t next;
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    uint32_t be;
206
    uint16_t offset[8];
207
};
208

    
209
#define USB_HZ                      12000000
210

    
211
/* OHCI Local stuff */
212
#define OHCI_CTL_CBSR         ((1<<0)|(1<<1))
213
#define OHCI_CTL_PLE          (1<<2)
214
#define OHCI_CTL_IE           (1<<3)
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#define OHCI_CTL_CLE          (1<<4)
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#define OHCI_CTL_BLE          (1<<5)
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#define OHCI_CTL_HCFS         ((1<<6)|(1<<7))
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#define  OHCI_USB_RESET       0x00
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#define  OHCI_USB_RESUME      0x40
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#define  OHCI_USB_OPERATIONAL 0x80
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#define  OHCI_USB_SUSPEND     0xc0
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#define OHCI_CTL_IR           (1<<8)
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#define OHCI_CTL_RWC          (1<<9)
224
#define OHCI_CTL_RWE          (1<<10)
225

    
226
#define OHCI_STATUS_HCR       (1<<0)
227
#define OHCI_STATUS_CLF       (1<<1)
228
#define OHCI_STATUS_BLF       (1<<2)
229
#define OHCI_STATUS_OCR       (1<<3)
230
#define OHCI_STATUS_SOC       ((1<<6)|(1<<7))
231

    
232
#define OHCI_INTR_SO          (1<<0) /* Scheduling overrun */
233
#define OHCI_INTR_WD          (1<<1) /* HcDoneHead writeback */
234
#define OHCI_INTR_SF          (1<<2) /* Start of frame */
235
#define OHCI_INTR_RD          (1<<3) /* Resume detect */
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#define OHCI_INTR_UE          (1<<4) /* Unrecoverable error */
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#define OHCI_INTR_FNO         (1<<5) /* Frame number overflow */
238
#define OHCI_INTR_RHSC        (1<<6) /* Root hub status change */
239
#define OHCI_INTR_OC          (1<<30) /* Ownership change */
240
#define OHCI_INTR_MIE         (1<<31) /* Master Interrupt Enable */
241

    
242
#define OHCI_HCCA_SIZE        0x100
243
#define OHCI_HCCA_MASK        0xffffff00
244

    
245
#define OHCI_EDPTR_MASK       0xfffffff0
246

    
247
#define OHCI_FMI_FI           0x00003fff
248
#define OHCI_FMI_FSMPS        0xffff0000
249
#define OHCI_FMI_FIT          0x80000000
250

    
251
#define OHCI_FR_RT            (1<<31)
252

    
253
#define OHCI_LS_THRESH        0x628
254

    
255
#define OHCI_RHA_RW_MASK      0x00000000 /* Mask of supported features.  */
256
#define OHCI_RHA_PSM          (1<<8)
257
#define OHCI_RHA_NPS          (1<<9)
258
#define OHCI_RHA_DT           (1<<10)
259
#define OHCI_RHA_OCPM         (1<<11)
260
#define OHCI_RHA_NOCP         (1<<12)
261
#define OHCI_RHA_POTPGT_MASK  0xff000000
262

    
263
#define OHCI_RHS_LPS          (1<<0)
264
#define OHCI_RHS_OCI          (1<<1)
265
#define OHCI_RHS_DRWE         (1<<15)
266
#define OHCI_RHS_LPSC         (1<<16)
267
#define OHCI_RHS_OCIC         (1<<17)
268
#define OHCI_RHS_CRWE         (1<<31)
269

    
270
#define OHCI_PORT_CCS         (1<<0)
271
#define OHCI_PORT_PES         (1<<1)
272
#define OHCI_PORT_PSS         (1<<2)
273
#define OHCI_PORT_POCI        (1<<3)
274
#define OHCI_PORT_PRS         (1<<4)
275
#define OHCI_PORT_PPS         (1<<8)
276
#define OHCI_PORT_LSDA        (1<<9)
277
#define OHCI_PORT_CSC         (1<<16)
278
#define OHCI_PORT_PESC        (1<<17)
279
#define OHCI_PORT_PSSC        (1<<18)
280
#define OHCI_PORT_OCIC        (1<<19)
281
#define OHCI_PORT_PRSC        (1<<20)
282
#define OHCI_PORT_WTC         (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
283
                               |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
284

    
285
#define OHCI_TD_DIR_SETUP     0x0
286
#define OHCI_TD_DIR_OUT       0x1
287
#define OHCI_TD_DIR_IN        0x2
288
#define OHCI_TD_DIR_RESERVED  0x3
289

    
290
#define OHCI_CC_NOERROR             0x0
291
#define OHCI_CC_CRC                 0x1
292
#define OHCI_CC_BITSTUFFING         0x2
293
#define OHCI_CC_DATATOGGLEMISMATCH  0x3
294
#define OHCI_CC_STALL               0x4
295
#define OHCI_CC_DEVICENOTRESPONDING 0x5
296
#define OHCI_CC_PIDCHECKFAILURE     0x6
297
#define OHCI_CC_UNDEXPETEDPID       0x7
298
#define OHCI_CC_DATAOVERRUN         0x8
299
#define OHCI_CC_DATAUNDERRUN        0x9
300
#define OHCI_CC_BUFFEROVERRUN       0xc
301
#define OHCI_CC_BUFFERUNDERRUN      0xd
302

    
303
#define OHCI_HRESET_FSBIR       (1 << 0)
304

    
305
/* Update IRQ levels */
306
static inline void ohci_intr_update(OHCIState *ohci)
307
{
308
    int level = 0;
309

    
310
    if ((ohci->intr & OHCI_INTR_MIE) &&
311
        (ohci->intr_status & ohci->intr))
312
        level = 1;
313

    
314
    qemu_set_irq(ohci->irq, level);
315
}
316

    
317
/* Set an interrupt */
318
static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
319
{
320
    ohci->intr_status |= intr;
321
    ohci_intr_update(ohci);
322
}
323

    
324
/* Attach or detach a device on a root hub port.  */
325
static void ohci_attach(USBPort *port1)
326
{
327
    OHCIState *s = port1->opaque;
328
    OHCIPort *port = &s->rhport[port1->index];
329

    
330
    /* set connect status */
331
    port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
332

    
333
    /* update speed */
334
    if (port->port.dev->speed == USB_SPEED_LOW) {
335
        port->ctrl |= OHCI_PORT_LSDA;
336
    } else {
337
        port->ctrl &= ~OHCI_PORT_LSDA;
338
    }
339

    
340
    /* notify of remote-wakeup */
341
    if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
342
        ohci_set_interrupt(s, OHCI_INTR_RD);
343
    }
344

    
345
    DPRINTF("usb-ohci: Attached port %d\n", port1->index);
346
}
347

    
348
static void ohci_detach(USBPort *port1)
349
{
350
    OHCIState *s = port1->opaque;
351
    OHCIPort *port = &s->rhport[port1->index];
352
    uint32_t old_state = port->ctrl;
353

    
354
    /* set connect status */
355
    if (port->ctrl & OHCI_PORT_CCS) {
356
        port->ctrl &= ~OHCI_PORT_CCS;
357
        port->ctrl |= OHCI_PORT_CSC;
358
    }
359
    /* disable port */
360
    if (port->ctrl & OHCI_PORT_PES) {
361
        port->ctrl &= ~OHCI_PORT_PES;
362
        port->ctrl |= OHCI_PORT_PESC;
363
    }
364
    DPRINTF("usb-ohci: Detached port %d\n", port1->index);
365

    
366
    if (old_state != port->ctrl)
367
        ohci_set_interrupt(s, OHCI_INTR_RHSC);
368
}
369

    
370
static void ohci_wakeup(USBDevice *dev)
371
{
372
    USBBus *bus = usb_bus_from_device(dev);
373
    OHCIState *s = container_of(bus, OHCIState, bus);
374
    int portnum = dev->port->index;
375
    OHCIPort *port = &s->rhport[portnum];
376
    if (port->ctrl & OHCI_PORT_PSS) {
377
        DPRINTF("usb-ohci: port %d: wakeup\n", portnum);
378
        port->ctrl |= OHCI_PORT_PSSC;
379
        port->ctrl &= ~OHCI_PORT_PSS;
380
        if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
381
            ohci_set_interrupt(s, OHCI_INTR_RD);
382
        }
383
    }
384
}
385

    
386
/* Reset the controller */
387
static void ohci_reset(void *opaque)
388
{
389
    OHCIState *ohci = opaque;
390
    OHCIPort *port;
391
    int i;
392

    
393
    ohci_bus_stop(ohci);
394
    ohci->ctl = 0;
395
    ohci->old_ctl = 0;
396
    ohci->status = 0;
397
    ohci->intr_status = 0;
398
    ohci->intr = OHCI_INTR_MIE;
399

    
400
    ohci->hcca = 0;
401
    ohci->ctrl_head = ohci->ctrl_cur = 0;
402
    ohci->bulk_head = ohci->bulk_cur = 0;
403
    ohci->per_cur = 0;
404
    ohci->done = 0;
405
    ohci->done_count = 7;
406

    
407
    /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
408
     * I took the value linux sets ...
409
     */
410
    ohci->fsmps = 0x2778;
411
    ohci->fi = 0x2edf;
412
    ohci->fit = 0;
413
    ohci->frt = 0;
414
    ohci->frame_number = 0;
415
    ohci->pstart = 0;
416
    ohci->lst = OHCI_LS_THRESH;
417

    
418
    ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
419
    ohci->rhdesc_b = 0x0; /* Impl. specific */
420
    ohci->rhstatus = 0;
421

    
422
    for (i = 0; i < ohci->num_ports; i++)
423
      {
424
        port = &ohci->rhport[i];
425
        port->ctrl = 0;
426
        if (port->port.dev) {
427
            usb_attach(&port->port, port->port.dev);
428
        }
429
      }
430
    if (ohci->async_td) {
431
        usb_cancel_packet(&ohci->usb_packet);
432
        ohci->async_td = 0;
433
    }
434
    DPRINTF("usb-ohci: Reset %s\n", ohci->name);
435
}
436

    
437
/* Get an array of dwords from main memory */
438
static inline int get_dwords(OHCIState *ohci,
439
                             uint32_t addr, uint32_t *buf, int num)
440
{
441
    int i;
442

    
443
    addr += ohci->localmem_base;
444

    
445
    for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
446
        cpu_physical_memory_read(addr, buf, sizeof(*buf));
447
        *buf = le32_to_cpu(*buf);
448
    }
449

    
450
    return 1;
451
}
452

    
453
/* Put an array of dwords in to main memory */
454
static inline int put_dwords(OHCIState *ohci,
455
                             uint32_t addr, uint32_t *buf, int num)
456
{
457
    int i;
458

    
459
    addr += ohci->localmem_base;
460

    
461
    for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
462
        uint32_t tmp = cpu_to_le32(*buf);
463
        cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
464
    }
465

    
466
    return 1;
467
}
468

    
469
/* Get an array of words from main memory */
470
static inline int get_words(OHCIState *ohci,
471
                            uint32_t addr, uint16_t *buf, int num)
472
{
473
    int i;
474

    
475
    addr += ohci->localmem_base;
476

    
477
    for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
478
        cpu_physical_memory_read(addr, buf, sizeof(*buf));
479
        *buf = le16_to_cpu(*buf);
480
    }
481

    
482
    return 1;
483
}
484

    
485
/* Put an array of words in to main memory */
486
static inline int put_words(OHCIState *ohci,
487
                            uint32_t addr, uint16_t *buf, int num)
488
{
489
    int i;
490

    
491
    addr += ohci->localmem_base;
492

    
493
    for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
494
        uint16_t tmp = cpu_to_le16(*buf);
495
        cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
496
    }
497

    
498
    return 1;
499
}
500

    
501
static inline int ohci_read_ed(OHCIState *ohci,
502
                               uint32_t addr, struct ohci_ed *ed)
503
{
504
    return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
505
}
506

    
507
static inline int ohci_read_td(OHCIState *ohci,
508
                               uint32_t addr, struct ohci_td *td)
509
{
510
    return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
511
}
512

    
513
static inline int ohci_read_iso_td(OHCIState *ohci,
514
                                   uint32_t addr, struct ohci_iso_td *td)
515
{
516
    return (get_dwords(ohci, addr, (uint32_t *)td, 4) &&
517
            get_words(ohci, addr + 16, td->offset, 8));
518
}
519

    
520
static inline int ohci_read_hcca(OHCIState *ohci,
521
                                 uint32_t addr, struct ohci_hcca *hcca)
522
{
523
    cpu_physical_memory_read(addr + ohci->localmem_base, hcca, sizeof(*hcca));
524
    return 1;
525
}
526

    
527
static inline int ohci_put_ed(OHCIState *ohci,
528
                              uint32_t addr, struct ohci_ed *ed)
529
{
530
    return put_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
531
}
532

    
533
static inline int ohci_put_td(OHCIState *ohci,
534
                              uint32_t addr, struct ohci_td *td)
535
{
536
    return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
537
}
538

    
539
static inline int ohci_put_iso_td(OHCIState *ohci,
540
                                  uint32_t addr, struct ohci_iso_td *td)
541
{
542
    return (put_dwords(ohci, addr, (uint32_t *)td, 4) &&
543
            put_words(ohci, addr + 16, td->offset, 8));
544
}
545

    
546
static inline int ohci_put_hcca(OHCIState *ohci,
547
                                uint32_t addr, struct ohci_hcca *hcca)
548
{
549
    cpu_physical_memory_write(addr + ohci->localmem_base, hcca, sizeof(*hcca));
550
    return 1;
551
}
552

    
553
/* Read/Write the contents of a TD from/to main memory.  */
554
static void ohci_copy_td(OHCIState *ohci, struct ohci_td *td,
555
                         uint8_t *buf, int len, int write)
556
{
557
    uint32_t ptr;
558
    uint32_t n;
559

    
560
    ptr = td->cbp;
561
    n = 0x1000 - (ptr & 0xfff);
562
    if (n > len)
563
        n = len;
564
    cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
565
    if (n == len)
566
        return;
567
    ptr = td->be & ~0xfffu;
568
    buf += n;
569
    cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
570
}
571

    
572
/* Read/Write the contents of an ISO TD from/to main memory.  */
573
static void ohci_copy_iso_td(OHCIState *ohci,
574
                             uint32_t start_addr, uint32_t end_addr,
575
                             uint8_t *buf, int len, int write)
576
{
577
    uint32_t ptr;
578
    uint32_t n;
579

    
580
    ptr = start_addr;
581
    n = 0x1000 - (ptr & 0xfff);
582
    if (n > len)
583
        n = len;
584
    cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
585
    if (n == len)
586
        return;
587
    ptr = end_addr & ~0xfffu;
588
    buf += n;
589
    cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
590
}
591

    
592
static void ohci_process_lists(OHCIState *ohci, int completion);
593

    
594
static void ohci_async_complete_packet(USBDevice *dev, USBPacket *packet)
595
{
596
    OHCIState *ohci = container_of(packet, OHCIState, usb_packet);
597
#ifdef DEBUG_PACKET
598
    DPRINTF("Async packet complete\n");
599
#endif
600
    ohci->async_complete = 1;
601
    ohci_process_lists(ohci, 1);
602
}
603

    
604
#define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
605

    
606
static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed,
607
                               int completion)
608
{
609
    int dir;
610
    size_t len = 0;
611
#ifdef DEBUG_ISOCH
612
    const char *str = NULL;
613
#endif
614
    int pid;
615
    int ret;
616
    int i;
617
    USBDevice *dev;
618
    struct ohci_iso_td iso_td;
619
    uint32_t addr;
620
    uint16_t starting_frame;
621
    int16_t relative_frame_number;
622
    int frame_count;
623
    uint32_t start_offset, next_offset, end_offset = 0;
624
    uint32_t start_addr, end_addr;
625

    
626
    addr = ed->head & OHCI_DPTR_MASK;
627

    
628
    if (!ohci_read_iso_td(ohci, addr, &iso_td)) {
629
        printf("usb-ohci: ISO_TD read error at %x\n", addr);
630
        return 0;
631
    }
632

    
633
    starting_frame = OHCI_BM(iso_td.flags, TD_SF);
634
    frame_count = OHCI_BM(iso_td.flags, TD_FC);
635
    relative_frame_number = USUB(ohci->frame_number, starting_frame); 
636

    
637
#ifdef DEBUG_ISOCH
638
    printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n"
639
           "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
640
           "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
641
           "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
642
           "frame_number 0x%.8x starting_frame 0x%.8x\n"
643
           "frame_count  0x%.8x relative %d\n"
644
           "di 0x%.8x cc 0x%.8x\n",
645
           ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK,
646
           iso_td.flags, iso_td.bp, iso_td.next, iso_td.be,
647
           iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3],
648
           iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7],
649
           ohci->frame_number, starting_frame, 
650
           frame_count, relative_frame_number,         
651
           OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC));
652
#endif
653

    
654
    if (relative_frame_number < 0) {
655
        DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
656
        return 1;
657
    } else if (relative_frame_number > frame_count) {
658
        /* ISO TD expired - retire the TD to the Done Queue and continue with
659
           the next ISO TD of the same ED */
660
        DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number, 
661
               frame_count);
662
        OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
663
        ed->head &= ~OHCI_DPTR_MASK;
664
        ed->head |= (iso_td.next & OHCI_DPTR_MASK);
665
        iso_td.next = ohci->done;
666
        ohci->done = addr;
667
        i = OHCI_BM(iso_td.flags, TD_DI);
668
        if (i < ohci->done_count)
669
            ohci->done_count = i;
670
        ohci_put_iso_td(ohci, addr, &iso_td);
671
        return 0;
672
    }
673

    
674
    dir = OHCI_BM(ed->flags, ED_D);
675
    switch (dir) {
676
    case OHCI_TD_DIR_IN:
677
#ifdef DEBUG_ISOCH
678
        str = "in";
679
#endif
680
        pid = USB_TOKEN_IN;
681
        break;
682
    case OHCI_TD_DIR_OUT:
683
#ifdef DEBUG_ISOCH
684
        str = "out";
685
#endif
686
        pid = USB_TOKEN_OUT;
687
        break;
688
    case OHCI_TD_DIR_SETUP:
689
#ifdef DEBUG_ISOCH
690
        str = "setup";
691
#endif
692
        pid = USB_TOKEN_SETUP;
693
        break;
694
    default:
695
        printf("usb-ohci: Bad direction %d\n", dir);
696
        return 1;
697
    }
698

    
699
    if (!iso_td.bp || !iso_td.be) {
700
        printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td.bp, iso_td.be);
701
        return 1;
702
    }
703

    
704
    start_offset = iso_td.offset[relative_frame_number];
705
    next_offset = iso_td.offset[relative_frame_number + 1];
706

    
707
    if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || 
708
        ((relative_frame_number < frame_count) && 
709
         !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
710
        printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n",
711
               start_offset, next_offset);
712
        return 1;
713
    }
714

    
715
    if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
716
        printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n",
717
                start_offset, next_offset);
718
        return 1;
719
    }
720

    
721
    if ((start_offset & 0x1000) == 0) {
722
        start_addr = (iso_td.bp & OHCI_PAGE_MASK) |
723
            (start_offset & OHCI_OFFSET_MASK);
724
    } else {
725
        start_addr = (iso_td.be & OHCI_PAGE_MASK) |
726
            (start_offset & OHCI_OFFSET_MASK);
727
    }
728

    
729
    if (relative_frame_number < frame_count) {
730
        end_offset = next_offset - 1;
731
        if ((end_offset & 0x1000) == 0) {
732
            end_addr = (iso_td.bp & OHCI_PAGE_MASK) |
733
                (end_offset & OHCI_OFFSET_MASK);
734
        } else {
735
            end_addr = (iso_td.be & OHCI_PAGE_MASK) |
736
                (end_offset & OHCI_OFFSET_MASK);
737
        }
738
    } else {
739
        /* Last packet in the ISO TD */
740
        end_addr = iso_td.be;
741
    }
742

    
743
    if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
744
        len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
745
            - (start_addr & OHCI_OFFSET_MASK);
746
    } else {
747
        len = end_addr - start_addr + 1;
748
    }
749

    
750
    if (len && dir != OHCI_TD_DIR_IN) {
751
        ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 0);
752
    }
753

    
754
    if (completion) {
755
        ret = ohci->usb_packet.len;
756
    } else {
757
        ret = USB_RET_NODEV;
758
        for (i = 0; i < ohci->num_ports; i++) {
759
            dev = ohci->rhport[i].port.dev;
760
            if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
761
                continue;
762
            ohci->usb_packet.pid = pid;
763
            ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
764
            ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
765
            ohci->usb_packet.data = ohci->usb_buf;
766
            ohci->usb_packet.len = len;
767
            ret = usb_handle_packet(dev, &ohci->usb_packet);
768
            if (ret != USB_RET_NODEV)
769
                break;
770
        }
771
    
772
        if (ret == USB_RET_ASYNC) {
773
            return 1;
774
        }
775
    }
776

    
777
#ifdef DEBUG_ISOCH
778
    printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n",
779
           start_offset, end_offset, start_addr, end_addr, str, len, ret);
780
#endif
781

    
782
    /* Writeback */
783
    if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) {
784
        /* IN transfer succeeded */
785
        ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 1);
786
        OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
787
                    OHCI_CC_NOERROR);
788
        OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret);
789
    } else if (dir == OHCI_TD_DIR_OUT && ret == len) {
790
        /* OUT transfer succeeded */
791
        OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
792
                    OHCI_CC_NOERROR);
793
        OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
794
    } else {
795
        if (ret > (ssize_t) len) {
796
            printf("usb-ohci: DataOverrun %d > %zu\n", ret, len);
797
            OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
798
                        OHCI_CC_DATAOVERRUN);
799
            OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
800
                        len);
801
        } else if (ret >= 0) {
802
            printf("usb-ohci: DataUnderrun %d\n", ret);
803
            OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
804
                        OHCI_CC_DATAUNDERRUN);
805
        } else {
806
            switch (ret) {
807
            case USB_RET_NODEV:
808
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
809
                            OHCI_CC_DEVICENOTRESPONDING);
810
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
811
                            0);
812
                break;
813
            case USB_RET_NAK:
814
            case USB_RET_STALL:
815
                printf("usb-ohci: got NAK/STALL %d\n", ret);
816
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
817
                            OHCI_CC_STALL);
818
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
819
                            0);
820
                break;
821
            default:
822
                printf("usb-ohci: Bad device response %d\n", ret);
823
                OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
824
                            OHCI_CC_UNDEXPETEDPID);
825
                break;
826
            }
827
        }
828
    }
829

    
830
    if (relative_frame_number == frame_count) {
831
        /* Last data packet of ISO TD - retire the TD to the Done Queue */
832
        OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR);
833
        ed->head &= ~OHCI_DPTR_MASK;
834
        ed->head |= (iso_td.next & OHCI_DPTR_MASK);
835
        iso_td.next = ohci->done;
836
        ohci->done = addr;
837
        i = OHCI_BM(iso_td.flags, TD_DI);
838
        if (i < ohci->done_count)
839
            ohci->done_count = i;
840
    }
841
    ohci_put_iso_td(ohci, addr, &iso_td);
842
    return 1;
843
}
844

    
845
/* Service a transport descriptor.
846
   Returns nonzero to terminate processing of this endpoint.  */
847

    
848
static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
849
{
850
    int dir;
851
    size_t len = 0;
852
#ifdef DEBUG_PACKET
853
    const char *str = NULL;
854
#endif
855
    int pid;
856
    int ret;
857
    int i;
858
    USBDevice *dev;
859
    struct ohci_td td;
860
    uint32_t addr;
861
    int flag_r;
862
    int completion;
863

    
864
    addr = ed->head & OHCI_DPTR_MASK;
865
    /* See if this TD has already been submitted to the device.  */
866
    completion = (addr == ohci->async_td);
867
    if (completion && !ohci->async_complete) {
868
#ifdef DEBUG_PACKET
869
        DPRINTF("Skipping async TD\n");
870
#endif
871
        return 1;
872
    }
873
    if (!ohci_read_td(ohci, addr, &td)) {
874
        fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
875
        return 0;
876
    }
877

    
878
    dir = OHCI_BM(ed->flags, ED_D);
879
    switch (dir) {
880
    case OHCI_TD_DIR_OUT:
881
    case OHCI_TD_DIR_IN:
882
        /* Same value.  */
883
        break;
884
    default:
885
        dir = OHCI_BM(td.flags, TD_DP);
886
        break;
887
    }
888

    
889
    switch (dir) {
890
    case OHCI_TD_DIR_IN:
891
#ifdef DEBUG_PACKET
892
        str = "in";
893
#endif
894
        pid = USB_TOKEN_IN;
895
        break;
896
    case OHCI_TD_DIR_OUT:
897
#ifdef DEBUG_PACKET
898
        str = "out";
899
#endif
900
        pid = USB_TOKEN_OUT;
901
        break;
902
    case OHCI_TD_DIR_SETUP:
903
#ifdef DEBUG_PACKET
904
        str = "setup";
905
#endif
906
        pid = USB_TOKEN_SETUP;
907
        break;
908
    default:
909
        fprintf(stderr, "usb-ohci: Bad direction\n");
910
        return 1;
911
    }
912
    if (td.cbp && td.be) {
913
        if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
914
            len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
915
        } else {
916
            len = (td.be - td.cbp) + 1;
917
        }
918

    
919
        if (len && dir != OHCI_TD_DIR_IN && !completion) {
920
            ohci_copy_td(ohci, &td, ohci->usb_buf, len, 0);
921
        }
922
    }
923

    
924
    flag_r = (td.flags & OHCI_TD_R) != 0;
925
#ifdef DEBUG_PACKET
926
    DPRINTF(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
927
            addr, (int64_t)len, str, flag_r, td.cbp, td.be);
928

    
929
    if (len > 0 && dir != OHCI_TD_DIR_IN) {
930
        DPRINTF("  data:");
931
        for (i = 0; i < len; i++)
932
            printf(" %.2x", ohci->usb_buf[i]);
933
        DPRINTF("\n");
934
    }
935
#endif
936
    if (completion) {
937
        ret = ohci->usb_packet.len;
938
        ohci->async_td = 0;
939
        ohci->async_complete = 0;
940
    } else {
941
        ret = USB_RET_NODEV;
942
        for (i = 0; i < ohci->num_ports; i++) {
943
            dev = ohci->rhport[i].port.dev;
944
            if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
945
                continue;
946

    
947
            if (ohci->async_td) {
948
                /* ??? The hardware should allow one active packet per
949
                   endpoint.  We only allow one active packet per controller.
950
                   This should be sufficient as long as devices respond in a
951
                   timely manner.
952
                 */
953
#ifdef DEBUG_PACKET
954
                DPRINTF("Too many pending packets\n");
955
#endif
956
                return 1;
957
            }
958
            ohci->usb_packet.pid = pid;
959
            ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
960
            ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
961
            ohci->usb_packet.data = ohci->usb_buf;
962
            ohci->usb_packet.len = len;
963
            ret = usb_handle_packet(dev, &ohci->usb_packet);
964
            if (ret != USB_RET_NODEV)
965
                break;
966
        }
967
#ifdef DEBUG_PACKET
968
        DPRINTF("ret=%d\n", ret);
969
#endif
970
        if (ret == USB_RET_ASYNC) {
971
            ohci->async_td = addr;
972
            return 1;
973
        }
974
    }
975
    if (ret >= 0) {
976
        if (dir == OHCI_TD_DIR_IN) {
977
            ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1);
978
#ifdef DEBUG_PACKET
979
            DPRINTF("  data:");
980
            for (i = 0; i < ret; i++)
981
                printf(" %.2x", ohci->usb_buf[i]);
982
            DPRINTF("\n");
983
#endif
984
        } else {
985
            ret = len;
986
        }
987
    }
988

    
989
    /* Writeback */
990
    if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
991
        /* Transmission succeeded.  */
992
        if (ret == len) {
993
            td.cbp = 0;
994
        } else {
995
            td.cbp += ret;
996
            if ((td.cbp & 0xfff) + ret > 0xfff) {
997
                td.cbp &= 0xfff;
998
                td.cbp |= td.be & ~0xfff;
999
            }
1000
        }
1001
        td.flags |= OHCI_TD_T1;
1002
        td.flags ^= OHCI_TD_T0;
1003
        OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
1004
        OHCI_SET_BM(td.flags, TD_EC, 0);
1005

    
1006
        ed->head &= ~OHCI_ED_C;
1007
        if (td.flags & OHCI_TD_T0)
1008
            ed->head |= OHCI_ED_C;
1009
    } else {
1010
        if (ret >= 0) {
1011
            DPRINTF("usb-ohci: Underrun\n");
1012
            OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
1013
        } else {
1014
            switch (ret) {
1015
            case USB_RET_NODEV:
1016
                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
1017
            case USB_RET_NAK:
1018
                DPRINTF("usb-ohci: got NAK\n");
1019
                return 1;
1020
            case USB_RET_STALL:
1021
                DPRINTF("usb-ohci: got STALL\n");
1022
                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
1023
                break;
1024
            case USB_RET_BABBLE:
1025
                DPRINTF("usb-ohci: got BABBLE\n");
1026
                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
1027
                break;
1028
            default:
1029
                fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
1030
                OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
1031
                OHCI_SET_BM(td.flags, TD_EC, 3);
1032
                break;
1033
            }
1034
        }
1035
        ed->head |= OHCI_ED_H;
1036
    }
1037

    
1038
    /* Retire this TD */
1039
    ed->head &= ~OHCI_DPTR_MASK;
1040
    ed->head |= td.next & OHCI_DPTR_MASK;
1041
    td.next = ohci->done;
1042
    ohci->done = addr;
1043
    i = OHCI_BM(td.flags, TD_DI);
1044
    if (i < ohci->done_count)
1045
        ohci->done_count = i;
1046
    ohci_put_td(ohci, addr, &td);
1047
    return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
1048
}
1049

    
1050
/* Service an endpoint list.  Returns nonzero if active TD were found.  */
1051
static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion)
1052
{
1053
    struct ohci_ed ed;
1054
    uint32_t next_ed;
1055
    uint32_t cur;
1056
    int active;
1057

    
1058
    active = 0;
1059

    
1060
    if (head == 0)
1061
        return 0;
1062

    
1063
    for (cur = head; cur; cur = next_ed) {
1064
        if (!ohci_read_ed(ohci, cur, &ed)) {
1065
            fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
1066
            return 0;
1067
        }
1068

    
1069
        next_ed = ed.next & OHCI_DPTR_MASK;
1070

    
1071
        if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
1072
            uint32_t addr;
1073
            /* Cancel pending packets for ED that have been paused.  */
1074
            addr = ed.head & OHCI_DPTR_MASK;
1075
            if (ohci->async_td && addr == ohci->async_td) {
1076
                usb_cancel_packet(&ohci->usb_packet);
1077
                ohci->async_td = 0;
1078
            }
1079
            continue;
1080
        }
1081

    
1082
        while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
1083
#ifdef DEBUG_PACKET
1084
            DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
1085
                    "h=%u c=%u\n  head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
1086
                    OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
1087
                    OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
1088
                    (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
1089
                    OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
1090
                    (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
1091
                    ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
1092
#endif
1093
            active = 1;
1094

    
1095
            if ((ed.flags & OHCI_ED_F) == 0) {
1096
                if (ohci_service_td(ohci, &ed))
1097
                    break;
1098
            } else {
1099
                /* Handle isochronous endpoints */
1100
                if (ohci_service_iso_td(ohci, &ed, completion))
1101
                    break;
1102
            }
1103
        }
1104

    
1105
        ohci_put_ed(ohci, cur, &ed);
1106
    }
1107

    
1108
    return active;
1109
}
1110

    
1111
/* Generate a SOF event, and set a timer for EOF */
1112
static void ohci_sof(OHCIState *ohci)
1113
{
1114
    ohci->sof_time = qemu_get_clock_ns(vm_clock);
1115
    qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time);
1116
    ohci_set_interrupt(ohci, OHCI_INTR_SF);
1117
}
1118

    
1119
/* Process Control and Bulk lists.  */
1120
static void ohci_process_lists(OHCIState *ohci, int completion)
1121
{
1122
    if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
1123
        if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) {
1124
            DPRINTF("usb-ohci: head %x, cur %x\n",
1125
                    ohci->ctrl_head, ohci->ctrl_cur);
1126
        }
1127
        if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
1128
            ohci->ctrl_cur = 0;
1129
            ohci->status &= ~OHCI_STATUS_CLF;
1130
        }
1131
    }
1132

    
1133
    if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
1134
        if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) {
1135
            ohci->bulk_cur = 0;
1136
            ohci->status &= ~OHCI_STATUS_BLF;
1137
        }
1138
    }
1139
}
1140

    
1141
/* Do frame processing on frame boundary */
1142
static void ohci_frame_boundary(void *opaque)
1143
{
1144
    OHCIState *ohci = opaque;
1145
    struct ohci_hcca hcca;
1146

    
1147
    ohci_read_hcca(ohci, ohci->hcca, &hcca);
1148

    
1149
    /* Process all the lists at the end of the frame */
1150
    if (ohci->ctl & OHCI_CTL_PLE) {
1151
        int n;
1152

    
1153
        n = ohci->frame_number & 0x1f;
1154
        ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0);
1155
    }
1156

    
1157
    /* Cancel all pending packets if either of the lists has been disabled.  */
1158
    if (ohci->async_td &&
1159
        ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
1160
        usb_cancel_packet(&ohci->usb_packet);
1161
        ohci->async_td = 0;
1162
    }
1163
    ohci->old_ctl = ohci->ctl;
1164
    ohci_process_lists(ohci, 0);
1165

    
1166
    /* Frame boundary, so do EOF stuf here */
1167
    ohci->frt = ohci->fit;
1168

    
1169
    /* Increment frame number and take care of endianness. */
1170
    ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
1171
    hcca.frame = cpu_to_le16(ohci->frame_number);
1172

    
1173
    if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
1174
        if (!ohci->done)
1175
            abort();
1176
        if (ohci->intr & ohci->intr_status)
1177
            ohci->done |= 1;
1178
        hcca.done = cpu_to_le32(ohci->done);
1179
        ohci->done = 0;
1180
        ohci->done_count = 7;
1181
        ohci_set_interrupt(ohci, OHCI_INTR_WD);
1182
    }
1183

    
1184
    if (ohci->done_count != 7 && ohci->done_count != 0)
1185
        ohci->done_count--;
1186

    
1187
    /* Do SOF stuff here */
1188
    ohci_sof(ohci);
1189

    
1190
    /* Writeback HCCA */
1191
    ohci_put_hcca(ohci, ohci->hcca, &hcca);
1192
}
1193

    
1194
/* Start sending SOF tokens across the USB bus, lists are processed in
1195
 * next frame
1196
 */
1197
static int ohci_bus_start(OHCIState *ohci)
1198
{
1199
    ohci->eof_timer = qemu_new_timer_ns(vm_clock,
1200
                    ohci_frame_boundary,
1201
                    ohci);
1202

    
1203
    if (ohci->eof_timer == NULL) {
1204
        fprintf(stderr, "usb-ohci: %s: qemu_new_timer_ns failed\n", ohci->name);
1205
        /* TODO: Signal unrecoverable error */
1206
        return 0;
1207
    }
1208

    
1209
    DPRINTF("usb-ohci: %s: USB Operational\n", ohci->name);
1210

    
1211
    ohci_sof(ohci);
1212

    
1213
    return 1;
1214
}
1215

    
1216
/* Stop sending SOF tokens on the bus */
1217
static void ohci_bus_stop(OHCIState *ohci)
1218
{
1219
    if (ohci->eof_timer)
1220
        qemu_del_timer(ohci->eof_timer);
1221
    ohci->eof_timer = NULL;
1222
}
1223

    
1224
/* Sets a flag in a port status register but only set it if the port is
1225
 * connected, if not set ConnectStatusChange flag. If flag is enabled
1226
 * return 1.
1227
 */
1228
static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
1229
{
1230
    int ret = 1;
1231

    
1232
    /* writing a 0 has no effect */
1233
    if (val == 0)
1234
        return 0;
1235

    
1236
    /* If CurrentConnectStatus is cleared we set
1237
     * ConnectStatusChange
1238
     */
1239
    if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
1240
        ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
1241
        if (ohci->rhstatus & OHCI_RHS_DRWE) {
1242
            /* TODO: CSC is a wakeup event */
1243
        }
1244
        return 0;
1245
    }
1246

    
1247
    if (ohci->rhport[i].ctrl & val)
1248
        ret = 0;
1249

    
1250
    /* set the bit */
1251
    ohci->rhport[i].ctrl |= val;
1252

    
1253
    return ret;
1254
}
1255

    
1256
/* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1257
static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
1258
{
1259
    val &= OHCI_FMI_FI;
1260

    
1261
    if (val != ohci->fi) {
1262
        DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
1263
            ohci->name, ohci->fi, ohci->fi);
1264
    }
1265

    
1266
    ohci->fi = val;
1267
}
1268

    
1269
static void ohci_port_power(OHCIState *ohci, int i, int p)
1270
{
1271
    if (p) {
1272
        ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
1273
    } else {
1274
        ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
1275
                    OHCI_PORT_CCS|
1276
                    OHCI_PORT_PSS|
1277
                    OHCI_PORT_PRS);
1278
    }
1279
}
1280

    
1281
/* Set HcControlRegister */
1282
static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
1283
{
1284
    uint32_t old_state;
1285
    uint32_t new_state;
1286

    
1287
    old_state = ohci->ctl & OHCI_CTL_HCFS;
1288
    ohci->ctl = val;
1289
    new_state = ohci->ctl & OHCI_CTL_HCFS;
1290

    
1291
    /* no state change */
1292
    if (old_state == new_state)
1293
        return;
1294

    
1295
    switch (new_state) {
1296
    case OHCI_USB_OPERATIONAL:
1297
        ohci_bus_start(ohci);
1298
        break;
1299
    case OHCI_USB_SUSPEND:
1300
        ohci_bus_stop(ohci);
1301
        DPRINTF("usb-ohci: %s: USB Suspended\n", ohci->name);
1302
        break;
1303
    case OHCI_USB_RESUME:
1304
        DPRINTF("usb-ohci: %s: USB Resume\n", ohci->name);
1305
        break;
1306
    case OHCI_USB_RESET:
1307
        ohci_reset(ohci);
1308
        DPRINTF("usb-ohci: %s: USB Reset\n", ohci->name);
1309
        break;
1310
    }
1311
}
1312

    
1313
static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
1314
{
1315
    uint16_t fr;
1316
    int64_t tks;
1317

    
1318
    if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
1319
        return (ohci->frt << 31);
1320

    
1321
    /* Being in USB operational state guarnatees sof_time was
1322
     * set already.
1323
     */
1324
    tks = qemu_get_clock_ns(vm_clock) - ohci->sof_time;
1325

    
1326
    /* avoid muldiv if possible */
1327
    if (tks >= usb_frame_time)
1328
        return (ohci->frt << 31);
1329

    
1330
    tks = muldiv64(1, tks, usb_bit_time);
1331
    fr = (uint16_t)(ohci->fi - tks);
1332

    
1333
    return (ohci->frt << 31) | fr;
1334
}
1335

    
1336

    
1337
/* Set root hub status */
1338
static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
1339
{
1340
    uint32_t old_state;
1341

    
1342
    old_state = ohci->rhstatus;
1343

    
1344
    /* write 1 to clear OCIC */
1345
    if (val & OHCI_RHS_OCIC)
1346
        ohci->rhstatus &= ~OHCI_RHS_OCIC;
1347

    
1348
    if (val & OHCI_RHS_LPS) {
1349
        int i;
1350

    
1351
        for (i = 0; i < ohci->num_ports; i++)
1352
            ohci_port_power(ohci, i, 0);
1353
        DPRINTF("usb-ohci: powered down all ports\n");
1354
    }
1355

    
1356
    if (val & OHCI_RHS_LPSC) {
1357
        int i;
1358

    
1359
        for (i = 0; i < ohci->num_ports; i++)
1360
            ohci_port_power(ohci, i, 1);
1361
        DPRINTF("usb-ohci: powered up all ports\n");
1362
    }
1363

    
1364
    if (val & OHCI_RHS_DRWE)
1365
        ohci->rhstatus |= OHCI_RHS_DRWE;
1366

    
1367
    if (val & OHCI_RHS_CRWE)
1368
        ohci->rhstatus &= ~OHCI_RHS_DRWE;
1369

    
1370
    if (old_state != ohci->rhstatus)
1371
        ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1372
}
1373

    
1374
/* Set root hub port status */
1375
static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
1376
{
1377
    uint32_t old_state;
1378
    OHCIPort *port;
1379

    
1380
    port = &ohci->rhport[portnum];
1381
    old_state = port->ctrl;
1382

    
1383
    /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1384
    if (val & OHCI_PORT_WTC)
1385
        port->ctrl &= ~(val & OHCI_PORT_WTC);
1386

    
1387
    if (val & OHCI_PORT_CCS)
1388
        port->ctrl &= ~OHCI_PORT_PES;
1389

    
1390
    ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
1391

    
1392
    if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
1393
        DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
1394
    }
1395

    
1396
    if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
1397
        DPRINTF("usb-ohci: port %d: RESET\n", portnum);
1398
        usb_send_msg(port->port.dev, USB_MSG_RESET);
1399
        port->ctrl &= ~OHCI_PORT_PRS;
1400
        /* ??? Should this also set OHCI_PORT_PESC.  */
1401
        port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
1402
    }
1403

    
1404
    /* Invert order here to ensure in ambiguous case, device is
1405
     * powered up...
1406
     */
1407
    if (val & OHCI_PORT_LSDA)
1408
        ohci_port_power(ohci, portnum, 0);
1409
    if (val & OHCI_PORT_PPS)
1410
        ohci_port_power(ohci, portnum, 1);
1411

    
1412
    if (old_state != port->ctrl)
1413
        ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1414

    
1415
    return;
1416
}
1417

    
1418
static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr)
1419
{
1420
    OHCIState *ohci = ptr;
1421
    uint32_t retval;
1422

    
1423
    addr &= 0xff;
1424

    
1425
    /* Only aligned reads are allowed on OHCI */
1426
    if (addr & 3) {
1427
        fprintf(stderr, "usb-ohci: Mis-aligned read\n");
1428
        return 0xffffffff;
1429
    } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1430
        /* HcRhPortStatus */
1431
        retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
1432
    } else {
1433
        switch (addr >> 2) {
1434
        case 0: /* HcRevision */
1435
            retval = 0x10;
1436
            break;
1437

    
1438
        case 1: /* HcControl */
1439
            retval = ohci->ctl;
1440
            break;
1441

    
1442
        case 2: /* HcCommandStatus */
1443
            retval = ohci->status;
1444
            break;
1445

    
1446
        case 3: /* HcInterruptStatus */
1447
            retval = ohci->intr_status;
1448
            break;
1449

    
1450
        case 4: /* HcInterruptEnable */
1451
        case 5: /* HcInterruptDisable */
1452
            retval = ohci->intr;
1453
            break;
1454

    
1455
        case 6: /* HcHCCA */
1456
            retval = ohci->hcca;
1457
            break;
1458

    
1459
        case 7: /* HcPeriodCurrentED */
1460
            retval = ohci->per_cur;
1461
            break;
1462

    
1463
        case 8: /* HcControlHeadED */
1464
            retval = ohci->ctrl_head;
1465
            break;
1466

    
1467
        case 9: /* HcControlCurrentED */
1468
            retval = ohci->ctrl_cur;
1469
            break;
1470

    
1471
        case 10: /* HcBulkHeadED */
1472
            retval = ohci->bulk_head;
1473
            break;
1474

    
1475
        case 11: /* HcBulkCurrentED */
1476
            retval = ohci->bulk_cur;
1477
            break;
1478

    
1479
        case 12: /* HcDoneHead */
1480
            retval = ohci->done;
1481
            break;
1482

    
1483
        case 13: /* HcFmInterretval */
1484
            retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
1485
            break;
1486

    
1487
        case 14: /* HcFmRemaining */
1488
            retval = ohci_get_frame_remaining(ohci);
1489
            break;
1490

    
1491
        case 15: /* HcFmNumber */
1492
            retval = ohci->frame_number;
1493
            break;
1494

    
1495
        case 16: /* HcPeriodicStart */
1496
            retval = ohci->pstart;
1497
            break;
1498

    
1499
        case 17: /* HcLSThreshold */
1500
            retval = ohci->lst;
1501
            break;
1502

    
1503
        case 18: /* HcRhDescriptorA */
1504
            retval = ohci->rhdesc_a;
1505
            break;
1506

    
1507
        case 19: /* HcRhDescriptorB */
1508
            retval = ohci->rhdesc_b;
1509
            break;
1510

    
1511
        case 20: /* HcRhStatus */
1512
            retval = ohci->rhstatus;
1513
            break;
1514

    
1515
        /* PXA27x specific registers */
1516
        case 24: /* HcStatus */
1517
            retval = ohci->hstatus & ohci->hmask;
1518
            break;
1519

    
1520
        case 25: /* HcHReset */
1521
            retval = ohci->hreset;
1522
            break;
1523

    
1524
        case 26: /* HcHInterruptEnable */
1525
            retval = ohci->hmask;
1526
            break;
1527

    
1528
        case 27: /* HcHInterruptTest */
1529
            retval = ohci->htest;
1530
            break;
1531

    
1532
        default:
1533
            fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr);
1534
            retval = 0xffffffff;
1535
        }
1536
    }
1537

    
1538
    return retval;
1539
}
1540

    
1541
static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val)
1542
{
1543
    OHCIState *ohci = ptr;
1544

    
1545
    addr &= 0xff;
1546

    
1547
    /* Only aligned reads are allowed on OHCI */
1548
    if (addr & 3) {
1549
        fprintf(stderr, "usb-ohci: Mis-aligned write\n");
1550
        return;
1551
    }
1552

    
1553
    if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1554
        /* HcRhPortStatus */
1555
        ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
1556
        return;
1557
    }
1558

    
1559
    switch (addr >> 2) {
1560
    case 1: /* HcControl */
1561
        ohci_set_ctl(ohci, val);
1562
        break;
1563

    
1564
    case 2: /* HcCommandStatus */
1565
        /* SOC is read-only */
1566
        val = (val & ~OHCI_STATUS_SOC);
1567

    
1568
        /* Bits written as '0' remain unchanged in the register */
1569
        ohci->status |= val;
1570

    
1571
        if (ohci->status & OHCI_STATUS_HCR)
1572
            ohci_reset(ohci);
1573
        break;
1574

    
1575
    case 3: /* HcInterruptStatus */
1576
        ohci->intr_status &= ~val;
1577
        ohci_intr_update(ohci);
1578
        break;
1579

    
1580
    case 4: /* HcInterruptEnable */
1581
        ohci->intr |= val;
1582
        ohci_intr_update(ohci);
1583
        break;
1584

    
1585
    case 5: /* HcInterruptDisable */
1586
        ohci->intr &= ~val;
1587
        ohci_intr_update(ohci);
1588
        break;
1589

    
1590
    case 6: /* HcHCCA */
1591
        ohci->hcca = val & OHCI_HCCA_MASK;
1592
        break;
1593

    
1594
    case 7: /* HcPeriodCurrentED */
1595
        /* Ignore writes to this read-only register, Linux does them */
1596
        break;
1597

    
1598
    case 8: /* HcControlHeadED */
1599
        ohci->ctrl_head = val & OHCI_EDPTR_MASK;
1600
        break;
1601

    
1602
    case 9: /* HcControlCurrentED */
1603
        ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
1604
        break;
1605

    
1606
    case 10: /* HcBulkHeadED */
1607
        ohci->bulk_head = val & OHCI_EDPTR_MASK;
1608
        break;
1609

    
1610
    case 11: /* HcBulkCurrentED */
1611
        ohci->bulk_cur = val & OHCI_EDPTR_MASK;
1612
        break;
1613

    
1614
    case 13: /* HcFmInterval */
1615
        ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
1616
        ohci->fit = (val & OHCI_FMI_FIT) >> 31;
1617
        ohci_set_frame_interval(ohci, val);
1618
        break;
1619

    
1620
    case 15: /* HcFmNumber */
1621
        break;
1622

    
1623
    case 16: /* HcPeriodicStart */
1624
        ohci->pstart = val & 0xffff;
1625
        break;
1626

    
1627
    case 17: /* HcLSThreshold */
1628
        ohci->lst = val & 0xffff;
1629
        break;
1630

    
1631
    case 18: /* HcRhDescriptorA */
1632
        ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
1633
        ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
1634
        break;
1635

    
1636
    case 19: /* HcRhDescriptorB */
1637
        break;
1638

    
1639
    case 20: /* HcRhStatus */
1640
        ohci_set_hub_status(ohci, val);
1641
        break;
1642

    
1643
    /* PXA27x specific registers */
1644
    case 24: /* HcStatus */
1645
        ohci->hstatus &= ~(val & ohci->hmask);
1646

    
1647
    case 25: /* HcHReset */
1648
        ohci->hreset = val & ~OHCI_HRESET_FSBIR;
1649
        if (val & OHCI_HRESET_FSBIR)
1650
            ohci_reset(ohci);
1651
        break;
1652

    
1653
    case 26: /* HcHInterruptEnable */
1654
        ohci->hmask = val;
1655
        break;
1656

    
1657
    case 27: /* HcHInterruptTest */
1658
        ohci->htest = val;
1659
        break;
1660

    
1661
    default:
1662
        fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr);
1663
        break;
1664
    }
1665
}
1666

    
1667
static void ohci_device_destroy(USBBus *bus, USBDevice *dev)
1668
{
1669
    OHCIState *ohci = container_of(bus, OHCIState, bus);
1670

    
1671
    if (ohci->async_td && ohci->usb_packet.owner == dev) {
1672
        usb_cancel_packet(&ohci->usb_packet);
1673
        ohci->async_td = 0;
1674
    }
1675
}
1676

    
1677
/* Only dword reads are defined on OHCI register space */
1678
static CPUReadMemoryFunc * const ohci_readfn[3]={
1679
    ohci_mem_read,
1680
    ohci_mem_read,
1681
    ohci_mem_read
1682
};
1683

    
1684
/* Only dword writes are defined on OHCI register space */
1685
static CPUWriteMemoryFunc * const ohci_writefn[3]={
1686
    ohci_mem_write,
1687
    ohci_mem_write,
1688
    ohci_mem_write
1689
};
1690

    
1691
static USBPortOps ohci_port_ops = {
1692
    .attach = ohci_attach,
1693
    .detach = ohci_detach,
1694
    .wakeup = ohci_wakeup,
1695
    .complete = ohci_async_complete_packet,
1696
};
1697

    
1698
static USBBusOps ohci_bus_ops = {
1699
    .device_destroy = ohci_device_destroy,
1700
};
1701

    
1702
static void usb_ohci_init(OHCIState *ohci, DeviceState *dev,
1703
                          int num_ports, uint32_t localmem_base)
1704
{
1705
    int i;
1706

    
1707
    if (usb_frame_time == 0) {
1708
#ifdef OHCI_TIME_WARP
1709
        usb_frame_time = get_ticks_per_sec();
1710
        usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000);
1711
#else
1712
        usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000);
1713
        if (get_ticks_per_sec() >= USB_HZ) {
1714
            usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ);
1715
        } else {
1716
            usb_bit_time = 1;
1717
        }
1718
#endif
1719
        DPRINTF("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n",
1720
                usb_frame_time, usb_bit_time);
1721
    }
1722

    
1723
    ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci,
1724
                                       DEVICE_LITTLE_ENDIAN);
1725
    ohci->localmem_base = localmem_base;
1726

    
1727
    ohci->name = dev->info->name;
1728

    
1729
    usb_bus_new(&ohci->bus, &ohci_bus_ops, dev);
1730
    ohci->num_ports = num_ports;
1731
    for (i = 0; i < num_ports; i++) {
1732
        usb_register_port(&ohci->bus, &ohci->rhport[i].port, ohci, i, &ohci_port_ops,
1733
                          USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1734
        usb_port_location(&ohci->rhport[i].port, NULL, i+1);
1735
    }
1736

    
1737
    ohci->async_td = 0;
1738
    qemu_register_reset(ohci_reset, ohci);
1739
}
1740

    
1741
typedef struct {
1742
    PCIDevice pci_dev;
1743
    OHCIState state;
1744
} OHCIPCIState;
1745

    
1746
static int usb_ohci_initfn_pci(struct PCIDevice *dev)
1747
{
1748
    OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev);
1749
    int num_ports = 3;
1750

    
1751
    pci_config_set_vendor_id(ohci->pci_dev.config, PCI_VENDOR_ID_APPLE);
1752
    pci_config_set_device_id(ohci->pci_dev.config,
1753
                             PCI_DEVICE_ID_APPLE_IPID_USB);
1754
    ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */
1755
    pci_config_set_class(ohci->pci_dev.config, PCI_CLASS_SERIAL_USB);
1756
    /* TODO: RST# value should be 0. */
1757
    ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
1758

    
1759
    usb_ohci_init(&ohci->state, &dev->qdev, num_ports, 0);
1760
    ohci->state.irq = ohci->pci_dev.irq[0];
1761

    
1762
    /* TODO: avoid cast below by using dev */
1763
    pci_register_bar_simple(&ohci->pci_dev, 0, 256, 0, ohci->state.mem);
1764
    return 0;
1765
}
1766

    
1767
void usb_ohci_init_pci(struct PCIBus *bus, int devfn)
1768
{
1769
    pci_create_simple(bus, devfn, "pci-ohci");
1770
}
1771

    
1772
typedef struct {
1773
    SysBusDevice busdev;
1774
    OHCIState ohci;
1775
    uint32_t num_ports;
1776
    target_phys_addr_t dma_offset;
1777
} OHCISysBusState;
1778

    
1779
static int ohci_init_pxa(SysBusDevice *dev)
1780
{
1781
    OHCISysBusState *s = FROM_SYSBUS(OHCISysBusState, dev);
1782

    
1783
    usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset);
1784
    sysbus_init_irq(dev, &s->ohci.irq);
1785
    sysbus_init_mmio(dev, 0x1000, s->ohci.mem);
1786

    
1787
    return 0;
1788
}
1789

    
1790
static PCIDeviceInfo ohci_pci_info = {
1791
    .qdev.name    = "pci-ohci",
1792
    .qdev.desc    = "Apple USB Controller",
1793
    .qdev.size    = sizeof(OHCIPCIState),
1794
    .init         = usb_ohci_initfn_pci,
1795
};
1796

    
1797
static SysBusDeviceInfo ohci_sysbus_info = {
1798
    .init         = ohci_init_pxa,
1799
    .qdev.name    = "sysbus-ohci",
1800
    .qdev.desc    = "OHCI USB Controller",
1801
    .qdev.size    = sizeof(OHCISysBusState),
1802
    .qdev.props = (Property[]) {
1803
        DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
1804
        DEFINE_PROP_TADDR("dma-offset", OHCISysBusState, dma_offset, 3),
1805
        DEFINE_PROP_END_OF_LIST(),
1806
    }
1807
};
1808

    
1809
static void ohci_register(void)
1810
{
1811
    pci_qdev_register(&ohci_pci_info);
1812
    sysbus_register_withprop(&ohci_sysbus_info);
1813
}
1814
device_init(ohci_register);