root / hw / ide / mmio.c @ 9c17d615
History | View | Annotate | Download (4 kB)
1 |
/*
|
---|---|
2 |
* QEMU IDE Emulation: mmio support (for embedded).
|
3 |
*
|
4 |
* Copyright (c) 2003 Fabrice Bellard
|
5 |
* Copyright (c) 2006 Openedhand Ltd.
|
6 |
*
|
7 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
8 |
* of this software and associated documentation files (the "Software"), to deal
|
9 |
* in the Software without restriction, including without limitation the rights
|
10 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
11 |
* copies of the Software, and to permit persons to whom the Software is
|
12 |
* furnished to do so, subject to the following conditions:
|
13 |
*
|
14 |
* The above copyright notice and this permission notice shall be included in
|
15 |
* all copies or substantial portions of the Software.
|
16 |
*
|
17 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
18 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
19 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
20 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
21 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
22 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
23 |
* THE SOFTWARE.
|
24 |
*/
|
25 |
#include <hw/hw.h> |
26 |
#include "block/block.h" |
27 |
#include "sysemu/dma.h" |
28 |
|
29 |
#include <hw/ide/internal.h> |
30 |
|
31 |
/***********************************************************/
|
32 |
/* MMIO based ide port
|
33 |
* This emulates IDE device connected directly to the CPU bus without
|
34 |
* dedicated ide controller, which is often seen on embedded boards.
|
35 |
*/
|
36 |
|
37 |
typedef struct { |
38 |
IDEBus bus; |
39 |
int shift;
|
40 |
MemoryRegion iomem1, iomem2; |
41 |
} MMIOState; |
42 |
|
43 |
static void mmio_ide_reset(void *opaque) |
44 |
{ |
45 |
MMIOState *s = opaque; |
46 |
|
47 |
ide_bus_reset(&s->bus); |
48 |
} |
49 |
|
50 |
static uint64_t mmio_ide_read(void *opaque, hwaddr addr, |
51 |
unsigned size)
|
52 |
{ |
53 |
MMIOState *s = opaque; |
54 |
addr >>= s->shift; |
55 |
if (addr & 7) |
56 |
return ide_ioport_read(&s->bus, addr);
|
57 |
else
|
58 |
return ide_data_readw(&s->bus, 0); |
59 |
} |
60 |
|
61 |
static void mmio_ide_write(void *opaque, hwaddr addr, |
62 |
uint64_t val, unsigned size)
|
63 |
{ |
64 |
MMIOState *s = opaque; |
65 |
addr >>= s->shift; |
66 |
if (addr & 7) |
67 |
ide_ioport_write(&s->bus, addr, val); |
68 |
else
|
69 |
ide_data_writew(&s->bus, 0, val);
|
70 |
} |
71 |
|
72 |
static const MemoryRegionOps mmio_ide_ops = { |
73 |
.read = mmio_ide_read, |
74 |
.write = mmio_ide_write, |
75 |
.endianness = DEVICE_NATIVE_ENDIAN, |
76 |
}; |
77 |
|
78 |
static uint64_t mmio_ide_status_read(void *opaque, hwaddr addr, |
79 |
unsigned size)
|
80 |
{ |
81 |
MMIOState *s= opaque; |
82 |
return ide_status_read(&s->bus, 0); |
83 |
} |
84 |
|
85 |
static void mmio_ide_cmd_write(void *opaque, hwaddr addr, |
86 |
uint64_t val, unsigned size)
|
87 |
{ |
88 |
MMIOState *s = opaque; |
89 |
ide_cmd_write(&s->bus, 0, val);
|
90 |
} |
91 |
|
92 |
static const MemoryRegionOps mmio_ide_cs_ops = { |
93 |
.read = mmio_ide_status_read, |
94 |
.write = mmio_ide_cmd_write, |
95 |
.endianness = DEVICE_NATIVE_ENDIAN, |
96 |
}; |
97 |
|
98 |
static const VMStateDescription vmstate_ide_mmio = { |
99 |
.name = "mmio-ide",
|
100 |
.version_id = 3,
|
101 |
.minimum_version_id = 0,
|
102 |
.minimum_version_id_old = 0,
|
103 |
.fields = (VMStateField []) { |
104 |
VMSTATE_IDE_BUS(bus, MMIOState), |
105 |
VMSTATE_IDE_DRIVES(bus.ifs, MMIOState), |
106 |
VMSTATE_END_OF_LIST() |
107 |
} |
108 |
}; |
109 |
|
110 |
void mmio_ide_init (hwaddr membase, hwaddr membase2,
|
111 |
MemoryRegion *address_space, |
112 |
qemu_irq irq, int shift,
|
113 |
DriveInfo *hd0, DriveInfo *hd1) |
114 |
{ |
115 |
MMIOState *s = g_malloc0(sizeof(MMIOState));
|
116 |
|
117 |
ide_init2_with_non_qdev_drives(&s->bus, hd0, hd1, irq); |
118 |
|
119 |
s->shift = shift; |
120 |
|
121 |
memory_region_init_io(&s->iomem1, &mmio_ide_ops, s, |
122 |
"ide-mmio.1", 16 << shift); |
123 |
memory_region_init_io(&s->iomem2, &mmio_ide_cs_ops, s, |
124 |
"ide-mmio.2", 2 << shift); |
125 |
memory_region_add_subregion(address_space, membase, &s->iomem1); |
126 |
memory_region_add_subregion(address_space, membase2, &s->iomem2); |
127 |
vmstate_register(NULL, 0, &vmstate_ide_mmio, s); |
128 |
qemu_register_reset(mmio_ide_reset, s); |
129 |
} |
130 |
|