Revision 9c2149c8 target-mips/cpu.h
b/target-mips/cpu.h | ||
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44 | 44 |
typedef struct tlb_t tlb_t; |
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struct tlb_t { |
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target_ulong VPN; |
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uint_fast32_t PageMask;
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uint32_t PageMask; |
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48 | 48 |
uint_fast8_t ASID; |
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uint_fast16_t G:1; |
50 | 50 |
uint_fast16_t C0:3; |
... | ... | |
110 | 110 |
tlb_t tlb[MIPS_TLB_MAX]; |
111 | 111 |
uint32_t tlb_in_use; |
112 | 112 |
#endif |
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uint32_t CP0_index;
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uint32_t CP0_random;
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uint64_t CP0_EntryLo0;
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uint64_t CP0_EntryLo1;
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uint64_t CP0_Context;
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uint32_t CP0_PageMask;
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uint32_t CP0_PageGrain;
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uint32_t CP0_Wired;
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uint32_t CP0_HWREna;
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int32_t CP0_Index;
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int32_t CP0_Random;
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target_ulong CP0_EntryLo0;
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target_ulong CP0_EntryLo1;
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target_ulong CP0_Context;
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int32_t CP0_PageMask; |
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int32_t CP0_PageGrain; |
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int32_t CP0_Wired; |
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int32_t CP0_HWREna; |
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122 | 122 |
target_ulong CP0_BadVAddr; |
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uint32_t CP0_Count;
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uint64_t CP0_EntryHi;
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uint32_t CP0_Compare;
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uint32_t CP0_Status;
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int32_t CP0_Count; |
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target_ulong CP0_EntryHi;
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int32_t CP0_Compare; |
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int32_t CP0_Status; |
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127 | 127 |
#define CP0St_CU3 31 |
128 | 128 |
#define CP0St_CU2 30 |
129 | 129 |
#define CP0St_CU1 29 |
... | ... | |
146 | 146 |
#define CP0St_ERL 2 |
147 | 147 |
#define CP0St_EXL 1 |
148 | 148 |
#define CP0St_IE 0 |
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uint32_t CP0_IntCtl; |
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uint32_t CP0_SRSCtl; |
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uint32_t CP0_Cause; |
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int32_t CP0_IntCtl; |
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int32_t CP0_SRSCtl; |
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int32_t CP0_SRSMap; |
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int32_t CP0_Cause; |
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152 | 153 |
#define CP0Ca_BD 31 |
153 | 154 |
#define CP0Ca_TI 30 |
154 | 155 |
#define CP0Ca_CE 28 |
... | ... | |
159 | 160 |
#define CP0Ca_IP 8 |
160 | 161 |
#define CP0Ca_EC 2 |
161 | 162 |
target_ulong CP0_EPC; |
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uint32_t CP0_PRid;
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int32_t CP0_PRid; |
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163 | 164 |
target_ulong CP0_EBase; |
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uint32_t CP0_Config0;
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int32_t CP0_Config0; |
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165 | 166 |
#define CP0C0_M 31 |
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#define CP0C0_K23 28 |
167 | 168 |
#define CP0C0_KU 25 |
... | ... | |
174 | 175 |
#define CP0C0_MT 7 |
175 | 176 |
#define CP0C0_VI 3 |
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#define CP0C0_K0 0 |
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uint32_t CP0_Config1;
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int32_t CP0_Config1; |
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178 | 179 |
#define CP0C1_M 31 |
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#define CP0C1_MMU 25 |
180 | 181 |
#define CP0C1_IS 22 |
... | ... | |
190 | 191 |
#define CP0C1_CA 2 |
191 | 192 |
#define CP0C1_EP 1 |
192 | 193 |
#define CP0C1_FP 0 |
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uint32_t CP0_Config2;
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int32_t CP0_Config2; |
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194 | 195 |
#define CP0C2_M 31 |
195 | 196 |
#define CP0C2_TU 28 |
196 | 197 |
#define CP0C2_TS 24 |
... | ... | |
200 | 201 |
#define CP0C2_SS 8 |
201 | 202 |
#define CP0C2_SL 4 |
202 | 203 |
#define CP0C2_SA 0 |
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uint32_t CP0_Config3;
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int32_t CP0_Config3; |
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#define CP0C3_M 31 |
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#define CP0C3_DSPP 10 |
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#define CP0C3_LPA 7 |
... | ... | |
211 | 212 |
#define CP0C3_SM 1 |
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#define CP0C3_TL 0 |
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target_ulong CP0_LLAddr; |
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uint32_t CP0_WatchLo;
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uint32_t CP0_WatchHi;
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uint32_t CP0_XContext;
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uint32_t CP0_Framemask;
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uint32_t CP0_Debug;
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target_ulong CP0_WatchLo;
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int32_t CP0_WatchHi; |
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target_ulong CP0_XContext;
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int32_t CP0_Framemask; |
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int32_t CP0_Debug; |
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219 | 220 |
#define CPDB_DBD 31 |
220 | 221 |
#define CP0DB_DM 30 |
221 | 222 |
#define CP0DB_LSNM 28 |
... | ... | |
235 | 236 |
#define CP0DB_DBp 1 |
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#define CP0DB_DSS 0 |
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target_ulong CP0_DEPC; |
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uint32_t CP0_Performance0;
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uint32_t CP0_TagLo;
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uint32_t CP0_DataLo;
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uint32_t CP0_TagHi;
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uint32_t CP0_DataHi;
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int32_t CP0_Performance0; |
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int32_t CP0_TagLo; |
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int32_t CP0_DataLo; |
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int32_t CP0_TagHi; |
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int32_t CP0_DataHi; |
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target_ulong CP0_ErrorEPC; |
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uint32_t CP0_DESAVE;
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int32_t CP0_DESAVE; |
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/* Qemu */ |
246 | 247 |
int interrupt_request; |
247 | 248 |
jmp_buf jmp_env; |
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