Revision 9c2149c8 target-mips/cpu.h

b/target-mips/cpu.h
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typedef struct tlb_t tlb_t;
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struct tlb_t {
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    target_ulong VPN;
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    uint_fast32_t PageMask;
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    uint32_t PageMask;
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    uint_fast8_t ASID;
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    uint_fast16_t G:1;
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    uint_fast16_t C0:3;
......
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    tlb_t tlb[MIPS_TLB_MAX];
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    uint32_t tlb_in_use;
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#endif
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    uint32_t CP0_index;
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    uint32_t CP0_random;
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    uint64_t CP0_EntryLo0;
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    uint64_t CP0_EntryLo1;
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    uint64_t CP0_Context;
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    uint32_t CP0_PageMask;
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    uint32_t CP0_PageGrain;
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    uint32_t CP0_Wired;
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    uint32_t CP0_HWREna;
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    int32_t CP0_Index;
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    int32_t CP0_Random;
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    target_ulong CP0_EntryLo0;
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    target_ulong CP0_EntryLo1;
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    target_ulong CP0_Context;
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    int32_t CP0_PageMask;
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    int32_t CP0_PageGrain;
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    int32_t CP0_Wired;
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    int32_t CP0_HWREna;
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    target_ulong CP0_BadVAddr;
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    uint32_t CP0_Count;
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    uint64_t CP0_EntryHi;
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    uint32_t CP0_Compare;
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    uint32_t CP0_Status;
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    int32_t CP0_Count;
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    target_ulong CP0_EntryHi;
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    int32_t CP0_Compare;
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    int32_t CP0_Status;
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#define CP0St_CU3   31
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#define CP0St_CU2   30
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#define CP0St_CU1   29
......
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#define CP0St_ERL   2
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#define CP0St_EXL   1
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#define CP0St_IE    0
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    uint32_t CP0_IntCtl;
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    uint32_t CP0_SRSCtl;
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    uint32_t CP0_Cause;
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    int32_t CP0_IntCtl;
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    int32_t CP0_SRSCtl;
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    int32_t CP0_SRSMap;
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    int32_t CP0_Cause;
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#define CP0Ca_BD   31
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#define CP0Ca_TI   30
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#define CP0Ca_CE   28
......
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#define CP0Ca_IP    8
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#define CP0Ca_EC    2
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    target_ulong CP0_EPC;
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    uint32_t CP0_PRid;
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    int32_t CP0_PRid;
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    target_ulong CP0_EBase;
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    uint32_t CP0_Config0;
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    int32_t CP0_Config0;
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#define CP0C0_M    31
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#define CP0C0_K23  28
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#define CP0C0_KU   25
......
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#define CP0C0_MT   7
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#define CP0C0_VI   3
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#define CP0C0_K0   0
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    uint32_t CP0_Config1;
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    int32_t CP0_Config1;
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#define CP0C1_M    31
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#define CP0C1_MMU  25
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#define CP0C1_IS   22
......
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#define CP0C1_CA   2
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#define CP0C1_EP   1
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#define CP0C1_FP   0
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    uint32_t CP0_Config2;
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    int32_t CP0_Config2;
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#define CP0C2_M    31
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#define CP0C2_TU   28
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#define CP0C2_TS   24
......
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#define CP0C2_SS   8
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#define CP0C2_SL   4
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#define CP0C2_SA   0
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    uint32_t CP0_Config3;
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    int32_t CP0_Config3;
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#define CP0C3_M    31
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#define CP0C3_DSPP 10
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#define CP0C3_LPA  7
......
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#define CP0C3_SM   1
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#define CP0C3_TL   0
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    target_ulong CP0_LLAddr;
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    uint32_t CP0_WatchLo;
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    uint32_t CP0_WatchHi;
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    uint32_t CP0_XContext;
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    uint32_t CP0_Framemask;
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    uint32_t CP0_Debug;
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    target_ulong CP0_WatchLo;
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    int32_t CP0_WatchHi;
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    target_ulong CP0_XContext;
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    int32_t CP0_Framemask;
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    int32_t CP0_Debug;
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#define CPDB_DBD   31
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#define CP0DB_DM   30
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#define CP0DB_LSNM 28
......
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#define CP0DB_DBp  1
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#define CP0DB_DSS  0
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    target_ulong CP0_DEPC;
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    uint32_t CP0_Performance0;
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    uint32_t CP0_TagLo;
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    uint32_t CP0_DataLo;
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    uint32_t CP0_TagHi;
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    uint32_t CP0_DataHi;
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    int32_t CP0_Performance0;
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    int32_t CP0_TagLo;
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    int32_t CP0_DataLo;
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    int32_t CP0_TagHi;
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    int32_t CP0_DataHi;
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    target_ulong CP0_ErrorEPC;
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    uint32_t CP0_DESAVE;
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    int32_t CP0_DESAVE;
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    /* Qemu */
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    int interrupt_request;
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    jmp_buf jmp_env;

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