Revision 9c2149c8 target-mips/op_helper.c
| b/target-mips/op_helper.c | ||
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| 411 | 411 |
that might be a further win. */ |
| 412 | 412 |
mips_tlb_flush_extra (env, MIPS_TLB_NB); |
| 413 | 413 |
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/* Wildly undefined effects for CP0_index containing a too high value and
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/* Wildly undefined effects for CP0_Index containing a too high value and
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| 415 | 415 |
MIPS_TLB_NB not being a power of two. But so does real silicon. */ |
| 416 |
invalidate_tlb(env, env->CP0_index & (MIPS_TLB_NB - 1), 0);
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fill_tlb(env->CP0_index & (MIPS_TLB_NB - 1));
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invalidate_tlb(env, env->CP0_Index & (MIPS_TLB_NB - 1), 0);
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fill_tlb(env->CP0_Index & (MIPS_TLB_NB - 1));
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| 418 | 418 |
} |
| 419 | 419 |
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| 420 | 420 |
void do_tlbwr (void) |
| ... | ... | |
| 439 | 439 |
/* Check ASID, virtual page number & size */ |
| 440 | 440 |
if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
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/* TLB match */ |
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env->CP0_index = i;
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env->CP0_Index = i;
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break; |
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} |
| 445 | 445 |
} |
| ... | ... | |
| 455 | 455 |
} |
| 456 | 456 |
} |
| 457 | 457 |
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env->CP0_index |= 0x80000000;
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env->CP0_Index |= 0x80000000;
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| 459 | 459 |
} |
| 460 | 460 |
} |
| 461 | 461 |
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| ... | ... | |
| 465 | 465 |
uint8_t ASID; |
| 466 | 466 |
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ASID = env->CP0_EntryHi & 0xFF; |
| 468 |
tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
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tlb = &env->tlb[env->CP0_Index & (MIPS_TLB_NB - 1)];
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| 469 | 469 |
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/* If this will change the current ASID, flush qemu's TLB. */ |
| 471 | 471 |
if (ASID != tlb->ASID) |
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