Revision 9c76219e

b/cpu-all.h
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extern CPUState *first_cpu;
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extern CPUState *cpu_single_env;
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#define CPU_INTERRUPT_HARD   0x02 /* hardware interrupt pending */
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#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
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#define CPU_INTERRUPT_TIMER  0x08 /* internal timer exception pending */
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#define CPU_INTERRUPT_FIQ    0x10 /* Fast interrupt pending.  */
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#define CPU_INTERRUPT_HALT   0x20 /* CPU halt wanted */
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#define CPU_INTERRUPT_SMI    0x40 /* (x86 only) SMI interrupt pending */
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#define CPU_INTERRUPT_DEBUG  0x80 /* Debug event occured.  */
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#define CPU_INTERRUPT_VIRQ   0x100 /* virtual interrupt pending.  */
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#define CPU_INTERRUPT_NMI    0x200 /* NMI pending. */
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#define CPU_INTERRUPT_INIT   0x400 /* INIT pending. */
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#define CPU_INTERRUPT_SIPI   0x800 /* SIPI pending. */
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#define CPU_INTERRUPT_MCE    0x1000 /* (x86 only) MCE pending. */
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/* Flags for use in ENV->INTERRUPT_PENDING.
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   The numbers assigned here are non-sequential in order to preserve
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   binary compatibility with the vmstate dump.  Bit 0 (0x0001) was
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   previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
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   the vmstate dump.  */
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/* External hardware interrupt pending.  This is typically used for
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   interrupts from devices.  */
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#define CPU_INTERRUPT_HARD        0x0002
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/* Exit the current TB.  This is typically used when some system-level device
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   makes some change to the memory mapping.  E.g. the a20 line change.  */
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#define CPU_INTERRUPT_EXITTB      0x0004
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/* Halt the CPU.  */
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#define CPU_INTERRUPT_HALT        0x0020
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/* Debug event pending.  */
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#define CPU_INTERRUPT_DEBUG       0x0080
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/* Several target-specific external hardware interrupts.  Each target/cpu.h
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   should define proper names based on these defines.  */
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#define CPU_INTERRUPT_TGT_EXT_0   0x0008
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#define CPU_INTERRUPT_TGT_EXT_1   0x0010
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#define CPU_INTERRUPT_TGT_EXT_2   0x0040
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#define CPU_INTERRUPT_TGT_EXT_3   0x0200
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#define CPU_INTERRUPT_TGT_EXT_4   0x1000
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/* Several target-specific internal interrupts.  These differ from the
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   preceeding target-specific interrupts in that they are intended to
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   originate from within the cpu itself, typically in response to some
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   instruction being executed.  These, therefore, are not masked while
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   single-stepping within the debugger.  */
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#define CPU_INTERRUPT_TGT_INT_0   0x0100
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#define CPU_INTERRUPT_TGT_INT_1   0x0400
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#define CPU_INTERRUPT_TGT_INT_2   0x0800
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/* First unused bit: 0x2000.  */
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/* Temporary remapping from the generic names back to the previous
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   cpu-specific names.  These will be moved to target-foo/cpu.h next.  */
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#define CPU_INTERRUPT_TIMER       CPU_INTERRUPT_TGT_EXT_0
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#define CPU_INTERRUPT_FIQ         CPU_INTERRUPT_TGT_EXT_1
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#define CPU_INTERRUPT_SMI         CPU_INTERRUPT_TGT_EXT_2
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#define CPU_INTERRUPT_VIRQ        CPU_INTERRUPT_TGT_INT_0
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#define CPU_INTERRUPT_NMI         CPU_INTERRUPT_TGT_EXT_3
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#define CPU_INTERRUPT_INIT        CPU_INTERRUPT_TGT_INT_1
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#define CPU_INTERRUPT_SIPI        CPU_INTERRUPT_TGT_INT_2
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#define CPU_INTERRUPT_MCE         CPU_INTERRUPT_TGT_EXT_4
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#ifndef CONFIG_USER_ONLY
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typedef void (*CPUInterruptHandler)(CPUState *, int);
b/poison.h
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#pragma GCC poison CPU_INTERRUPT_DEBUG
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#pragma GCC poison CPU_INTERRUPT_VIRQ
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#pragma GCC poison CPU_INTERRUPT_NMI
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#pragma GCC poison CPU_INTERRUPT_TGT_EXT_0
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#pragma GCC poison CPU_INTERRUPT_TGT_EXT_1
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#pragma GCC poison CPU_INTERRUPT_TGT_EXT_2
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#pragma GCC poison CPU_INTERRUPT_TGT_EXT_3
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#pragma GCC poison CPU_INTERRUPT_TGT_EXT_4
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#pragma GCC poison CPU_INTERRUPT_TGT_INT_0
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#pragma GCC poison CPU_INTERRUPT_TGT_INT_1
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#pragma GCC poison CPU_INTERRUPT_TGT_INT_2
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#endif
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#endif

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