root / hw / pflash_cfi02.c @ 9c9bb6c8
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| 1 |
/*
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* CFI parallel flash with AMD command set emulation
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*
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* Copyright (c) 2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* For now, this code can emulate flashes of 1, 2 or 4 bytes width.
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* Supported commands/modes are:
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* - flash read
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* - flash write
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* - flash ID read
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* - sector erase
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* - chip erase
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* - unlock bypass command
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* - CFI queries
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*
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* It does not support flash interleaving.
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* It does not implement boot blocs with reduced size
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* It does not implement software data protection as found in many real chips
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* It does not implement erase suspend/resume commands
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* It does not implement multiple sectors erase
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*/
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#include "hw.h" |
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#include "flash.h" |
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#include "qemu-timer.h" |
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#include "block.h" |
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|
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//#define PFLASH_DEBUG
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#ifdef PFLASH_DEBUG
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#define DPRINTF(fmt, args...) \
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do { \
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printf("PFLASH: " fmt , ##args); \ |
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} while (0) |
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#else
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#define DPRINTF(fmt, args...) do { } while (0) |
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#endif
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|
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struct pflash_t {
|
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BlockDriverState *bs; |
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target_phys_addr_t base; |
| 57 |
uint32_t sector_len; |
| 58 |
uint32_t chip_len; |
| 59 |
int mappings;
|
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int width;
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int wcycle; /* if 0, the flash is read normally */ |
| 62 |
int bypass;
|
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int ro;
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uint8_t cmd; |
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uint8_t status; |
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uint16_t ident[4];
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uint16_t unlock_addr[2];
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uint8_t cfi_len; |
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uint8_t cfi_table[0x52];
|
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QEMUTimer *timer; |
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ram_addr_t off; |
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int fl_mem;
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int rom_mode;
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void *storage;
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}; |
| 76 |
|
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static void pflash_register_memory(pflash_t *pfl, int rom_mode) |
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{
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unsigned long phys_offset = pfl->fl_mem; |
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int i;
|
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|
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if (rom_mode)
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phys_offset |= pfl->off | IO_MEM_ROMD; |
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pfl->rom_mode = rom_mode; |
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|
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for (i = 0; i < pfl->mappings; i++) |
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cpu_register_physical_memory(pfl->base + i * pfl->chip_len, |
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pfl->chip_len, phys_offset); |
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} |
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|
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static void pflash_timer (void *opaque) |
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{
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pflash_t *pfl = opaque; |
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|
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DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
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/* Reset flash */
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pfl->status ^= 0x80;
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if (pfl->bypass) {
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pfl->wcycle = 2;
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} else {
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pflash_register_memory(pfl, 1);
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pfl->wcycle = 0;
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} |
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pfl->cmd = 0;
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} |
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|
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static uint32_t pflash_read (pflash_t *pfl, uint32_t offset, int width) |
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{
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uint32_t boff; |
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uint32_t ret; |
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uint8_t *p; |
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|
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DPRINTF("%s: offset " TARGET_FMT_lx "\n", __func__, offset); |
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ret = -1;
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if (pfl->rom_mode) {
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offset -= (uint32_t)(long)pfl->storage;
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/* Lazy reset of to ROMD mode */
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if (pfl->wcycle == 0) |
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pflash_register_memory(pfl, 1);
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} else
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offset -= pfl->base; |
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offset &= pfl->chip_len - 1;
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boff = offset & 0xFF;
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if (pfl->width == 2) |
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boff = boff >> 1;
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else if (pfl->width == 4) |
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boff = boff >> 2;
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switch (pfl->cmd) {
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default:
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/* This should never happen : reset state & treat it as a read*/
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DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
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pfl->wcycle = 0;
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pfl->cmd = 0;
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case 0x80: |
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/* We accept reads during second unlock sequence... */
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case 0x00: |
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flash_read:
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/* Flash area read */
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p = pfl->storage; |
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switch (width) {
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case 1: |
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ret = p[offset]; |
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// DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
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break;
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case 2: |
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#if defined(TARGET_WORDS_BIGENDIAN)
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ret = p[offset] << 8;
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ret |= p[offset + 1];
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#else
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ret = p[offset]; |
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ret |= p[offset + 1] << 8; |
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#endif
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// DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
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break;
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case 4: |
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#if defined(TARGET_WORDS_BIGENDIAN)
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ret = p[offset] << 24;
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ret |= p[offset + 1] << 16; |
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ret |= p[offset + 2] << 8; |
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ret |= p[offset + 3];
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#else
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ret = p[offset]; |
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ret |= p[offset + 1] << 8; |
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ret |= p[offset + 2] << 16; |
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ret |= p[offset + 3] << 24; |
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#endif
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// DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
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break;
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} |
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break;
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case 0x90: |
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/* flash ID read */
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switch (boff) {
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case 0x00: |
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case 0x01: |
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ret = pfl->ident[boff & 0x01];
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break;
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case 0x02: |
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ret = 0x00; /* Pretend all sectors are unprotected */ |
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break;
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case 0x0E: |
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case 0x0F: |
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if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1) |
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goto flash_read;
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ret = pfl->ident[2 + (boff & 0x01)]; |
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break;
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default:
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goto flash_read;
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} |
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DPRINTF("%s: ID " TARGET_FMT_ld " %x\n", __func__, boff, ret); |
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break;
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case 0xA0: |
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case 0x10: |
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case 0x30: |
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/* Status register read */
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ret = pfl->status; |
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DPRINTF("%s: status %x\n", __func__, ret);
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/* Toggle bit 6 */
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pfl->status ^= 0x40;
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break;
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case 0x98: |
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/* CFI query mode */
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if (boff > pfl->cfi_len)
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ret = 0;
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else
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ret = pfl->cfi_table[boff]; |
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break;
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} |
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return ret;
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} |
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|
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/* update flash content on disk */
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static void pflash_update(pflash_t *pfl, int offset, |
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int size)
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{
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int offset_end;
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if (pfl->bs) {
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offset_end = offset + size; |
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/* round to sectors */
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offset = offset >> 9;
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offset_end = (offset_end + 511) >> 9; |
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bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
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offset_end - offset); |
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} |
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} |
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static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value, |
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int width)
|
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{
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uint32_t boff; |
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uint8_t *p; |
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uint8_t cmd; |
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cmd = value; |
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if (pfl->cmd != 0xA0 && cmd == 0xF0) { |
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#if 0
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DPRINTF("%s: flash reset asked (%02x %02x)\n",
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__func__, pfl->cmd, cmd);
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#endif
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goto reset_flash;
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} |
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DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d %d\n", __func__, |
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offset, value, width, pfl->wcycle); |
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/* WARNING: when the memory area is in ROMD mode, the offset is a
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ram offset, not a physical address */
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if (pfl->rom_mode)
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offset -= (uint32_t)(long)pfl->storage;
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else
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offset -= pfl->base; |
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offset &= pfl->chip_len - 1;
|
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|
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DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d\n", __func__, |
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offset, value, width); |
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boff = offset & (pfl->sector_len - 1);
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if (pfl->width == 2) |
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boff = boff >> 1;
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else if (pfl->width == 4) |
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boff = boff >> 2;
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switch (pfl->wcycle) {
|
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case 0: |
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/* Set the device in I/O access mode if required */
|
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if (pfl->rom_mode)
|
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pflash_register_memory(pfl, 0);
|
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/* We're in read mode */
|
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check_unlock0:
|
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if (boff == 0x55 && cmd == 0x98) { |
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enter_CFI_mode:
|
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/* Enter CFI query mode */
|
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pfl->wcycle = 7;
|
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pfl->cmd = 0x98;
|
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return;
|
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} |
| 274 |
if (boff != pfl->unlock_addr[0] || cmd != 0xAA) { |
| 275 |
DPRINTF("%s: unlock0 failed " TARGET_FMT_lx " %02x %04x\n", |
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__func__, boff, cmd, pfl->unlock_addr[0]);
|
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goto reset_flash;
|
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} |
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DPRINTF("%s: unlock sequence started\n", __func__);
|
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break;
|
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case 1: |
| 282 |
/* We started an unlock sequence */
|
| 283 |
check_unlock1:
|
| 284 |
if (boff != pfl->unlock_addr[1] || cmd != 0x55) { |
| 285 |
DPRINTF("%s: unlock1 failed " TARGET_FMT_lx " %02x\n", __func__, |
| 286 |
boff, cmd); |
| 287 |
goto reset_flash;
|
| 288 |
} |
| 289 |
DPRINTF("%s: unlock sequence done\n", __func__);
|
| 290 |
break;
|
| 291 |
case 2: |
| 292 |
/* We finished an unlock sequence */
|
| 293 |
if (!pfl->bypass && boff != pfl->unlock_addr[0]) { |
| 294 |
DPRINTF("%s: command failed " TARGET_FMT_lx " %02x\n", __func__, |
| 295 |
boff, cmd); |
| 296 |
goto reset_flash;
|
| 297 |
} |
| 298 |
switch (cmd) {
|
| 299 |
case 0x20: |
| 300 |
pfl->bypass = 1;
|
| 301 |
goto do_bypass;
|
| 302 |
case 0x80: |
| 303 |
case 0x90: |
| 304 |
case 0xA0: |
| 305 |
pfl->cmd = cmd; |
| 306 |
DPRINTF("%s: starting command %02x\n", __func__, cmd);
|
| 307 |
break;
|
| 308 |
default:
|
| 309 |
DPRINTF("%s: unknown command %02x\n", __func__, cmd);
|
| 310 |
goto reset_flash;
|
| 311 |
} |
| 312 |
break;
|
| 313 |
case 3: |
| 314 |
switch (pfl->cmd) {
|
| 315 |
case 0x80: |
| 316 |
/* We need another unlock sequence */
|
| 317 |
goto check_unlock0;
|
| 318 |
case 0xA0: |
| 319 |
DPRINTF("%s: write data offset " TARGET_FMT_lx " %08x %d\n", |
| 320 |
__func__, offset, value, width); |
| 321 |
p = pfl->storage; |
| 322 |
switch (width) {
|
| 323 |
case 1: |
| 324 |
p[offset] &= value; |
| 325 |
pflash_update(pfl, offset, 1);
|
| 326 |
break;
|
| 327 |
case 2: |
| 328 |
#if defined(TARGET_WORDS_BIGENDIAN)
|
| 329 |
p[offset] &= value >> 8;
|
| 330 |
p[offset + 1] &= value;
|
| 331 |
#else
|
| 332 |
p[offset] &= value; |
| 333 |
p[offset + 1] &= value >> 8; |
| 334 |
#endif
|
| 335 |
pflash_update(pfl, offset, 2);
|
| 336 |
break;
|
| 337 |
case 4: |
| 338 |
#if defined(TARGET_WORDS_BIGENDIAN)
|
| 339 |
p[offset] &= value >> 24;
|
| 340 |
p[offset + 1] &= value >> 16; |
| 341 |
p[offset + 2] &= value >> 8; |
| 342 |
p[offset + 3] &= value;
|
| 343 |
#else
|
| 344 |
p[offset] &= value; |
| 345 |
p[offset + 1] &= value >> 8; |
| 346 |
p[offset + 2] &= value >> 16; |
| 347 |
p[offset + 3] &= value >> 24; |
| 348 |
#endif
|
| 349 |
pflash_update(pfl, offset, 4);
|
| 350 |
break;
|
| 351 |
} |
| 352 |
pfl->status = 0x00 | ~(value & 0x80); |
| 353 |
/* Let's pretend write is immediate */
|
| 354 |
if (pfl->bypass)
|
| 355 |
goto do_bypass;
|
| 356 |
goto reset_flash;
|
| 357 |
case 0x90: |
| 358 |
if (pfl->bypass && cmd == 0x00) { |
| 359 |
/* Unlock bypass reset */
|
| 360 |
goto reset_flash;
|
| 361 |
} |
| 362 |
/* We can enter CFI query mode from autoselect mode */
|
| 363 |
if (boff == 0x55 && cmd == 0x98) |
| 364 |
goto enter_CFI_mode;
|
| 365 |
/* No break here */
|
| 366 |
default:
|
| 367 |
DPRINTF("%s: invalid write for command %02x\n",
|
| 368 |
__func__, pfl->cmd); |
| 369 |
goto reset_flash;
|
| 370 |
} |
| 371 |
case 4: |
| 372 |
switch (pfl->cmd) {
|
| 373 |
case 0xA0: |
| 374 |
/* Ignore writes while flash data write is occuring */
|
| 375 |
/* As we suppose write is immediate, this should never happen */
|
| 376 |
return;
|
| 377 |
case 0x80: |
| 378 |
goto check_unlock1;
|
| 379 |
default:
|
| 380 |
/* Should never happen */
|
| 381 |
DPRINTF("%s: invalid command state %02x (wc 4)\n",
|
| 382 |
__func__, pfl->cmd); |
| 383 |
goto reset_flash;
|
| 384 |
} |
| 385 |
break;
|
| 386 |
case 5: |
| 387 |
switch (cmd) {
|
| 388 |
case 0x10: |
| 389 |
if (boff != pfl->unlock_addr[0]) { |
| 390 |
DPRINTF("%s: chip erase: invalid address " TARGET_FMT_lx "\n", |
| 391 |
__func__, offset); |
| 392 |
goto reset_flash;
|
| 393 |
} |
| 394 |
/* Chip erase */
|
| 395 |
DPRINTF("%s: start chip erase\n", __func__);
|
| 396 |
memset(pfl->storage, 0xFF, pfl->chip_len);
|
| 397 |
pfl->status = 0x00;
|
| 398 |
pflash_update(pfl, 0, pfl->chip_len);
|
| 399 |
/* Let's wait 5 seconds before chip erase is done */
|
| 400 |
qemu_mod_timer(pfl->timer, |
| 401 |
qemu_get_clock(vm_clock) + (ticks_per_sec * 5));
|
| 402 |
break;
|
| 403 |
case 0x30: |
| 404 |
/* Sector erase */
|
| 405 |
p = pfl->storage; |
| 406 |
offset &= ~(pfl->sector_len - 1);
|
| 407 |
DPRINTF("%s: start sector erase at " TARGET_FMT_lx "\n", __func__, |
| 408 |
offset); |
| 409 |
memset(p + offset, 0xFF, pfl->sector_len);
|
| 410 |
pflash_update(pfl, offset, pfl->sector_len); |
| 411 |
pfl->status = 0x00;
|
| 412 |
/* Let's wait 1/2 second before sector erase is done */
|
| 413 |
qemu_mod_timer(pfl->timer, |
| 414 |
qemu_get_clock(vm_clock) + (ticks_per_sec / 2));
|
| 415 |
break;
|
| 416 |
default:
|
| 417 |
DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
|
| 418 |
goto reset_flash;
|
| 419 |
} |
| 420 |
pfl->cmd = cmd; |
| 421 |
break;
|
| 422 |
case 6: |
| 423 |
switch (pfl->cmd) {
|
| 424 |
case 0x10: |
| 425 |
/* Ignore writes during chip erase */
|
| 426 |
return;
|
| 427 |
case 0x30: |
| 428 |
/* Ignore writes during sector erase */
|
| 429 |
return;
|
| 430 |
default:
|
| 431 |
/* Should never happen */
|
| 432 |
DPRINTF("%s: invalid command state %02x (wc 6)\n",
|
| 433 |
__func__, pfl->cmd); |
| 434 |
goto reset_flash;
|
| 435 |
} |
| 436 |
break;
|
| 437 |
case 7: /* Special value for CFI queries */ |
| 438 |
DPRINTF("%s: invalid write in CFI query mode\n", __func__);
|
| 439 |
goto reset_flash;
|
| 440 |
default:
|
| 441 |
/* Should never happen */
|
| 442 |
DPRINTF("%s: invalid write state (wc 7)\n", __func__);
|
| 443 |
goto reset_flash;
|
| 444 |
} |
| 445 |
pfl->wcycle++; |
| 446 |
|
| 447 |
return;
|
| 448 |
|
| 449 |
/* Reset flash */
|
| 450 |
reset_flash:
|
| 451 |
pfl->bypass = 0;
|
| 452 |
pfl->wcycle = 0;
|
| 453 |
pfl->cmd = 0;
|
| 454 |
return;
|
| 455 |
|
| 456 |
do_bypass:
|
| 457 |
pfl->wcycle = 2;
|
| 458 |
pfl->cmd = 0;
|
| 459 |
return;
|
| 460 |
} |
| 461 |
|
| 462 |
|
| 463 |
static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr) |
| 464 |
{
|
| 465 |
return pflash_read(opaque, addr, 1); |
| 466 |
} |
| 467 |
|
| 468 |
static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr) |
| 469 |
{
|
| 470 |
pflash_t *pfl = opaque; |
| 471 |
|
| 472 |
return pflash_read(pfl, addr, 2); |
| 473 |
} |
| 474 |
|
| 475 |
static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr) |
| 476 |
{
|
| 477 |
pflash_t *pfl = opaque; |
| 478 |
|
| 479 |
return pflash_read(pfl, addr, 4); |
| 480 |
} |
| 481 |
|
| 482 |
static void pflash_writeb (void *opaque, target_phys_addr_t addr, |
| 483 |
uint32_t value) |
| 484 |
{
|
| 485 |
pflash_write(opaque, addr, value, 1);
|
| 486 |
} |
| 487 |
|
| 488 |
static void pflash_writew (void *opaque, target_phys_addr_t addr, |
| 489 |
uint32_t value) |
| 490 |
{
|
| 491 |
pflash_t *pfl = opaque; |
| 492 |
|
| 493 |
pflash_write(pfl, addr, value, 2);
|
| 494 |
} |
| 495 |
|
| 496 |
static void pflash_writel (void *opaque, target_phys_addr_t addr, |
| 497 |
uint32_t value) |
| 498 |
{
|
| 499 |
pflash_t *pfl = opaque; |
| 500 |
|
| 501 |
pflash_write(pfl, addr, value, 4);
|
| 502 |
} |
| 503 |
|
| 504 |
static CPUWriteMemoryFunc *pflash_write_ops[] = {
|
| 505 |
&pflash_writeb, |
| 506 |
&pflash_writew, |
| 507 |
&pflash_writel, |
| 508 |
}; |
| 509 |
|
| 510 |
static CPUReadMemoryFunc *pflash_read_ops[] = {
|
| 511 |
&pflash_readb, |
| 512 |
&pflash_readw, |
| 513 |
&pflash_readl, |
| 514 |
}; |
| 515 |
|
| 516 |
/* Count trailing zeroes of a 32 bits quantity */
|
| 517 |
static int ctz32 (uint32_t n) |
| 518 |
{
|
| 519 |
int ret;
|
| 520 |
|
| 521 |
ret = 0;
|
| 522 |
if (!(n & 0xFFFF)) { |
| 523 |
ret += 16;
|
| 524 |
n = n >> 16;
|
| 525 |
} |
| 526 |
if (!(n & 0xFF)) { |
| 527 |
ret += 8;
|
| 528 |
n = n >> 8;
|
| 529 |
} |
| 530 |
if (!(n & 0xF)) { |
| 531 |
ret += 4;
|
| 532 |
n = n >> 4;
|
| 533 |
} |
| 534 |
if (!(n & 0x3)) { |
| 535 |
ret += 2;
|
| 536 |
n = n >> 2;
|
| 537 |
} |
| 538 |
if (!(n & 0x1)) { |
| 539 |
ret++; |
| 540 |
n = n >> 1;
|
| 541 |
} |
| 542 |
#if 0 /* This is not necessary as n is never 0 */
|
| 543 |
if (!n)
|
| 544 |
ret++;
|
| 545 |
#endif
|
| 546 |
|
| 547 |
return ret;
|
| 548 |
} |
| 549 |
|
| 550 |
pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, |
| 551 |
BlockDriverState *bs, uint32_t sector_len, |
| 552 |
int nb_blocs, int nb_mappings, int width, |
| 553 |
uint16_t id0, uint16_t id1, |
| 554 |
uint16_t id2, uint16_t id3, |
| 555 |
uint16_t unlock_addr0, uint16_t unlock_addr1) |
| 556 |
{
|
| 557 |
pflash_t *pfl; |
| 558 |
int32_t chip_len; |
| 559 |
|
| 560 |
chip_len = sector_len * nb_blocs; |
| 561 |
/* XXX: to be fixed */
|
| 562 |
#if 0
|
| 563 |
if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
|
| 564 |
total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
|
| 565 |
return NULL;
|
| 566 |
#endif
|
| 567 |
pfl = qemu_mallocz(sizeof(pflash_t));
|
| 568 |
if (pfl == NULL) |
| 569 |
return NULL; |
| 570 |
pfl->storage = phys_ram_base + off; |
| 571 |
pfl->fl_mem = cpu_register_io_memory(0, pflash_read_ops, pflash_write_ops,
|
| 572 |
pfl); |
| 573 |
pfl->off = off; |
| 574 |
pfl->base = base; |
| 575 |
pfl->chip_len = chip_len; |
| 576 |
pfl->mappings = nb_mappings; |
| 577 |
pflash_register_memory(pfl, 1);
|
| 578 |
pfl->bs = bs; |
| 579 |
if (pfl->bs) {
|
| 580 |
/* read the initial flash content */
|
| 581 |
bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9); |
| 582 |
} |
| 583 |
#if 0 /* XXX: there should be a bit to set up read-only,
|
| 584 |
* the same way the hardware does (with WP pin).
|
| 585 |
*/
|
| 586 |
pfl->ro = 1;
|
| 587 |
#else
|
| 588 |
pfl->ro = 0;
|
| 589 |
#endif
|
| 590 |
pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl); |
| 591 |
pfl->sector_len = sector_len; |
| 592 |
pfl->width = width; |
| 593 |
pfl->wcycle = 0;
|
| 594 |
pfl->cmd = 0;
|
| 595 |
pfl->status = 0;
|
| 596 |
pfl->ident[0] = id0;
|
| 597 |
pfl->ident[1] = id1;
|
| 598 |
pfl->ident[2] = id2;
|
| 599 |
pfl->ident[3] = id3;
|
| 600 |
pfl->unlock_addr[0] = unlock_addr0;
|
| 601 |
pfl->unlock_addr[1] = unlock_addr1;
|
| 602 |
/* Hardcoded CFI table (mostly from SG29 Spansion flash) */
|
| 603 |
pfl->cfi_len = 0x52;
|
| 604 |
/* Standard "QRY" string */
|
| 605 |
pfl->cfi_table[0x10] = 'Q'; |
| 606 |
pfl->cfi_table[0x11] = 'R'; |
| 607 |
pfl->cfi_table[0x12] = 'Y'; |
| 608 |
/* Command set (AMD/Fujitsu) */
|
| 609 |
pfl->cfi_table[0x13] = 0x02; |
| 610 |
pfl->cfi_table[0x14] = 0x00; |
| 611 |
/* Primary extended table address (none) */
|
| 612 |
pfl->cfi_table[0x15] = 0x00; |
| 613 |
pfl->cfi_table[0x16] = 0x00; |
| 614 |
/* Alternate command set (none) */
|
| 615 |
pfl->cfi_table[0x17] = 0x00; |
| 616 |
pfl->cfi_table[0x18] = 0x00; |
| 617 |
/* Alternate extended table (none) */
|
| 618 |
pfl->cfi_table[0x19] = 0x00; |
| 619 |
pfl->cfi_table[0x1A] = 0x00; |
| 620 |
/* Vcc min */
|
| 621 |
pfl->cfi_table[0x1B] = 0x27; |
| 622 |
/* Vcc max */
|
| 623 |
pfl->cfi_table[0x1C] = 0x36; |
| 624 |
/* Vpp min (no Vpp pin) */
|
| 625 |
pfl->cfi_table[0x1D] = 0x00; |
| 626 |
/* Vpp max (no Vpp pin) */
|
| 627 |
pfl->cfi_table[0x1E] = 0x00; |
| 628 |
/* Reserved */
|
| 629 |
pfl->cfi_table[0x1F] = 0x07; |
| 630 |
/* Timeout for min size buffer write (16 ?s) */
|
| 631 |
pfl->cfi_table[0x20] = 0x04; |
| 632 |
/* Typical timeout for block erase (512 ms) */
|
| 633 |
pfl->cfi_table[0x21] = 0x09; |
| 634 |
/* Typical timeout for full chip erase (4096 ms) */
|
| 635 |
pfl->cfi_table[0x22] = 0x0C; |
| 636 |
/* Reserved */
|
| 637 |
pfl->cfi_table[0x23] = 0x01; |
| 638 |
/* Max timeout for buffer write */
|
| 639 |
pfl->cfi_table[0x24] = 0x04; |
| 640 |
/* Max timeout for block erase */
|
| 641 |
pfl->cfi_table[0x25] = 0x0A; |
| 642 |
/* Max timeout for chip erase */
|
| 643 |
pfl->cfi_table[0x26] = 0x0D; |
| 644 |
/* Device size */
|
| 645 |
pfl->cfi_table[0x27] = ctz32(chip_len) + 1; |
| 646 |
/* Flash device interface (8 & 16 bits) */
|
| 647 |
pfl->cfi_table[0x28] = 0x02; |
| 648 |
pfl->cfi_table[0x29] = 0x00; |
| 649 |
/* Max number of bytes in multi-bytes write */
|
| 650 |
/* XXX: disable buffered write as it's not supported */
|
| 651 |
// pfl->cfi_table[0x2A] = 0x05;
|
| 652 |
pfl->cfi_table[0x2A] = 0x00; |
| 653 |
pfl->cfi_table[0x2B] = 0x00; |
| 654 |
/* Number of erase block regions (uniform) */
|
| 655 |
pfl->cfi_table[0x2C] = 0x01; |
| 656 |
/* Erase block region 1 */
|
| 657 |
pfl->cfi_table[0x2D] = nb_blocs - 1; |
| 658 |
pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8; |
| 659 |
pfl->cfi_table[0x2F] = sector_len >> 8; |
| 660 |
pfl->cfi_table[0x30] = sector_len >> 16; |
| 661 |
|
| 662 |
return pfl;
|
| 663 |
} |