Revision 9d05095e

b/cpu-exec.c
561 561 
#elif defined(TARGET_SH4)
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		    /* XXXXX */
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#endif
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                   /* Don't use the cached interupt_request value,
565 
                      do_interrupt may have updated the EXITTB flag. */
564 566 
                    if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
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                        env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
566 568 
                        /* ensure that no TB jump will be modified as
b/target-mips/helper.c
219 219 
                exception = EXCP_TLBS;
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            else
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                exception = EXCP_TLBL;
222 
            error_code = 0;
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            break;
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        case -4:
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            /* TLB match but 'D' bit is cleared */
......
350 349 
        cause = 4;
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        goto set_EPC;
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    case EXCP_TLBL:
353 
    case EXCP_TLBF:
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        cause = 2;
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        if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
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            offset = 0x000;

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