Archipelago » qemu

    return 0;

}

{

    uint8_t *pci_conf;

    uint16_t checksum = 0;

    static const char info_str[] = "e1000";

    int i;

    pci_conf = d->dev.config;

    memmove(d->eeprom_data, e1000_eeprom_template,

        sizeof e1000_eeprom_template);

    for (i = 0; i < 3; i++)

    for (i = 0; i < EEPROM_CHECKSUM_REG; i++)

        checksum += d->eeprom_data[i];

    checksum = (uint16_t) EEPROM_SUM - checksum;

    d->rxbuf_min_shift = 1;

    memset(&d->tx, 0, sizeof d->tx);

                                 e1000_receive, e1000_can_receive,

                                 e1000_cleanup, d);

    d->vc->link_status_changed = e1000_set_link_status;

    register_savevm(info_str, -1, 2, nic_save, nic_load, d);

    d->dev.unregister = pci_e1000_uninit;

}

    return 0;

}

{

    EEPRO100State *s;

    logout("\n");

    d->dev.unregister = pci_nic_uninit;

    s = &d->eepro100;

    pci_register_io_region(&d->dev, 2, PCI_FLASH_SIZE, PCI_ADDRESS_SPACE_MEM,

                           pci_mmio_map);

    logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6));

    assert(s->region[1] == 0);

    nic_reset(s);

                                 nic_receive, nic_can_receive,

                                 nic_cleanup, s);

    qemu_register_reset(nic_reset, s);

    register_savevm(s->vc->model, -1, 3, nic_save, nic_load, s);

}

{

}

{

}

{

}

    unregister_savevm("ne2000", s);

}

{

    NE2000State *s;

    uint8_t *pci_conf;

    pci_conf = d->dev.config;

    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);

    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8029);

    s = &d->ne2000;

    s->irq = d->dev.irq[0];

    s->pci_dev = (PCIDevice *)d;

    ne2000_reset(s);

                                 ne2000_receive, ne2000_can_receive,

                                 ne2000_cleanup, s);

    qemu_format_nic_info_str(s->vc, s->macaddr);

    register_savevm("ne2000", -1, 3, ne2000_save, ne2000_load, s);

}

    NULL

};

    NULL

};

PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,

                  const char *default_model)

{

    int i;

    qemu_check_nic_model_list(nd, pci_nic_models, default_model);

        if (strcmp(nd->model, pci_nic_models[i]) == 0) {

        }

    return NULL;

}

/* usb-ohci.c */

void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);

/* prep_pci.c */

PCIBus *pci_prep_init(qemu_irq *pic);

 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt

 */

#include "pci.h"

#include "net.h"

#include "qemu-timer.h"

typedef struct PCNetState_st PCNetState;

struct PCNetState_st {

    PCIDevice *pci_dev;

    VLANClientState *vc;

    QEMUTimer *poll_timer;

    uint32_t rdra, tdra;

    uint8_t prom[16];

    uint16_t csr[128];

    uint16_t bcr[32];

    uint64_t timer;

    uint8_t buffer[4096];

    int tx_busy;

    qemu_irq irq;

    void (*phys_mem_read)(void *dma_opaque, target_phys_addr_t addr,

                         uint8_t *buf, int len, int do_bswap);

    void (*phys_mem_write)(void *dma_opaque, target_phys_addr_t addr,

    int looptest;

};

struct qemu_ether_header {

    uint8_t ether_dhost[6];

    uint8_t ether_shost[6];

    /* Initialize the PROM */

    s->prom[12] = s->prom[13] = 0x00;

    s->prom[14] = s->prom[15] = 0x57;

static void pcnet_ioport_map(PCIDevice *pci_dev, int region_num,

                             uint32_t addr, uint32_t size, int type)

{

#ifdef PCNET_DEBUG_IO

    printf("pcnet_ioport_map addr=0x%04x size=0x%04x\n", addr, size);

    qemu_free_timer(d->poll_timer);

}

{

}

/* PCI interface */

static void pcnet_mmio_map(PCIDevice *pci_dev, int region_num,

                            uint32_t addr, uint32_t size, int type)

{

#ifdef PCNET_DEBUG_IO

    printf("pcnet_mmio_map addr=0x%08x 0x%08x\n", addr, size);

#endif

}

static void pci_physical_memory_write(void *dma_opaque, target_phys_addr_t addr,

static int pci_pcnet_uninit(PCIDevice *dev)

{

    return 0;

}

{

    uint8_t *pci_conf;

#if 0

        sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));

#endif

    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_AMD);

    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_AMD_LANCE);

    pci_conf[0x3f] = 0xff;

    /* Handler for memory-mapped I/O */

    pci_register_io_region((PCIDevice *)d, 0, PCNET_IOPORT_SIZE,

                           PCI_ADDRESS_SPACE_IO, pcnet_ioport_map);

    pci_register_io_region((PCIDevice *)d, 1, PCNET_PNPMMIO_SIZE,

                           PCI_ADDRESS_SPACE_MEM, pcnet_mmio_map);

}

/* SPARC32 interface */

    PCNetState *d = vc->opaque;

    pcnet_common_cleanup(d);

}

{

        cpu_register_io_memory(0, lance_mem_read, lance_mem_write, d);

}

#endif /* TARGET_SPARC */

   inherit from a particular bus (e.g. PCI or I2C) rather than

   this API directly.  */

#include "qdev.h"

#include "sysemu.h"

    prop->value.ptr = value;

}

qemu_irq qdev_get_irq_sink(DeviceState *dev, int n)

{

    dev->gpio_out[n] = pin;

}

static int next_block_unit[IF_COUNT];

/* Get a block device.  This should only be used for single-drive devices

    int num_gpio_in;

    qemu_irq *gpio_in;

    ChildBusList *child_bus;

};

/*** Board API.  This should go away once we have a machine config file.  ***/

/* Set properties between creation and init.  */

void qdev_set_prop_int(DeviceState *dev, const char *name, int value);

void qdev_set_prop_ptr(DeviceState *dev, const char *name, void *value);

qemu_irq qdev_get_irq_sink(DeviceState *dev, int n);

qemu_irq qdev_get_gpio_in(DeviceState *dev, int n);

    return 0;

}

{

    RTL8139State *s;

    uint8_t *pci_conf;

    d->dev.unregister = pci_rtl8139_uninit;

    pci_conf = d->dev.config;

                           PCI_ADDRESS_SPACE_MEM, rtl8139_mmio_map);

    s->pci_dev = (PCIDevice *)d;

    rtl8139_reset(s);

                                 rtl8139_receive, rtl8139_can_receive,

                                 rtl8139_cleanup, s);

    qemu_mod_timer(s->timer,

        rtl8139_get_next_tctr_time(s,qemu_get_clock(vm_clock)));

#endif /* RTL8139_ONBOARD_TIMER */

}

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#include "qemu-timer.h"

#include "sun4m.h"

#include "nvram.h"

    return kernel_size;

}

static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,

                          const char *boot_device,

                          const char *kernel_filename,

/* sparc32_dma.c */

#include "sparc32_dma.h"

/* eccmemctl.c */

void *ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version);

#define SMBD_COMMAND "/usr/sbin/smbd"

#endif

#endif