Revision 9d52e907 target-ppc/helper.c
b/target-ppc/helper.c | ||
---|---|---|
1200 | 1200 |
#if defined(TARGET_PPC64) |
1201 | 1201 |
case POWERPC_MMU_620: |
1202 | 1202 |
case POWERPC_MMU_64B: |
1203 |
case POWERPC_MMU_2_06: |
|
1203 | 1204 |
/* Real address are 60 bits long */ |
1204 | 1205 |
ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL; |
1205 | 1206 |
ctx->prot |= PAGE_WRITE; |
... | ... | |
1277 | 1278 |
#if defined(TARGET_PPC64) |
1278 | 1279 |
case POWERPC_MMU_620: |
1279 | 1280 |
case POWERPC_MMU_64B: |
1281 |
case POWERPC_MMU_2_06: |
|
1280 | 1282 |
#endif |
1281 | 1283 |
if (ret < 0) { |
1282 | 1284 |
/* We didn't match any BAT entry or don't have BATs */ |
... | ... | |
1376 | 1378 |
#if defined(TARGET_PPC64) |
1377 | 1379 |
case POWERPC_MMU_620: |
1378 | 1380 |
case POWERPC_MMU_64B: |
1381 |
case POWERPC_MMU_2_06: |
|
1379 | 1382 |
#endif |
1380 | 1383 |
env->exception_index = POWERPC_EXCP_ISI; |
1381 | 1384 |
env->error_code = 0x40000000; |
... | ... | |
1485 | 1488 |
#if defined(TARGET_PPC64) |
1486 | 1489 |
case POWERPC_MMU_620: |
1487 | 1490 |
case POWERPC_MMU_64B: |
1491 |
case POWERPC_MMU_2_06: |
|
1488 | 1492 |
#endif |
1489 | 1493 |
env->exception_index = POWERPC_EXCP_DSI; |
1490 | 1494 |
env->error_code = 0; |
... | ... | |
1808 | 1812 |
#if defined(TARGET_PPC64) |
1809 | 1813 |
case POWERPC_MMU_620: |
1810 | 1814 |
case POWERPC_MMU_64B: |
1815 |
case POWERPC_MMU_2_06: |
|
1811 | 1816 |
#endif /* defined(TARGET_PPC64) */ |
1812 | 1817 |
tlb_flush(env, 1); |
1813 | 1818 |
break; |
... | ... | |
1875 | 1880 |
#if defined(TARGET_PPC64) |
1876 | 1881 |
case POWERPC_MMU_620: |
1877 | 1882 |
case POWERPC_MMU_64B: |
1883 |
case POWERPC_MMU_2_06: |
|
1878 | 1884 |
/* tlbie invalidate TLBs for all segments */ |
1879 | 1885 |
/* XXX: given the fact that there are too many segments to invalidate, |
1880 | 1886 |
* and we still don't have a tlb_flush_mask(env, n, mask) in Qemu, |
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