Revision 9ee6e8bb hw/pl011.c
| b/hw/pl011.c | ||
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| 28 | 28 |
int read_trigger; |
| 29 | 29 |
CharDriverState *chr; |
| 30 | 30 |
qemu_irq irq; |
| 31 |
enum pl011_type type; |
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| 31 | 32 |
} pl011_state; |
| 32 | 33 |
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| 33 | 34 |
#define PL011_INT_TX 0x20 |
| ... | ... | |
| 38 | 39 |
#define PL011_FLAG_TXFF 0x20 |
| 39 | 40 |
#define PL011_FLAG_RXFE 0x10 |
| 40 | 41 |
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static const unsigned char pl011_id[] = |
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| 42 |
{ 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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static const unsigned char pl011_id[2][8] = {
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{ 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }, /* PL011_ARM */
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{ 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }, /* PL011_LUMINARY */
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}; |
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| 43 | 46 |
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| 44 | 47 |
static void pl011_update(pl011_state *s) |
| 45 | 48 |
{
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| ... | ... | |
| 56 | 59 |
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| 57 | 60 |
offset -= s->base; |
| 58 | 61 |
if (offset >= 0xfe0 && offset < 0x1000) {
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return pl011_id[(offset - 0xfe0) >> 2]; |
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return pl011_id[s->type][(offset - 0xfe0) >> 2];
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| 60 | 63 |
} |
| 61 | 64 |
switch (offset >> 2) {
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| 62 | 65 |
case 0: /* UARTDR */ |
| ... | ... | |
| 137 | 140 |
case 1: /* UARTCR */ |
| 138 | 141 |
s->cr = value; |
| 139 | 142 |
break; |
| 143 |
case 6: /* UARTFR */ |
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/* Writes to Flag register are ignored. */ |
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break; |
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| 140 | 146 |
case 8: /* UARTUARTILPR */ |
| 141 | 147 |
s->ilpr = value; |
| 142 | 148 |
break; |
| ... | ... | |
| 224 | 230 |
}; |
| 225 | 231 |
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| 226 | 232 |
void pl011_init(uint32_t base, qemu_irq irq, |
| 227 |
CharDriverState *chr) |
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CharDriverState *chr, enum pl011_type type)
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{
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int iomemtype; |
| 230 | 236 |
pl011_state *s; |
| ... | ... | |
| 235 | 241 |
cpu_register_physical_memory(base, 0x00001000, iomemtype); |
| 236 | 242 |
s->base = base; |
| 237 | 243 |
s->irq = irq; |
| 244 |
s->type = type; |
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| 238 | 245 |
s->chr = chr; |
| 239 | 246 |
s->read_trigger = 1; |
| 240 | 247 |
s->ifl = 0x12; |
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