Revision 9ee6e8bb hw/pxa2xx.c
| b/hw/pxa2xx.c | ||
|---|---|---|
| 297 | 297 |
ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; |
| 298 | 298 |
s->env->cp15.c1_sys = 0; |
| 299 | 299 |
s->env->cp15.c1_coproc = 0; |
| 300 |
s->env->cp15.c2_base = 0; |
|
| 300 |
s->env->cp15.c2_base0 = 0;
|
|
| 301 | 301 |
s->env->cp15.c3 = 0; |
| 302 | 302 |
s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ |
| 303 | 303 |
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ |
| ... | ... | |
| 2031 | 2031 |
fprintf(stderr, "Unable to find CPU definition\n"); |
| 2032 | 2032 |
exit(1); |
| 2033 | 2033 |
} |
| 2034 |
register_savevm("cpu", 0, 0, cpu_save, cpu_load, s->env);
|
|
| 2034 |
register_savevm("cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load,
|
|
| 2035 |
s->env); |
|
| 2035 | 2036 |
|
| 2036 | 2037 |
/* SDRAM & Internal Memory Storage */ |
| 2037 | 2038 |
cpu_register_physical_memory(PXA2XX_SDRAM_BASE, |
| ... | ... | |
| 2145 | 2146 |
fprintf(stderr, "Unable to find CPU definition\n"); |
| 2146 | 2147 |
exit(1); |
| 2147 | 2148 |
} |
| 2148 |
register_savevm("cpu", 0, 0, cpu_save, cpu_load, s->env);
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|
| 2149 |
register_savevm("cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load,
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|
| 2150 |
s->env); |
|
| 2149 | 2151 |
|
| 2150 | 2152 |
/* SDRAM & Internal Memory Storage */ |
| 2151 | 2153 |
cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size, |
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