Revision 9ee6e8bb hw/realview.c
b/hw/realview.c | ||
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25 | 25 |
NICInfo *nd; |
26 | 26 |
int n; |
27 | 27 |
int done_smc = 0; |
28 |
qemu_irq cpu_irq[4]; |
|
29 |
int ncpu; |
|
28 | 30 |
|
29 | 31 |
if (!cpu_model) |
30 | 32 |
cpu_model = "arm926"; |
31 |
env = cpu_init(cpu_model); |
|
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if (!env) { |
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fprintf(stderr, "Unable to find CPU definition\n"); |
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exit(1); |
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/* FIXME: obey smp_cpus. */ |
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if (strcmp(cpu_model, "arm11mpcore") == 0) { |
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ncpu = 4; |
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} else { |
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ncpu = 1; |
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} |
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39 |
|
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for (n = 0; n < ncpu; n++) { |
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env = cpu_init(cpu_model); |
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if (!env) { |
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fprintf(stderr, "Unable to find CPU definition\n"); |
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exit(1); |
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} |
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pic = arm_pic_init_cpu(env); |
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cpu_irq[n] = pic[ARM_PIC_CPU_IRQ]; |
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if (n > 0) { |
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/* Set entry point for secondary CPUs. This assumes we're using |
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the init code from arm_boot.c. Real hardware resets all CPUs |
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the same. */ |
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env->regs[15] = 0x80000000; |
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} |
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35 | 54 |
} |
36 | 55 |
|
37 | 56 |
/* ??? RAM shoud repeat to fill physical memory space. */ |
... | ... | |
39 | 58 |
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); |
40 | 59 |
|
41 | 60 |
arm_sysctl_init(0x10000000, 0xc1400400); |
42 |
pic = arm_pic_init_cpu(env); |
|
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/* ??? The documentation says GIC1 is nFIQ and either GIC2 or GIC3 |
|
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is nIRQ (there are inconsistencies). However Linux 2.6.17 expects |
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GIC1 to be nIRQ and ignores all the others, so do that for now. */ |
|
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pic = arm_gic_init(0x10040000, pic[ARM_PIC_CPU_IRQ]); |
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|
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if (ncpu == 1) { |
|
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/* ??? The documentation says GIC1 is nFIQ and either GIC2 or GIC3 |
|
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is nIRQ (there are inconsistencies). However Linux 2.6.17 expects |
|
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GIC1 to be nIRQ and ignores all the others, so do that for now. */ |
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pic = realview_gic_init(0x10040000, cpu_irq[0]); |
|
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} else { |
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pic = mpcore_irq_init(cpu_irq); |
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} |
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|
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47 | 71 |
pl050_init(0x10006000, pic[20], 0); |
48 | 72 |
pl050_init(0x10007000, pic[21], 1); |
49 | 73 |
|
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pl011_init(0x10009000, pic[12], serial_hds[0]); |
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pl011_init(0x1000a000, pic[13], serial_hds[1]); |
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pl011_init(0x1000b000, pic[14], serial_hds[2]); |
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pl011_init(0x1000c000, pic[15], serial_hds[3]); |
|
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pl011_init(0x10009000, pic[12], serial_hds[0], PL011_ARM);
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pl011_init(0x1000a000, pic[13], serial_hds[1], PL011_ARM);
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pl011_init(0x1000b000, pic[14], serial_hds[2], PL011_ARM);
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pl011_init(0x1000c000, pic[15], serial_hds[3], PL011_ARM);
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54 | 78 |
|
55 | 79 |
/* DMA controller is optional, apparently. */ |
56 | 80 |
pl080_init(0x10030000, pic[24], 2); |
... | ... | |
114 | 138 |
/* 0x10019000 PCI controller config. */ |
115 | 139 |
/* 0x10020000 CLCD. */ |
116 | 140 |
/* 0x10030000 DMA Controller. */ |
117 |
/* 0x10040000 GIC1 (FIQ1). */
|
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/* 0x10050000 GIC2 (IRQ1). */
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/* 0x10060000 GIC3 (FIQ2). */
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/* 0x10070000 GIC4 (IRQ2). */
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/* 0x10040000 GIC1. */ |
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/* 0x10050000 GIC2. */ |
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/* 0x10060000 GIC3. */
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/* 0x10070000 GIC4. */
|
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121 | 145 |
/* 0x10080000 SMC. */ |
122 | 146 |
/* 0x40000000 NOR flash. */ |
123 | 147 |
/* 0x44000000 DoC flash. */ |
... | ... | |
137 | 161 |
/* 0x68000000 PCI mem 1. */ |
138 | 162 |
/* 0x6c000000 PCI mem 2. */ |
139 | 163 |
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arm_load_kernel(env, ram_size, kernel_filename, kernel_cmdline,
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arm_load_kernel(first_cpu, ram_size, kernel_filename, kernel_cmdline,
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141 | 165 |
initrd_filename, 0x33b, 0x0); |
166 |
|
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/* ??? Hack to map an additional page of ram for the secondary CPU |
|
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startup code. I guess this works on real hardware because the |
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BootROM happens to be in ROM/flash or in memory that isn't clobbered |
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until after Linux boots the secondary CPUs. */ |
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cpu_register_physical_memory(0x80000000, 0x1000, IO_MEM_RAM + ram_size); |
|
142 | 172 |
} |
143 | 173 |
|
144 | 174 |
QEMUMachine realview_machine = { |
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