Revision 9ee6e8bb vl.c
| b/vl.c | ||
|---|---|---|
| 6126 | 6126 |
qemu_put_be32(f, env->cp15.c1_sys); |
| 6127 | 6127 |
qemu_put_be32(f, env->cp15.c1_coproc); |
| 6128 | 6128 |
qemu_put_be32(f, env->cp15.c1_xscaleauxcr); |
| 6129 |
qemu_put_be32(f, env->cp15.c2_base); |
|
| 6129 |
qemu_put_be32(f, env->cp15.c2_base0); |
|
| 6130 |
qemu_put_be32(f, env->cp15.c2_base1); |
|
| 6131 |
qemu_put_be32(f, env->cp15.c2_mask); |
|
| 6130 | 6132 |
qemu_put_be32(f, env->cp15.c2_data); |
| 6131 | 6133 |
qemu_put_be32(f, env->cp15.c2_insn); |
| 6132 | 6134 |
qemu_put_be32(f, env->cp15.c3); |
| ... | ... | |
| 6141 | 6143 |
qemu_put_be32(f, env->cp15.c9_data); |
| 6142 | 6144 |
qemu_put_be32(f, env->cp15.c13_fcse); |
| 6143 | 6145 |
qemu_put_be32(f, env->cp15.c13_context); |
| 6146 |
qemu_put_be32(f, env->cp15.c13_tls1); |
|
| 6147 |
qemu_put_be32(f, env->cp15.c13_tls2); |
|
| 6148 |
qemu_put_be32(f, env->cp15.c13_tls3); |
|
| 6144 | 6149 |
qemu_put_be32(f, env->cp15.c15_cpar); |
| 6145 | 6150 |
|
| 6146 | 6151 |
qemu_put_be32(f, env->features); |
| ... | ... | |
| 6159 | 6164 |
/* TODO: Should use proper FPSCR access functions. */ |
| 6160 | 6165 |
qemu_put_be32(f, env->vfp.vec_len); |
| 6161 | 6166 |
qemu_put_be32(f, env->vfp.vec_stride); |
| 6167 |
|
|
| 6168 |
if (arm_feature(env, ARM_FEATURE_VFP3)) {
|
|
| 6169 |
for (i = 16; i < 32; i++) {
|
|
| 6170 |
CPU_DoubleU u; |
|
| 6171 |
u.d = env->vfp.regs[i]; |
|
| 6172 |
qemu_put_be32(f, u.l.upper); |
|
| 6173 |
qemu_put_be32(f, u.l.lower); |
|
| 6174 |
} |
|
| 6175 |
} |
|
| 6162 | 6176 |
} |
| 6163 | 6177 |
|
| 6164 | 6178 |
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
|
| ... | ... | |
| 6169 | 6183 |
qemu_put_be32(f, env->iwmmxt.cregs[i]); |
| 6170 | 6184 |
} |
| 6171 | 6185 |
} |
| 6186 |
|
|
| 6187 |
if (arm_feature(env, ARM_FEATURE_M)) {
|
|
| 6188 |
qemu_put_be32(f, env->v7m.other_sp); |
|
| 6189 |
qemu_put_be32(f, env->v7m.vecbase); |
|
| 6190 |
qemu_put_be32(f, env->v7m.basepri); |
|
| 6191 |
qemu_put_be32(f, env->v7m.control); |
|
| 6192 |
qemu_put_be32(f, env->v7m.current_sp); |
|
| 6193 |
qemu_put_be32(f, env->v7m.exception); |
|
| 6194 |
} |
|
| 6172 | 6195 |
} |
| 6173 | 6196 |
|
| 6174 | 6197 |
int cpu_load(QEMUFile *f, void *opaque, int version_id) |
| ... | ... | |
| 6176 | 6199 |
CPUARMState *env = (CPUARMState *)opaque; |
| 6177 | 6200 |
int i; |
| 6178 | 6201 |
|
| 6179 |
if (version_id != 0)
|
|
| 6202 |
if (version_id != ARM_CPU_SAVE_VERSION)
|
|
| 6180 | 6203 |
return -EINVAL; |
| 6181 | 6204 |
|
| 6182 | 6205 |
for (i = 0; i < 16; i++) {
|
| ... | ... | |
| 6198 | 6221 |
env->cp15.c1_sys = qemu_get_be32(f); |
| 6199 | 6222 |
env->cp15.c1_coproc = qemu_get_be32(f); |
| 6200 | 6223 |
env->cp15.c1_xscaleauxcr = qemu_get_be32(f); |
| 6201 |
env->cp15.c2_base = qemu_get_be32(f); |
|
| 6224 |
env->cp15.c2_base0 = qemu_get_be32(f); |
|
| 6225 |
env->cp15.c2_base1 = qemu_get_be32(f); |
|
| 6226 |
env->cp15.c2_mask = qemu_get_be32(f); |
|
| 6202 | 6227 |
env->cp15.c2_data = qemu_get_be32(f); |
| 6203 | 6228 |
env->cp15.c2_insn = qemu_get_be32(f); |
| 6204 | 6229 |
env->cp15.c3 = qemu_get_be32(f); |
| ... | ... | |
| 6213 | 6238 |
env->cp15.c9_data = qemu_get_be32(f); |
| 6214 | 6239 |
env->cp15.c13_fcse = qemu_get_be32(f); |
| 6215 | 6240 |
env->cp15.c13_context = qemu_get_be32(f); |
| 6241 |
env->cp15.c13_tls1 = qemu_get_be32(f); |
|
| 6242 |
env->cp15.c13_tls2 = qemu_get_be32(f); |
|
| 6243 |
env->cp15.c13_tls3 = qemu_get_be32(f); |
|
| 6216 | 6244 |
env->cp15.c15_cpar = qemu_get_be32(f); |
| 6217 | 6245 |
|
| 6218 | 6246 |
env->features = qemu_get_be32(f); |
| ... | ... | |
| 6231 | 6259 |
/* TODO: Should use proper FPSCR access functions. */ |
| 6232 | 6260 |
env->vfp.vec_len = qemu_get_be32(f); |
| 6233 | 6261 |
env->vfp.vec_stride = qemu_get_be32(f); |
| 6262 |
|
|
| 6263 |
if (arm_feature(env, ARM_FEATURE_VFP3)) {
|
|
| 6264 |
for (i = 0; i < 16; i++) {
|
|
| 6265 |
CPU_DoubleU u; |
|
| 6266 |
u.l.upper = qemu_get_be32(f); |
|
| 6267 |
u.l.lower = qemu_get_be32(f); |
|
| 6268 |
env->vfp.regs[i] = u.d; |
|
| 6269 |
} |
|
| 6270 |
} |
|
| 6234 | 6271 |
} |
| 6235 | 6272 |
|
| 6236 | 6273 |
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
|
| ... | ... | |
| 6242 | 6279 |
} |
| 6243 | 6280 |
} |
| 6244 | 6281 |
|
| 6282 |
if (arm_feature(env, ARM_FEATURE_M)) {
|
|
| 6283 |
env->v7m.other_sp = qemu_get_be32(f); |
|
| 6284 |
env->v7m.vecbase = qemu_get_be32(f); |
|
| 6285 |
env->v7m.basepri = qemu_get_be32(f); |
|
| 6286 |
env->v7m.control = qemu_get_be32(f); |
|
| 6287 |
env->v7m.current_sp = qemu_get_be32(f); |
|
| 6288 |
env->v7m.exception = qemu_get_be32(f); |
|
| 6289 |
} |
|
| 6290 |
|
|
| 6245 | 6291 |
return 0; |
| 6246 | 6292 |
} |
| 6247 | 6293 |
|
| ... | ... | |
| 7392 | 7438 |
qemu_register_machine(&borzoipda_machine); |
| 7393 | 7439 |
qemu_register_machine(&terrierpda_machine); |
| 7394 | 7440 |
qemu_register_machine(&palmte_machine); |
| 7441 |
qemu_register_machine(&lm3s811evb_machine); |
|
| 7442 |
qemu_register_machine(&lm3s6965evb_machine); |
|
| 7395 | 7443 |
#elif defined(TARGET_SH4) |
| 7396 | 7444 |
qemu_register_machine(&shix_machine); |
| 7397 | 7445 |
qemu_register_machine(&r2d_machine); |
Also available in: Unified diff