Revision 9f6f0423 hw/pci_host.c
| b/hw/pci_host.c | ||
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| 79 | 79 |
return val; |
| 80 | 80 |
} |
| 81 | 81 |
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static void pci_host_config_writel(void *opaque, target_phys_addr_t addr,
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| 83 |
uint32_t val)
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static void pci_host_config_write(ReadWriteHandler *handler,
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pcibus_t addr, uint32_t val, int len)
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| 84 | 84 |
{
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PCIHostState *s = opaque;
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PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
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| 86 | 86 |
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PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",
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__func__, addr, len, val); |
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| 87 | 89 |
#ifdef TARGET_WORDS_BIGENDIAN |
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val = bswap32(val);
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val = qemu_bswap_len(val, len);
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| 89 | 91 |
#endif |
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PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
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__func__, addr, val); |
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| 92 | 92 |
s->config_reg = val; |
| 93 | 93 |
} |
| 94 | 94 |
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static uint32_t pci_host_config_readl(void *opaque, target_phys_addr_t addr) |
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static uint32_t pci_host_config_read(ReadWriteHandler *handler, |
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pcibus_t addr, int len) |
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| 96 | 97 |
{
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PCIHostState *s = opaque;
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PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
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| 98 | 99 |
uint32_t val = s->config_reg; |
| 99 |
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| 100 | 100 |
#ifdef TARGET_WORDS_BIGENDIAN |
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val = bswap32(val);
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val = qemu_bswap_len(val, len);
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| 102 | 102 |
#endif |
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PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
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__func__, addr, val); |
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PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",
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__func__, addr, len, val);
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| 105 | 105 |
return val; |
| 106 | 106 |
} |
| 107 | 107 |
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static CPUWriteMemoryFunc * const pci_host_config_write[] = {
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&pci_host_config_writel, |
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&pci_host_config_writel, |
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&pci_host_config_writel, |
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}; |
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static CPUReadMemoryFunc * const pci_host_config_read[] = {
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&pci_host_config_readl, |
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&pci_host_config_readl, |
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&pci_host_config_readl, |
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}; |
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int pci_host_conf_register_mmio(PCIHostState *s) |
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{
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return cpu_register_io_memory(pci_host_config_read, |
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pci_host_config_write, s); |
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} |
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static void pci_host_config_writel_noswap(void *opaque, |
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target_phys_addr_t addr, |
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uint32_t val) |
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static void pci_host_config_write_noswap(ReadWriteHandler *handler, |
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pcibus_t addr, uint32_t val, int len) |
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{
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PCIHostState *s = opaque;
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PCIHostState *s = container_of(handler, PCIHostState, conf_noswap_handler);
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PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
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__func__, addr, val); |
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PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",
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__func__, addr, len, val);
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| 134 | 115 |
s->config_reg = val; |
| 135 | 116 |
} |
| 136 | 117 |
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static uint32_t pci_host_config_readl_noswap(void *opaque,
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target_phys_addr_t addr)
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static uint32_t pci_host_config_read_noswap(ReadWriteHandler *handler,
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pcibus_t addr, int len)
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{
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PCIHostState *s = opaque;
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PCIHostState *s = container_of(handler, PCIHostState, conf_noswap_handler);
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uint32_t val = s->config_reg; |
| 142 | 123 |
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PCI_DPRINTF("%s addr " TARGET_FMT_plx " val %"PRIx32"\n",
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__func__, addr, val); |
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PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",
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__func__, addr, len, val);
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| 145 | 126 |
return val; |
| 146 | 127 |
} |
| 147 | 128 |
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static CPUWriteMemoryFunc * const pci_host_config_write_noswap[] = {
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&pci_host_config_writel_noswap, |
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&pci_host_config_writel_noswap, |
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&pci_host_config_writel_noswap, |
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}; |
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static CPUReadMemoryFunc * const pci_host_config_read_noswap[] = {
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&pci_host_config_readl_noswap, |
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&pci_host_config_readl_noswap, |
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&pci_host_config_readl_noswap, |
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}; |
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int pci_host_conf_register_mmio_noswap(PCIHostState *s) |
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static void pci_host_data_write(ReadWriteHandler *handler, |
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pcibus_t addr, uint32_t val, int len) |
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{
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return cpu_register_io_memory(pci_host_config_read_noswap, |
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pci_host_config_write_noswap, s); |
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PCIHostState *s = container_of(handler, PCIHostState, data_handler); |
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#ifdef TARGET_WORDS_BIGENDIAN |
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val = qemu_bswap_len(val, len); |
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#endif |
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PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n",
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addr, len, val); |
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if (s->config_reg & (1u << 31)) |
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pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); |
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| 164 | 140 |
} |
| 165 | 141 |
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static void pci_host_config_writel_ioport(void *opaque,
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uint32_t addr, uint32_t val)
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static uint32_t pci_host_data_read(ReadWriteHandler *handler,
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pcibus_t addr, int len)
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{
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PCIHostState *s = opaque; |
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PCIHostState *s = container_of(handler, PCIHostState, data_handler); |
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uint32_t val; |
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if (!(s->config_reg & (1 << 31))) |
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return 0xffffffff; |
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val = pci_data_read(s->bus, s->config_reg | (addr & 3), len); |
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PCI_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n",
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addr, len, val); |
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#ifdef TARGET_WORDS_BIGENDIAN |
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val = qemu_bswap_len(val, len); |
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#endif |
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return val; |
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} |
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PCI_DPRINTF("%s addr %"PRIx32 " val %"PRIx32"\n", __func__, addr, val);
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s->config_reg = val; |
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static void pci_host_init(PCIHostState *s) |
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{
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s->conf_handler.write = pci_host_config_write; |
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s->conf_handler.read = pci_host_config_read; |
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s->conf_noswap_handler.write = pci_host_config_write_noswap; |
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s->conf_noswap_handler.read = pci_host_config_read_noswap; |
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s->data_handler.write = pci_host_data_write; |
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s->data_handler.read = pci_host_data_read; |
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} |
| 174 | 167 |
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static uint32_t pci_host_config_readl_ioport(void *opaque, uint32_t addr)
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int pci_host_conf_register_mmio(PCIHostState *s)
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{
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PCIHostState *s = opaque; |
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uint32_t val = s->config_reg; |
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pci_host_init(s); |
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return cpu_register_io_memory_simple(&s->conf_handler); |
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} |
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PCI_DPRINTF("%s addr %"PRIx32" val %"PRIx32"\n", __func__, addr, val);
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return val; |
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int pci_host_conf_register_mmio_noswap(PCIHostState *s) |
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{
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pci_host_init(s); |
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return cpu_register_io_memory_simple(&s->conf_noswap_handler); |
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| 182 | 178 |
} |
| 183 | 179 |
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| 184 | 180 |
void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s) |
| 185 | 181 |
{
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register_ioport_write(ioport, 4, 4, pci_host_config_writel_ioport, s);
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register_ioport_read(ioport, 4, 4, pci_host_config_readl_ioport, s);
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pci_host_init(s);
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register_ioport_simple(&s->conf_noswap_handler, ioport, 4, 4);
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| 188 | 184 |
} |
| 189 | 185 |
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#define PCI_ADDR_T target_phys_addr_t |
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#define PCI_HOST_SUFFIX _mmio |
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#include "pci_host_template.h" |
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static CPUWriteMemoryFunc * const pci_host_data_write_mmio[] = {
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pci_host_data_writeb_mmio, |
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pci_host_data_writew_mmio, |
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pci_host_data_writel_mmio, |
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}; |
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static CPUReadMemoryFunc * const pci_host_data_read_mmio[] = {
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pci_host_data_readb_mmio, |
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pci_host_data_readw_mmio, |
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pci_host_data_readl_mmio, |
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}; |
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int pci_host_data_register_mmio(PCIHostState *s) |
| 208 | 187 |
{
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return cpu_register_io_memory(pci_host_data_read_mmio, |
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pci_host_data_write_mmio, |
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s); |
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pci_host_init(s); |
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return cpu_register_io_memory_simple(&s->data_handler); |
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| 212 | 190 |
} |
| 213 | 191 |
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#undef PCI_ADDR_T |
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#undef PCI_HOST_SUFFIX |
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#define PCI_ADDR_T uint32_t |
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#define PCI_HOST_SUFFIX _ioport |
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#include "pci_host_template.h" |
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void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s) |
| 223 | 193 |
{
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register_ioport_write(ioport, 4, 1, pci_host_data_writeb_ioport, s); |
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register_ioport_write(ioport, 4, 2, pci_host_data_writew_ioport, s); |
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register_ioport_write(ioport, 4, 4, pci_host_data_writel_ioport, s); |
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register_ioport_read(ioport, 4, 1, pci_host_data_readb_ioport, s); |
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register_ioport_read(ioport, 4, 2, pci_host_data_readw_ioport, s); |
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register_ioport_read(ioport, 4, 4, pci_host_data_readl_ioport, s); |
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pci_host_init(s); |
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register_ioport_simple(&s->data_handler, ioport, 4, 1); |
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register_ioport_simple(&s->data_handler, ioport, 4, 2); |
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register_ioport_simple(&s->data_handler, ioport, 4, 4); |
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| 230 | 198 |
} |
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