Statistics
| Branch: | Revision:

root / target-mips / fop_template.c @ 9f77c1cd

History | View | Annotate | Download (4.6 kB)

1 6ea83fed bellard
/*
2 5fafdf24 ths
 * MIPS emulation micro-operations templates for floating point reg
3 6ea83fed bellard
 * load & store for qemu.
4 5fafdf24 ths
 *
5 6ea83fed bellard
 * Copyright (c) 2006 Marius Groeger
6 6ea83fed bellard
 *
7 6ea83fed bellard
 * This library is free software; you can redistribute it and/or
8 6ea83fed bellard
 * modify it under the terms of the GNU Lesser General Public
9 6ea83fed bellard
 * License as published by the Free Software Foundation; either
10 6ea83fed bellard
 * version 2 of the License, or (at your option) any later version.
11 6ea83fed bellard
 *
12 6ea83fed bellard
 * This library is distributed in the hope that it will be useful,
13 6ea83fed bellard
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 6ea83fed bellard
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15 6ea83fed bellard
 * Lesser General Public License for more details.
16 6ea83fed bellard
 *
17 6ea83fed bellard
 * You should have received a copy of the GNU Lesser General Public
18 6ea83fed bellard
 * License along with this library; if not, write to the Free Software
19 6ea83fed bellard
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20 6ea83fed bellard
 */
21 6ea83fed bellard
22 5a5012ec ths
#if defined(FREG)
23 6ea83fed bellard
24 5a5012ec ths
#define OP_WLOAD_FREG(treg, tregname, FREG)              \
25 5a5012ec ths
    void glue(glue(op_load_fpr_,tregname), FREG) (void)  \
26 5a5012ec ths
    {                                                    \
27 ead9360e ths
        treg = env->fpu->fpr[FREG].fs[FP_ENDIAN_IDX];    \
28 5a5012ec ths
        RETURN();                                        \
29 6ea83fed bellard
    }
30 6ea83fed bellard
31 5a5012ec ths
#define OP_WSTORE_FREG(treg, tregname, FREG)             \
32 5a5012ec ths
    void glue(glue(op_store_fpr_,tregname), FREG) (void) \
33 5a5012ec ths
    {                                                    \
34 ead9360e ths
        env->fpu->fpr[FREG].fs[FP_ENDIAN_IDX] = treg;    \
35 5a5012ec ths
        RETURN();                                        \
36 6ea83fed bellard
    }
37 6ea83fed bellard
38 5a5012ec ths
/* WT0 = FREG.w: op_load_fpr_WT0_fprFREG */
39 5a5012ec ths
OP_WLOAD_FREG(WT0, WT0_fpr, FREG)
40 5a5012ec ths
/* FREG.w = WT0: op_store_fpr_WT0_fprFREG */
41 5a5012ec ths
OP_WSTORE_FREG(WT0, WT0_fpr, FREG)
42 5a5012ec ths
43 5a5012ec ths
OP_WLOAD_FREG(WT1, WT1_fpr, FREG)
44 5a5012ec ths
OP_WSTORE_FREG(WT1, WT1_fpr, FREG)
45 5a5012ec ths
46 5a5012ec ths
OP_WLOAD_FREG(WT2, WT2_fpr, FREG)
47 5a5012ec ths
OP_WSTORE_FREG(WT2, WT2_fpr, FREG)
48 5a5012ec ths
49 5a5012ec ths
#define OP_DLOAD_FREG(treg, tregname, FREG)              \
50 5a5012ec ths
    void glue(glue(op_load_fpr_,tregname), FREG) (void)  \
51 5a5012ec ths
    {                                                    \
52 5e755519 ths
        if (env->hflags & MIPS_HFLAG_F64)                \
53 ead9360e ths
            treg = env->fpu->fpr[FREG].fd;               \
54 5a5012ec ths
        else                                             \
55 ead9360e ths
            treg = (uint64_t)(env->fpu->fpr[FREG | 1].fs[FP_ENDIAN_IDX]) << 32 | \
56 ead9360e ths
                   env->fpu->fpr[FREG & ~1].fs[FP_ENDIAN_IDX]; \
57 5a5012ec ths
        RETURN();                                        \
58 5a5012ec ths
    }
59 6ea83fed bellard
60 5a5012ec ths
#define OP_DSTORE_FREG(treg, tregname, FREG)             \
61 5a5012ec ths
    void glue(glue(op_store_fpr_,tregname), FREG) (void) \
62 5a5012ec ths
    {                                                    \
63 5e755519 ths
        if (env->hflags & MIPS_HFLAG_F64)                \
64 ead9360e ths
            env->fpu->fpr[FREG].fd = treg;               \
65 5a5012ec ths
        else {                                           \
66 ead9360e ths
            env->fpu->fpr[FREG | 1].fs[FP_ENDIAN_IDX] = treg >> 32; \
67 ead9360e ths
            env->fpu->fpr[FREG & ~1].fs[FP_ENDIAN_IDX] = treg;      \
68 5a5012ec ths
        }                                                \
69 5a5012ec ths
        RETURN();                                        \
70 5a5012ec ths
    }
71 6ea83fed bellard
72 5a5012ec ths
OP_DLOAD_FREG(DT0, DT0_fpr, FREG)
73 5a5012ec ths
OP_DSTORE_FREG(DT0, DT0_fpr, FREG)
74 6ea83fed bellard
75 5a5012ec ths
OP_DLOAD_FREG(DT1, DT1_fpr, FREG)
76 5a5012ec ths
OP_DSTORE_FREG(DT1, DT1_fpr, FREG)
77 6ea83fed bellard
78 5a5012ec ths
OP_DLOAD_FREG(DT2, DT2_fpr, FREG)
79 5a5012ec ths
OP_DSTORE_FREG(DT2, DT2_fpr, FREG)
80 6ea83fed bellard
81 5a5012ec ths
#define OP_PSLOAD_FREG(treg, tregname, FREG)             \
82 5a5012ec ths
    void glue(glue(op_load_fpr_,tregname), FREG) (void)  \
83 5a5012ec ths
    {                                                    \
84 ead9360e ths
        treg = env->fpu->fpr[FREG].fs[!FP_ENDIAN_IDX];   \
85 5a5012ec ths
        RETURN();                                        \
86 6ea83fed bellard
    }
87 6ea83fed bellard
88 5a5012ec ths
#define OP_PSSTORE_FREG(treg, tregname, FREG)            \
89 5a5012ec ths
    void glue(glue(op_store_fpr_,tregname), FREG) (void) \
90 5a5012ec ths
    {                                                    \
91 ead9360e ths
        env->fpu->fpr[FREG].fs[!FP_ENDIAN_IDX] = treg;   \
92 5a5012ec ths
        RETURN();                                        \
93 6ea83fed bellard
    }
94 6ea83fed bellard
95 5a5012ec ths
OP_PSLOAD_FREG(WTH0, WTH0_fpr, FREG)
96 5a5012ec ths
OP_PSSTORE_FREG(WTH0, WTH0_fpr, FREG)
97 6ea83fed bellard
98 5a5012ec ths
OP_PSLOAD_FREG(WTH1, WTH1_fpr, FREG)
99 5a5012ec ths
OP_PSSTORE_FREG(WTH1, WTH1_fpr, FREG)
100 6ea83fed bellard
101 5a5012ec ths
OP_PSLOAD_FREG(WTH2, WTH2_fpr, FREG)
102 5a5012ec ths
OP_PSSTORE_FREG(WTH2, WTH2_fpr, FREG)
103 6ea83fed bellard
104 6ea83fed bellard
#endif
105 6ea83fed bellard
106 6ea83fed bellard
#if defined (FTN)
107 6ea83fed bellard
108 5a5012ec ths
#define SET_RESET(treg, tregname)        \
109 6ea83fed bellard
    void glue(op_set, tregname)(void)    \
110 5a5012ec ths
    {                                    \
111 5a5012ec ths
        treg = PARAM1;                   \
112 5a5012ec ths
        RETURN();                        \
113 5a5012ec ths
    }                                    \
114 6ea83fed bellard
    void glue(op_reset, tregname)(void)  \
115 5a5012ec ths
    {                                    \
116 5a5012ec ths
        treg = 0;                        \
117 5a5012ec ths
        RETURN();                        \
118 5a5012ec ths
    }
119 6ea83fed bellard
120 6ea83fed bellard
SET_RESET(WT0, _WT0)
121 6ea83fed bellard
SET_RESET(WT1, _WT1)
122 6ea83fed bellard
SET_RESET(WT2, _WT2)
123 6ea83fed bellard
SET_RESET(DT0, _DT0)
124 6ea83fed bellard
SET_RESET(DT1, _DT1)
125 6ea83fed bellard
SET_RESET(DT2, _DT2)
126 5a5012ec ths
SET_RESET(WTH0, _WTH0)
127 5a5012ec ths
SET_RESET(WTH1, _WTH1)
128 5a5012ec ths
SET_RESET(WTH2, _WTH2)
129 6ea83fed bellard
130 c570fd16 ths
#undef SET_RESET
131 6ea83fed bellard
#endif