Revision 9fd1ae3a

b/target-sparc/cpu.h
556 556
#elif !defined(TARGET_SPARC64)
557 557
    return env1->psrs;
558 558
#else
559
    if (cpu_hypervisor_mode(env1)) {
559
    if (env1->tl > 0) {
560
        return MMU_NUCLEUS_IDX;
561
    } else if (cpu_hypervisor_mode(env1)) {
560 562
        return MMU_HYPV_IDX;
561 563
    } else if (cpu_supervisor_mode(env1)) {
562 564
        return MMU_KERNEL_IDX;
......
636 638
    *cs_base = env->npc;
637 639
#ifdef TARGET_SPARC64
638 640
    // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
639
    *flags = ((env->pstate & PS_AM) << 2)
640
        | (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
641
        | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
641
    *flags = ((env->pstate & PS_AM) << 2)          /* 5 */
642
        | (((env->pstate & PS_PEF) >> 1)           /* 3 */
643
        | ((env->fprs & FPRS_FEF) << 2))           /* 4 */
644
        | (env->pstate & PS_PRIV)                  /* 2 */
645
        | ((env->lsu & (DMMU_E | IMMU_E)) >> 2)    /* 1, 0 */
646
        | ((env->tl & 0xff) << 8)
647
        | (env->dmmu.mmu_primary_context << 16);   /* 16... */
642 648
#else
643 649
    // FPU enable . Supervisor
644 650
    *flags = (env->psref << 4) | env->psrs;
b/target-sparc/helper.c
572 572
    /* ??? We treat everything as a small page, then explicitly flush
573 573
       everything when an entry is evicted.  */
574 574
    *page_size = TARGET_PAGE_SIZE;
575

  
576
#if defined (DEBUG_MMU)
577
    /* safety net to catch wrong softmmu index use from dynamic code */
578
    if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) {
579
        DPRINTF_MMU("get_physical_address %s tl=%d mmu_idx=%d"
580
                    " primary context=%" PRIx64
581
                    " secondary context=%" PRIx64
582
                " address=%" PRIx64
583
                "\n",
584
                (rw == 2 ? "CODE" : "DATA"),
585
                env->tl, mmu_idx,
586
                env->dmmu.mmu_primary_context,
587
                env->dmmu.mmu_secondary_context,
588
                address);
589
    }
590
#endif
591

  
575 592
    if (rw == 2)
576 593
        return get_physical_address_code(env, physical, prot, address,
577 594
                                         mmu_idx);
......
718 735

  
719 736
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
720 737
{
721
    return cpu_get_phys_page_nofault(env, addr, MMU_KERNEL_IDX);
738
    return cpu_get_phys_page_nofault(env, addr, cpu_mmu_index(env));
722 739
}
723 740
#endif
724 741

  
b/target-sparc/translate.c
3484 3484
                            case 6: // pstate
3485 3485
                                save_state(dc, cpu_cond);
3486 3486
                                gen_helper_wrpstate(cpu_tmp0);
3487
                                gen_op_next_insn();
3488
                                tcg_gen_exit_tb(0);
3489
                                dc->is_br = 1;
3487
                                dc->npc = DYNAMIC_PC;
3490 3488
                                break;
3491 3489
                            case 7: // tl
3490
                                save_state(dc, cpu_cond);
3492 3491
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3493 3492
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3494 3493
                                               offsetof(CPUSPARCState, tl));
3494
                                dc->npc = DYNAMIC_PC;
3495 3495
                                break;
3496 3496
                            case 8: // pil
3497 3497
                                gen_helper_wrpil(cpu_tmp0);
......
4550 4550
#endif
4551 4551
                    save_state(dc, cpu_cond);
4552 4552
                    gen_st_asi(cpu_val, cpu_addr, insn, 4);
4553
                    dc->npc = DYNAMIC_PC;
4553 4554
                    break;
4554 4555
                case 0x15: /* stba, store byte alternate */
4555 4556
#ifndef TARGET_SPARC64
......
4560 4561
#endif
4561 4562
                    save_state(dc, cpu_cond);
4562 4563
                    gen_st_asi(cpu_val, cpu_addr, insn, 1);
4564
                    dc->npc = DYNAMIC_PC;
4563 4565
                    break;
4564 4566
                case 0x16: /* stha, store halfword alternate */
4565 4567
#ifndef TARGET_SPARC64
......
4570 4572
#endif
4571 4573
                    save_state(dc, cpu_cond);
4572 4574
                    gen_st_asi(cpu_val, cpu_addr, insn, 2);
4575
                    dc->npc = DYNAMIC_PC;
4573 4576
                    break;
4574 4577
                case 0x17: /* stda, store double word alternate */
4575 4578
#ifndef TARGET_SPARC64
......
4594 4597
                case 0x1e: /* V9 stxa */
4595 4598
                    save_state(dc, cpu_cond);
4596 4599
                    gen_st_asi(cpu_val, cpu_addr, insn, 8);
4600
                    dc->npc = DYNAMIC_PC;
4597 4601
                    break;
4598 4602
#endif
4599 4603
                default:

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