Revision 9fd1ae3a target-sparc/cpu.h

b/target-sparc/cpu.h
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#elif !defined(TARGET_SPARC64)
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    return env1->psrs;
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#else
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    if (cpu_hypervisor_mode(env1)) {
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    if (env1->tl > 0) {
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        return MMU_NUCLEUS_IDX;
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    } else if (cpu_hypervisor_mode(env1)) {
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        return MMU_HYPV_IDX;
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    } else if (cpu_supervisor_mode(env1)) {
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        return MMU_KERNEL_IDX;
......
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    *cs_base = env->npc;
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#ifdef TARGET_SPARC64
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    // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
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    *flags = ((env->pstate & PS_AM) << 2)
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        | (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
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        | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
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    *flags = ((env->pstate & PS_AM) << 2)          /* 5 */
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        | (((env->pstate & PS_PEF) >> 1)           /* 3 */
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        | ((env->fprs & FPRS_FEF) << 2))           /* 4 */
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        | (env->pstate & PS_PRIV)                  /* 2 */
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        | ((env->lsu & (DMMU_E | IMMU_E)) >> 2)    /* 1, 0 */
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        | ((env->tl & 0xff) << 8)
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        | (env->dmmu.mmu_primary_context << 16);   /* 16... */
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#else
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    // FPU enable . Supervisor
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    *flags = (env->psref << 4) | env->psrs;

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