Revision 9fdf0c29

b/Makefile.target
231 231
obj-ppc-y += ppc_oldworld.o
232 232
# NewWorld PowerMac
233 233
obj-ppc-y += ppc_newworld.o
234
# IBM pSeries (sPAPR)i
235
ifeq ($(CONFIG_FDT)$(TARGET_PPC64),yy)
236
obj-ppc-y += spapr.o spapr_hcall.o
237
endif
234 238
# PowerPC 4xx boards
235 239
obj-ppc-y += ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o
236 240
obj-ppc-y += ppc440.o ppc440_bamboo.o
b/hw/spapr.c
1
/*
2
 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3
 *
4
 * Copyright (c) 2004-2007 Fabrice Bellard
5
 * Copyright (c) 2007 Jocelyn Mayer
6
 * Copyright (c) 2010 David Gibson, IBM Corporation.
7
 *
8
 * Permission is hereby granted, free of charge, to any person obtaining a copy
9
 * of this software and associated documentation files (the "Software"), to deal
10
 * in the Software without restriction, including without limitation the rights
11
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12
 * copies of the Software, and to permit persons to whom the Software is
13
 * furnished to do so, subject to the following conditions:
14
 *
15
 * The above copyright notice and this permission notice shall be included in
16
 * all copies or substantial portions of the Software.
17
 *
18
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24
 * THE SOFTWARE.
25
 *
26
 */
27
#include "sysemu.h"
28
#include "qemu-char.h"
29
#include "hw.h"
30
#include "elf.h"
31

  
32
#include "hw/boards.h"
33
#include "hw/ppc.h"
34
#include "hw/loader.h"
35

  
36
#include "hw/spapr.h"
37

  
38
#include <libfdt.h>
39

  
40
#define KERNEL_LOAD_ADDR        0x00000000
41
#define INITRD_LOAD_ADDR        0x02800000
42
#define FDT_MAX_SIZE            0x10000
43

  
44
#define TIMEBASE_FREQ           512000000ULL
45

  
46
#define MAX_CPUS                32
47

  
48
sPAPREnvironment *spapr;
49

  
50
static void *spapr_create_fdt(int *fdt_size, ram_addr_t ramsize,
51
                              const char *cpu_model, CPUState *envs[],
52
                              sPAPREnvironment *spapr,
53
                              target_phys_addr_t initrd_base,
54
                              target_phys_addr_t initrd_size,
55
                              const char *kernel_cmdline)
56
{
57
    void *fdt;
58
    uint64_t mem_reg_property[] = { 0, cpu_to_be64(ramsize) };
59
    uint32_t start_prop = cpu_to_be32(initrd_base);
60
    uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
61
    int i;
62
    char *modelname;
63

  
64
#define _FDT(exp) \
65
    do { \
66
        int ret = (exp);                                           \
67
        if (ret < 0) {                                             \
68
            fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
69
                    #exp, fdt_strerror(ret));                      \
70
            exit(1);                                               \
71
        }                                                          \
72
    } while (0)
73

  
74
    fdt = qemu_mallocz(FDT_MAX_SIZE);
75
    _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
76

  
77
    _FDT((fdt_finish_reservemap(fdt)));
78

  
79
    /* Root node */
80
    _FDT((fdt_begin_node(fdt, "")));
81
    _FDT((fdt_property_string(fdt, "device_type", "chrp")));
82
    _FDT((fdt_property_string(fdt, "model", "qemu,emulated-pSeries-LPAR")));
83

  
84
    _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
85
    _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
86

  
87
    /* /chosen */
88
    _FDT((fdt_begin_node(fdt, "chosen")));
89

  
90
    _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
91
    _FDT((fdt_property(fdt, "linux,initrd-start",
92
                       &start_prop, sizeof(start_prop))));
93
    _FDT((fdt_property(fdt, "linux,initrd-end",
94
                       &end_prop, sizeof(end_prop))));
95

  
96
    _FDT((fdt_end_node(fdt)));
97

  
98
    /* memory node */
99
    _FDT((fdt_begin_node(fdt, "memory@0")));
100

  
101
    _FDT((fdt_property_string(fdt, "device_type", "memory")));
102
    _FDT((fdt_property(fdt, "reg",
103
                       mem_reg_property, sizeof(mem_reg_property))));
104

  
105
    _FDT((fdt_end_node(fdt)));
106

  
107
    /* cpus */
108
    _FDT((fdt_begin_node(fdt, "cpus")));
109

  
110
    _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
111
    _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
112

  
113
    modelname = qemu_strdup(cpu_model);
114

  
115
    for (i = 0; i < strlen(modelname); i++) {
116
        modelname[i] = toupper(modelname[i]);
117
    }
118

  
119
    for (i = 0; i < smp_cpus; i++) {
120
        CPUState *env = envs[i];
121
        char *nodename;
122
        uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
123
                           0xffffffff, 0xffffffff};
124

  
125
        if (asprintf(&nodename, "%s@%x", modelname, i) < 0) {
126
            fprintf(stderr, "Allocation failure\n");
127
            exit(1);
128
        }
129

  
130
        _FDT((fdt_begin_node(fdt, nodename)));
131

  
132
        free(nodename);
133

  
134
        _FDT((fdt_property_cell(fdt, "reg", i)));
135
        _FDT((fdt_property_string(fdt, "device_type", "cpu")));
136

  
137
        _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
138
        _FDT((fdt_property_cell(fdt, "dcache-block-size",
139
                                env->dcache_line_size)));
140
        _FDT((fdt_property_cell(fdt, "icache-block-size",
141
                                env->icache_line_size)));
142
        _FDT((fdt_property_cell(fdt, "timebase-frequency", TIMEBASE_FREQ)));
143
        /* Hardcode CPU frequency for now.  It's kind of arbitrary on
144
         * full emu, for kvm we should copy it from the host */
145
        _FDT((fdt_property_cell(fdt, "clock-frequency", 1000000000)));
146
        _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
147
        _FDT((fdt_property_string(fdt, "status", "okay")));
148
        _FDT((fdt_property(fdt, "64-bit", NULL, 0)));
149

  
150
        if (envs[i]->mmu_model & POWERPC_MMU_1TSEG) {
151
            _FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
152
                               segs, sizeof(segs))));
153
        }
154

  
155
        _FDT((fdt_end_node(fdt)));
156
    }
157

  
158
    qemu_free(modelname);
159

  
160
    _FDT((fdt_end_node(fdt)));
161

  
162
    _FDT((fdt_end_node(fdt))); /* close root node */
163
    _FDT((fdt_finish(fdt)));
164

  
165
    *fdt_size = fdt_totalsize(fdt);
166

  
167
    return fdt;
168
}
169

  
170
static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
171
{
172
    return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
173
}
174

  
175
static void emulate_spapr_hypercall(CPUState *env)
176
{
177
    env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]);
178
}
179

  
180
/* FIXME: hack until we implement the proper VIO console */
181
static target_ulong h_put_term_char(CPUState *env, sPAPREnvironment *spapr,
182
                                    target_ulong opcode, target_ulong *args)
183
{
184
    uint8_t buf[16];
185

  
186
    stq_p(buf, args[2]);
187
    stq_p(buf + 8, args[3]);
188

  
189
    qemu_chr_write(serial_hds[0], buf, args[1]);
190

  
191
    return 0;
192
}
193

  
194

  
195
/* pSeries LPAR / sPAPR hardware init */
196
static void ppc_spapr_init(ram_addr_t ram_size,
197
                           const char *boot_device,
198
                           const char *kernel_filename,
199
                           const char *kernel_cmdline,
200
                           const char *initrd_filename,
201
                           const char *cpu_model)
202
{
203
    CPUState *envs[MAX_CPUS];
204
    void *fdt;
205
    int i;
206
    ram_addr_t ram_offset;
207
    target_phys_addr_t fdt_addr;
208
    uint32_t kernel_base, initrd_base;
209
    long kernel_size, initrd_size;
210
    int fdt_size;
211

  
212
    spapr = qemu_malloc(sizeof(*spapr));
213
    cpu_ppc_hypercall = emulate_spapr_hypercall;
214

  
215
    /* We place the device tree just below either the top of RAM, or
216
     * 2GB, so that it can be processed with 32-bit code if
217
     * necessary */
218
    fdt_addr = MIN(ram_size, 0x80000000) - FDT_MAX_SIZE;
219

  
220
    /* init CPUs */
221
    if (cpu_model == NULL) {
222
        cpu_model = "POWER7";
223
    }
224
    for (i = 0; i < smp_cpus; i++) {
225
        CPUState *env = cpu_init(cpu_model);
226

  
227
        if (!env) {
228
            fprintf(stderr, "Unable to find PowerPC CPU definition\n");
229
            exit(1);
230
        }
231
        /* Set time-base frequency to 512 MHz */
232
        cpu_ppc_tb_init(env, TIMEBASE_FREQ);
233
        qemu_register_reset((QEMUResetHandler *)&cpu_reset, env);
234

  
235
        env->hreset_vector = 0x60;
236
        env->hreset_excp_prefix = 0;
237
        env->gpr[3] = i;
238

  
239
        envs[i] = env;
240
    }
241

  
242
    /* allocate RAM */
243
    ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", ram_size);
244
    cpu_register_physical_memory(0, ram_size, ram_offset);
245

  
246
    spapr_register_hypercall(H_PUT_TERM_CHAR, h_put_term_char);
247

  
248
    if (kernel_filename) {
249
        uint64_t lowaddr = 0;
250

  
251
        kernel_base = KERNEL_LOAD_ADDR;
252

  
253
        kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
254
                               NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
255
        if (kernel_size < 0) {
256
            kernel_size = load_image_targphys(kernel_filename, kernel_base,
257
                                              ram_size - kernel_base);
258
        }
259
        if (kernel_size < 0) {
260
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
261
                    kernel_filename);
262
            exit(1);
263
        }
264

  
265
        /* load initrd */
266
        if (initrd_filename) {
267
            initrd_base = INITRD_LOAD_ADDR;
268
            initrd_size = load_image_targphys(initrd_filename, initrd_base,
269
                                              ram_size - initrd_base);
270
            if (initrd_size < 0) {
271
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
272
                        initrd_filename);
273
                exit(1);
274
            }
275
        } else {
276
            initrd_base = 0;
277
            initrd_size = 0;
278
        }
279

  
280
    } else {
281
        fprintf(stderr, "pSeries machine needs -kernel for now");
282
        exit(1);
283
    }
284

  
285
    /* Prepare the device tree */
286
    fdt = spapr_create_fdt(&fdt_size, ram_size, cpu_model, envs, spapr,
287
                           initrd_base, initrd_size, kernel_cmdline);
288
    assert(fdt != NULL);
289

  
290
    cpu_physical_memory_write(fdt_addr, fdt, fdt_size);
291

  
292
    qemu_free(fdt);
293

  
294
    envs[0]->gpr[3] = fdt_addr;
295
    envs[0]->gpr[5] = 0;
296
    envs[0]->hreset_vector = kernel_base;
297
}
298

  
299
static QEMUMachine spapr_machine = {
300
    .name = "pseries",
301
    .desc = "pSeries Logical Partition (PAPR compliant)",
302
    .init = ppc_spapr_init,
303
    .max_cpus = MAX_CPUS,
304
    .no_vga = 1,
305
    .no_parallel = 1,
306
};
307

  
308
static void spapr_machine_init(void)
309
{
310
    qemu_register_machine(&spapr_machine);
311
}
312

  
313
machine_init(spapr_machine_init);
b/hw/spapr.h
1
#if !defined(__HW_SPAPR_H__)
2
#define __HW_SPAPR_H__
3

  
4
typedef struct sPAPREnvironment {
5
} sPAPREnvironment;
6

  
7
#define H_SUCCESS         0
8
#define H_BUSY            1        /* Hardware busy -- retry later */
9
#define H_CLOSED          2        /* Resource closed */
10
#define H_NOT_AVAILABLE   3
11
#define H_CONSTRAINED     4        /* Resource request constrained to max allowed */
12
#define H_PARTIAL         5
13
#define H_IN_PROGRESS     14       /* Kind of like busy */
14
#define H_PAGE_REGISTERED 15
15
#define H_PARTIAL_STORE   16
16
#define H_PENDING         17       /* returned from H_POLL_PENDING */
17
#define H_CONTINUE        18       /* Returned from H_Join on success */
18
#define H_LONG_BUSY_START_RANGE         9900  /* Start of long busy range */
19
#define H_LONG_BUSY_ORDER_1_MSEC        9900  /* Long busy, hint that 1msec \
20
                                                 is a good time to retry */
21
#define H_LONG_BUSY_ORDER_10_MSEC       9901  /* Long busy, hint that 10msec \
22
                                                 is a good time to retry */
23
#define H_LONG_BUSY_ORDER_100_MSEC      9902  /* Long busy, hint that 100msec \
24
                                                 is a good time to retry */
25
#define H_LONG_BUSY_ORDER_1_SEC         9903  /* Long busy, hint that 1sec \
26
                                                 is a good time to retry */
27
#define H_LONG_BUSY_ORDER_10_SEC        9904  /* Long busy, hint that 10sec \
28
                                                 is a good time to retry */
29
#define H_LONG_BUSY_ORDER_100_SEC       9905  /* Long busy, hint that 100sec \
30
                                                 is a good time to retry */
31
#define H_LONG_BUSY_END_RANGE           9905  /* End of long busy range */
32
#define H_HARDWARE        -1       /* Hardware error */
33
#define H_FUNCTION        -2       /* Function not supported */
34
#define H_PRIVILEGE       -3       /* Caller not privileged */
35
#define H_PARAMETER       -4       /* Parameter invalid, out-of-range or conflicting */
36
#define H_BAD_MODE        -5       /* Illegal msr value */
37
#define H_PTEG_FULL       -6       /* PTEG is full */
38
#define H_NOT_FOUND       -7       /* PTE was not found" */
39
#define H_RESERVED_DABR   -8       /* DABR address is reserved by the hypervisor on this processor" */
40
#define H_NO_MEM          -9
41
#define H_AUTHORITY       -10
42
#define H_PERMISSION      -11
43
#define H_DROPPED         -12
44
#define H_SOURCE_PARM     -13
45
#define H_DEST_PARM       -14
46
#define H_REMOTE_PARM     -15
47
#define H_RESOURCE        -16
48
#define H_ADAPTER_PARM    -17
49
#define H_RH_PARM         -18
50
#define H_RCQ_PARM        -19
51
#define H_SCQ_PARM        -20
52
#define H_EQ_PARM         -21
53
#define H_RT_PARM         -22
54
#define H_ST_PARM         -23
55
#define H_SIGT_PARM       -24
56
#define H_TOKEN_PARM      -25
57
#define H_MLENGTH_PARM    -27
58
#define H_MEM_PARM        -28
59
#define H_MEM_ACCESS_PARM -29
60
#define H_ATTR_PARM       -30
61
#define H_PORT_PARM       -31
62
#define H_MCG_PARM        -32
63
#define H_VL_PARM         -33
64
#define H_TSIZE_PARM      -34
65
#define H_TRACE_PARM      -35
66

  
67
#define H_MASK_PARM       -37
68
#define H_MCG_FULL        -38
69
#define H_ALIAS_EXIST     -39
70
#define H_P_COUNTER       -40
71
#define H_TABLE_FULL      -41
72
#define H_ALT_TABLE       -42
73
#define H_MR_CONDITION    -43
74
#define H_NOT_ENOUGH_RESOURCES -44
75
#define H_R_STATE         -45
76
#define H_RESCINDEND      -46
77
#define H_MULTI_THREADS_ACTIVE -9005
78

  
79

  
80
/* Long Busy is a condition that can be returned by the firmware
81
 * when a call cannot be completed now, but the identical call
82
 * should be retried later.  This prevents calls blocking in the
83
 * firmware for long periods of time.  Annoyingly the firmware can return
84
 * a range of return codes, hinting at how long we should wait before
85
 * retrying.  If you don't care for the hint, the macro below is a good
86
 * way to check for the long_busy return codes
87
 */
88
#define H_IS_LONG_BUSY(x)  ((x >= H_LONG_BUSY_START_RANGE) \
89
                            && (x <= H_LONG_BUSY_END_RANGE))
90

  
91
/* Flags */
92
#define H_LARGE_PAGE      (1ULL<<(63-16))
93
#define H_EXACT           (1ULL<<(63-24))       /* Use exact PTE or return H_PTEG_FULL */
94
#define H_R_XLATE         (1ULL<<(63-25))       /* include a valid logical page num in the pte if the valid bit is set */
95
#define H_READ_4          (1ULL<<(63-26))       /* Return 4 PTEs */
96
#define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
97
#define H_PAGE_UNUSED     ((1ULL<<(63-29)) | (1ULL<<(63-30)))
98
#define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
99
#define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
100
#define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
101
#define H_AVPN            (1ULL<<(63-32))       /* An avpn is provided as a sanity test */
102
#define H_ANDCOND         (1ULL<<(63-33))
103
#define H_ICACHE_INVALIDATE (1ULL<<(63-40))     /* icbi, etc.  (ignored for IO pages) */
104
#define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))    /* dcbst, icbi, etc (ignored for IO pages */
105
#define H_ZERO_PAGE       (1ULL<<(63-48))       /* zero the page before mapping (ignored for IO pages) */
106
#define H_COPY_PAGE       (1ULL<<(63-49))
107
#define H_N               (1ULL<<(63-61))
108
#define H_PP1             (1ULL<<(63-62))
109
#define H_PP2             (1ULL<<(63-63))
110

  
111
/* VASI States */
112
#define H_VASI_INVALID    0
113
#define H_VASI_ENABLED    1
114
#define H_VASI_ABORTED    2
115
#define H_VASI_SUSPENDING 3
116
#define H_VASI_SUSPENDED  4
117
#define H_VASI_RESUMED    5
118
#define H_VASI_COMPLETED  6
119

  
120
/* DABRX flags */
121
#define H_DABRX_HYPERVISOR (1ULL<<(63-61))
122
#define H_DABRX_KERNEL     (1ULL<<(63-62))
123
#define H_DABRX_USER       (1ULL<<(63-63))
124

  
125
/* Each control block has to be on a 4K bondary */
126
#define H_CB_ALIGNMENT     4096
127

  
128
/* pSeries hypervisor opcodes */
129
#define H_REMOVE                0x04
130
#define H_ENTER                 0x08
131
#define H_READ                  0x0c
132
#define H_CLEAR_MOD             0x10
133
#define H_CLEAR_REF             0x14
134
#define H_PROTECT               0x18
135
#define H_GET_TCE               0x1c
136
#define H_PUT_TCE               0x20
137
#define H_SET_SPRG0             0x24
138
#define H_SET_DABR              0x28
139
#define H_PAGE_INIT             0x2c
140
#define H_SET_ASR               0x30
141
#define H_ASR_ON                0x34
142
#define H_ASR_OFF               0x38
143
#define H_LOGICAL_CI_LOAD       0x3c
144
#define H_LOGICAL_CI_STORE      0x40
145
#define H_LOGICAL_CACHE_LOAD    0x44
146
#define H_LOGICAL_CACHE_STORE   0x48
147
#define H_LOGICAL_ICBI          0x4c
148
#define H_LOGICAL_DCBF          0x50
149
#define H_GET_TERM_CHAR         0x54
150
#define H_PUT_TERM_CHAR         0x58
151
#define H_REAL_TO_LOGICAL       0x5c
152
#define H_HYPERVISOR_DATA       0x60
153
#define H_EOI                   0x64
154
#define H_CPPR                  0x68
155
#define H_IPI                   0x6c
156
#define H_IPOLL                 0x70
157
#define H_XIRR                  0x74
158
#define H_PERFMON               0x7c
159
#define H_MIGRATE_DMA           0x78
160
#define H_REGISTER_VPA          0xDC
161
#define H_CEDE                  0xE0
162
#define H_CONFER                0xE4
163
#define H_PROD                  0xE8
164
#define H_GET_PPP               0xEC
165
#define H_SET_PPP               0xF0
166
#define H_PURR                  0xF4
167
#define H_PIC                   0xF8
168
#define H_REG_CRQ               0xFC
169
#define H_FREE_CRQ              0x100
170
#define H_VIO_SIGNAL            0x104
171
#define H_SEND_CRQ              0x108
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#define H_COPY_RDMA             0x110
173
#define H_REGISTER_LOGICAL_LAN  0x114
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#define H_FREE_LOGICAL_LAN      0x118
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#define H_ADD_LOGICAL_LAN_BUFFER 0x11C
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#define H_SEND_LOGICAL_LAN      0x120
177
#define H_BULK_REMOVE           0x124
178
#define H_MULTICAST_CTRL        0x130
179
#define H_SET_XDABR             0x134
180
#define H_STUFF_TCE             0x138
181
#define H_PUT_TCE_INDIRECT      0x13C
182
#define H_CHANGE_LOGICAL_LAN_MAC 0x14C
183
#define H_VTERM_PARTNER_INFO    0x150
184
#define H_REGISTER_VTERM        0x154
185
#define H_FREE_VTERM            0x158
186
#define H_RESET_EVENTS          0x15C
187
#define H_ALLOC_RESOURCE        0x160
188
#define H_FREE_RESOURCE         0x164
189
#define H_MODIFY_QP             0x168
190
#define H_QUERY_QP              0x16C
191
#define H_REREGISTER_PMR        0x170
192
#define H_REGISTER_SMR          0x174
193
#define H_QUERY_MR              0x178
194
#define H_QUERY_MW              0x17C
195
#define H_QUERY_HCA             0x180
196
#define H_QUERY_PORT            0x184
197
#define H_MODIFY_PORT           0x188
198
#define H_DEFINE_AQP1           0x18C
199
#define H_GET_TRACE_BUFFER      0x190
200
#define H_DEFINE_AQP0           0x194
201
#define H_RESIZE_MR             0x198
202
#define H_ATTACH_MCQP           0x19C
203
#define H_DETACH_MCQP           0x1A0
204
#define H_CREATE_RPT            0x1A4
205
#define H_REMOVE_RPT            0x1A8
206
#define H_REGISTER_RPAGES       0x1AC
207
#define H_DISABLE_AND_GETC      0x1B0
208
#define H_ERROR_DATA            0x1B4
209
#define H_GET_HCA_INFO          0x1B8
210
#define H_GET_PERF_COUNT        0x1BC
211
#define H_MANAGE_TRACE          0x1C0
212
#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
213
#define H_QUERY_INT_STATE       0x1E4
214
#define H_POLL_PENDING          0x1D8
215
#define H_ILLAN_ATTRIBUTES      0x244
216
#define H_MODIFY_HEA_QP         0x250
217
#define H_QUERY_HEA_QP          0x254
218
#define H_QUERY_HEA             0x258
219
#define H_QUERY_HEA_PORT        0x25C
220
#define H_MODIFY_HEA_PORT       0x260
221
#define H_REG_BCMC              0x264
222
#define H_DEREG_BCMC            0x268
223
#define H_REGISTER_HEA_RPAGES   0x26C
224
#define H_DISABLE_AND_GET_HEA   0x270
225
#define H_GET_HEA_INFO          0x274
226
#define H_ALLOC_HEA_RESOURCE    0x278
227
#define H_ADD_CONN              0x284
228
#define H_DEL_CONN              0x288
229
#define H_JOIN                  0x298
230
#define H_VASI_STATE            0x2A4
231
#define H_ENABLE_CRQ            0x2B0
232
#define H_GET_EM_PARMS          0x2B8
233
#define H_SET_MPP               0x2D0
234
#define H_GET_MPP               0x2D4
235
#define MAX_HCALL_OPCODE        H_GET_MPP
236

  
237
extern sPAPREnvironment *spapr;
238

  
239
/*#define DEBUG_SPAPR_HCALLS*/
240

  
241
#ifdef DEBUG_SPAPR_HCALLS
242
#define hcall_dprintf(fmt, ...) \
243
    do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
244
#else
245
#define hcall_dprintf(fmt, ...) \
246
    do { } while (0)
247
#endif
248

  
249
typedef target_ulong (*spapr_hcall_fn)(CPUState *env, sPAPREnvironment *spapr,
250
                                       target_ulong opcode,
251
                                       target_ulong *args);
252

  
253
void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
254
target_ulong spapr_hypercall(CPUState *env, target_ulong opcode,
255
                             target_ulong *args);
256

  
257
#endif /* !defined (__HW_SPAPR_H__) */
b/hw/spapr_hcall.c
1
#include "sysemu.h"
2
#include "cpu.h"
3
#include "qemu-char.h"
4
#include "hw/spapr.h"
5

  
6
spapr_hcall_fn hypercall_table[(MAX_HCALL_OPCODE / 4) + 1];
7

  
8
void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
9
{
10
    spapr_hcall_fn old_fn;
11

  
12
    assert(opcode <= MAX_HCALL_OPCODE);
13
    assert((opcode & 0x3) == 0);
14

  
15
    old_fn = hypercall_table[opcode / 4];
16

  
17
    assert(!old_fn || (fn == old_fn));
18

  
19
    hypercall_table[opcode / 4] = fn;
20
}
21

  
22
target_ulong spapr_hypercall(CPUState *env, target_ulong opcode,
23
                             target_ulong *args)
24
{
25
    if (msr_pr) {
26
        hcall_dprintf("Hypercall made with MSR[PR]=1\n");
27
        return H_PRIVILEGE;
28
    }
29

  
30
    if ((opcode <= MAX_HCALL_OPCODE)
31
        && ((opcode & 0x3) == 0)) {
32
        spapr_hcall_fn fn = hypercall_table[opcode / 4];
33

  
34
        if (fn) {
35
            return fn(env, spapr, opcode, args);
36
        }
37
    }
38

  
39
    hcall_dprintf("Unimplemented hcall 0x" TARGET_FMT_lx "\n", opcode);
40
    return H_FUNCTION;
41
}

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