Statistics
| Branch: | Revision:

root / target-ppc @ 9fdf0c29

Name Size
STATUS 10.6 kB
cpu.h 70.9 kB
exec.h 1.3 kB
helper.c 91.4 kB
helper.h 14.5 kB
helper_regs.h 3.3 kB
kvm.c 9.6 kB
kvm_ppc.c 2.6 kB
kvm_ppc.h 803 Bytes
machine.c 5.7 kB
mfrom_table.c 3.3 kB
mfrom_table_gen.c 652 Bytes
op_helper.c 127.2 kB
translate.c 340.6 kB
translate_init.c 420.1 kB

Latest revisions

# Date Author Comment
8500e3a9 04/01/2011 07:34 pm David Gibson

Clean up slb_lookup() function

The slb_lookup() function, used in the ppc translation path returns a
number of slb entry fields in reference parameters. However, only one
of the two callers of slb_lookup() actually wants this information.

This patch, therefore, makes slb_lookup() return a simple pointer to the...

bb593904 04/01/2011 07:34 pm David Gibson

Parse SDR1 on mtspr instead of at translate time

On ppc machines with hash table MMUs, the special purpose register SDR1
contains both the base address of the encoded size (hashed) page tables.

At present, we interpret the SDR1 value within the address translation...

fda6a0ec 04/01/2011 07:34 pm David Gibson

Use "hash" more consistently in ppc mmu code

Currently, get_segment() has a variable called hash. However it doesn't
(quite) get the hash value for the ppc hashed page table. Instead it
gets the hash shifted - effectively the offset of the hash bucket within...

256cebe5 04/01/2011 07:34 pm David Gibson

Better factor the ppc hash translation path

Currently the path handling hash page table translation in get_segment()
has a mix of common and 32 or 64 bit specific code. However the
division is not done terribly well which results in a lot of messy code
flipping between common and divided paths....

cdaee006 04/01/2011 07:34 pm David Gibson

Support 1T segments on ppc

Traditionally, the "segments" used for the two-stage translation used on
powerpc MMUs were 256MB in size. This was the only option on all hash
page table based 32-bit powerpc cpus, and on the earlier 64-bit hash page
table based cpus. However, newer 64-bit cpus also permit 1TB segments...

9d52e907 04/01/2011 07:34 pm David Gibson

Add POWER7 support for ppc

This adds emulation support for the recent POWER7 cpu to qemu. It's far
from perfect - it's missing a number of POWER7 features so far, including
any support for VSX or decimal floating point instructions. However, it's
close enough to boot a kernel with the POWER7 PVR....

d569956e 04/01/2011 07:34 pm David Gibson

Add a hook to allow hypercalls to be emulated on PowerPC

PowerPC and POWER chips since the POWER4 and 970 have a special
hypervisor mode, and a corresponding form of the system call
instruction which traps to the hypervisor.

qemu currently has stub implementations of hypervisor mode. That...

efdef95f 04/01/2011 07:34 pm David Gibson

Implement PowerPC slbmfee and slbmfev instructions

For a 64-bit PowerPC target, qemu correctly implements translation
through the segment lookaside buffer. Likewise it supports the
slbmte instruction which is used to load entries into the SLB.

However, it does not emulate the slbmfee and slbmfev instructions...

3a7f009a 04/01/2011 07:34 pm David Gibson

Implement missing parts of the logic for the POWER PURR

The PURR (Processor Utilization Resource Register) is a register found
on recent POWER CPUs. The guts of implementing it at least enough to
get by are already present in qemu, however some of the helper...

eaabeef2 04/01/2011 07:34 pm David Gibson

Correct ppc popcntb logic, implement popcntw and popcntd

qemu already includes support for the popcntb instruction introduced
in POWER5 (although it doesn't actually allow you to choose POWER5).

However, the logic is slightly incorrect: it will generate results...

View revisions

Also available in: Atom