root / hw / pxa2xx_lcd.c @ a07dec22
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/*
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* Intel XScale PXA255/270 LCDC emulation.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licensed under the GPLv2.
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*/
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#include "vl.h" |
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typedef void (*drawfn)(uint32_t *, uint8_t *, const uint8_t *, int, int); |
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struct pxa2xx_lcdc_s {
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target_phys_addr_t base; |
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qemu_irq irq; |
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int irqlevel;
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int invalidated;
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DisplayState *ds; |
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drawfn *line_fn[2];
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int dest_width;
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int xres, yres;
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int pal_for;
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int transp;
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enum {
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pxa_lcdc_2bpp = 1,
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pxa_lcdc_4bpp = 2,
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pxa_lcdc_8bpp = 3,
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pxa_lcdc_16bpp = 4,
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pxa_lcdc_18bpp = 5,
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pxa_lcdc_18pbpp = 6,
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pxa_lcdc_19bpp = 7,
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pxa_lcdc_19pbpp = 8,
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pxa_lcdc_24bpp = 9,
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pxa_lcdc_25bpp = 10,
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} bpp; |
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|
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uint32_t control[6];
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uint32_t status[2];
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uint32_t ovl1c[2];
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uint32_t ovl2c[2];
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uint32_t ccr; |
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uint32_t cmdcr; |
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uint32_t trgbr; |
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uint32_t tcr; |
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uint32_t liidr; |
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uint8_t bscntr; |
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struct {
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target_phys_addr_t branch; |
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int up;
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uint8_t palette[1024];
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uint8_t pbuffer[1024];
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void (*redraw)(struct pxa2xx_lcdc_s *s, uint8_t *fb, |
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int *miny, int *maxy); |
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target_phys_addr_t descriptor; |
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target_phys_addr_t source; |
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uint32_t id; |
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uint32_t command; |
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} dma_ch[7];
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void (*vsync_cb)(void *opaque); |
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void *opaque;
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int orientation;
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}; |
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struct __attribute__ ((__packed__)) pxa_frame_descriptor_s {
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uint32_t fdaddr; |
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uint32_t fsaddr; |
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uint32_t fidr; |
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uint32_t ldcmd; |
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}; |
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|
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#define LCCR0 0x000 /* LCD Controller Control register 0 */ |
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#define LCCR1 0x004 /* LCD Controller Control register 1 */ |
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#define LCCR2 0x008 /* LCD Controller Control register 2 */ |
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#define LCCR3 0x00c /* LCD Controller Control register 3 */ |
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#define LCCR4 0x010 /* LCD Controller Control register 4 */ |
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#define LCCR5 0x014 /* LCD Controller Control register 5 */ |
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|
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#define FBR0 0x020 /* DMA Channel 0 Frame Branch register */ |
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#define FBR1 0x024 /* DMA Channel 1 Frame Branch register */ |
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#define FBR2 0x028 /* DMA Channel 2 Frame Branch register */ |
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#define FBR3 0x02c /* DMA Channel 3 Frame Branch register */ |
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#define FBR4 0x030 /* DMA Channel 4 Frame Branch register */ |
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#define FBR5 0x110 /* DMA Channel 5 Frame Branch register */ |
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#define FBR6 0x114 /* DMA Channel 6 Frame Branch register */ |
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|
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#define LCSR1 0x034 /* LCD Controller Status register 1 */ |
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#define LCSR0 0x038 /* LCD Controller Status register 0 */ |
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#define LIIDR 0x03c /* LCD Controller Interrupt ID register */ |
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|
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#define TRGBR 0x040 /* TMED RGB Seed register */ |
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#define TCR 0x044 /* TMED Control register */ |
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#define OVL1C1 0x050 /* Overlay 1 Control register 1 */ |
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#define OVL1C2 0x060 /* Overlay 1 Control register 2 */ |
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#define OVL2C1 0x070 /* Overlay 2 Control register 1 */ |
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#define OVL2C2 0x080 /* Overlay 2 Control register 2 */ |
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#define CCR 0x090 /* Cursor Control register */ |
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#define CMDCR 0x100 /* Command Control register */ |
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#define PRSR 0x104 /* Panel Read Status register */ |
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#define PXA_LCDDMA_CHANS 7 |
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#define DMA_FDADR 0x00 /* Frame Descriptor Address register */ |
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#define DMA_FSADR 0x04 /* Frame Source Address register */ |
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#define DMA_FIDR 0x08 /* Frame ID register */ |
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#define DMA_LDCMD 0x0c /* Command register */ |
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/* LCD Buffer Strength Control register */
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#define BSCNTR 0x04000054 |
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|
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/* Bitfield masks */
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#define LCCR0_ENB (1 << 0) |
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#define LCCR0_CMS (1 << 1) |
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#define LCCR0_SDS (1 << 2) |
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#define LCCR0_LDM (1 << 3) |
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#define LCCR0_SOFM0 (1 << 4) |
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#define LCCR0_IUM (1 << 5) |
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#define LCCR0_EOFM0 (1 << 6) |
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#define LCCR0_PAS (1 << 7) |
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#define LCCR0_DPD (1 << 9) |
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#define LCCR0_DIS (1 << 10) |
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#define LCCR0_QDM (1 << 11) |
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#define LCCR0_PDD (0xff << 12) |
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#define LCCR0_BSM0 (1 << 20) |
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#define LCCR0_OUM (1 << 21) |
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#define LCCR0_LCDT (1 << 22) |
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#define LCCR0_RDSTM (1 << 23) |
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#define LCCR0_CMDIM (1 << 24) |
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#define LCCR0_OUC (1 << 25) |
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#define LCCR0_LDDALT (1 << 26) |
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#define LCCR1_PPL(x) ((x) & 0x3ff) |
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#define LCCR2_LPP(x) ((x) & 0x3ff) |
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#define LCCR3_API (15 << 16) |
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#define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8)) |
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#define LCCR3_PDFOR(x) (((x) >> 30) & 3) |
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#define LCCR4_K1(x) (((x) >> 0) & 7) |
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#define LCCR4_K2(x) (((x) >> 3) & 7) |
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#define LCCR4_K3(x) (((x) >> 6) & 7) |
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#define LCCR4_PALFOR(x) (((x) >> 15) & 3) |
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#define LCCR5_SOFM(ch) (1 << (ch - 1)) |
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#define LCCR5_EOFM(ch) (1 << (ch + 7)) |
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#define LCCR5_BSM(ch) (1 << (ch + 15)) |
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#define LCCR5_IUM(ch) (1 << (ch + 23)) |
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#define OVLC1_EN (1 << 31) |
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#define CCR_CEN (1 << 31) |
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#define FBR_BRA (1 << 0) |
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#define FBR_BINT (1 << 1) |
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#define FBR_SRCADDR (0xfffffff << 4) |
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#define LCSR0_LDD (1 << 0) |
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#define LCSR0_SOF0 (1 << 1) |
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#define LCSR0_BER (1 << 2) |
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#define LCSR0_ABC (1 << 3) |
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#define LCSR0_IU0 (1 << 4) |
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#define LCSR0_IU1 (1 << 5) |
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#define LCSR0_OU (1 << 6) |
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#define LCSR0_QD (1 << 7) |
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#define LCSR0_EOF0 (1 << 8) |
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#define LCSR0_BS0 (1 << 9) |
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#define LCSR0_SINT (1 << 10) |
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#define LCSR0_RDST (1 << 11) |
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#define LCSR0_CMDINT (1 << 12) |
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#define LCSR0_BERCH(x) (((x) & 7) << 28) |
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#define LCSR1_SOF(ch) (1 << (ch - 1)) |
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#define LCSR1_EOF(ch) (1 << (ch + 7)) |
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#define LCSR1_BS(ch) (1 << (ch + 15)) |
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#define LCSR1_IU(ch) (1 << (ch + 23)) |
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#define LDCMD_LENGTH(x) ((x) & 0x001ffffc) |
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#define LDCMD_EOFINT (1 << 21) |
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#define LDCMD_SOFINT (1 << 22) |
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#define LDCMD_PAL (1 << 26) |
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|
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/* Route internal interrupt lines to the global IC */
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static void pxa2xx_lcdc_int_update(struct pxa2xx_lcdc_s *s) |
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{
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int level = 0; |
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level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM); |
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level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0); |
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level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM); |
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level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1)); |
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level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM); |
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level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM); |
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level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0); |
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level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0); |
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level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM); |
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level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM); |
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level |= (s->status[1] & ~s->control[5]); |
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qemu_set_irq(s->irq, !!level); |
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s->irqlevel = level; |
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} |
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/* Set Branch Status interrupt high and poke associated registers */
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static inline void pxa2xx_dma_bs_set(struct pxa2xx_lcdc_s *s, int ch) |
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{
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int unmasked;
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if (ch == 0) { |
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s->status[0] |= LCSR0_BS0;
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unmasked = !(s->control[0] & LCCR0_BSM0);
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} else {
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s->status[1] |= LCSR1_BS(ch);
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unmasked = !(s->control[5] & LCCR5_BSM(ch));
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} |
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if (unmasked) {
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if (s->irqlevel)
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s->status[0] |= LCSR0_SINT;
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else
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s->liidr = s->dma_ch[ch].id; |
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} |
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} |
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/* Set Start Of Frame Status interrupt high and poke associated registers */
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static inline void pxa2xx_dma_sof_set(struct pxa2xx_lcdc_s *s, int ch) |
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{
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int unmasked;
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if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
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return;
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if (ch == 0) { |
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s->status[0] |= LCSR0_SOF0;
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unmasked = !(s->control[0] & LCCR0_SOFM0);
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} else {
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s->status[1] |= LCSR1_SOF(ch);
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unmasked = !(s->control[5] & LCCR5_SOFM(ch));
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} |
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if (unmasked) {
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if (s->irqlevel)
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s->status[0] |= LCSR0_SINT;
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else
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s->liidr = s->dma_ch[ch].id; |
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} |
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} |
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/* Set End Of Frame Status interrupt high and poke associated registers */
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static inline void pxa2xx_dma_eof_set(struct pxa2xx_lcdc_s *s, int ch) |
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{
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int unmasked;
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if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
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return;
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if (ch == 0) { |
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s->status[0] |= LCSR0_EOF0;
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unmasked = !(s->control[0] & LCCR0_EOFM0);
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} else {
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s->status[1] |= LCSR1_EOF(ch);
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unmasked = !(s->control[5] & LCCR5_EOFM(ch));
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} |
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if (unmasked) {
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if (s->irqlevel)
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s->status[0] |= LCSR0_SINT;
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else
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s->liidr = s->dma_ch[ch].id; |
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} |
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} |
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|
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/* Set Bus Error Status interrupt high and poke associated registers */
|
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static inline void pxa2xx_dma_ber_set(struct pxa2xx_lcdc_s *s, int ch) |
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{
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s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
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if (s->irqlevel)
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s->status[0] |= LCSR0_SINT;
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else
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s->liidr = s->dma_ch[ch].id; |
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} |
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|
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/* Set Read Status interrupt high and poke associated registers */
|
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static inline void pxa2xx_dma_rdst_set(struct pxa2xx_lcdc_s *s) |
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{
|
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s->status[0] |= LCSR0_RDST;
|
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if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM)) |
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s->status[0] |= LCSR0_SINT;
|
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} |
| 280 |
|
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/* Load new Frame Descriptors from DMA */
|
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static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s) |
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{
|
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struct pxa_frame_descriptor_s *desc[PXA_LCDDMA_CHANS];
|
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target_phys_addr_t descptr; |
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int i;
|
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|
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for (i = 0; i < PXA_LCDDMA_CHANS; i ++) { |
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desc[i] = 0;
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s->dma_ch[i].source = 0;
|
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|
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if (!s->dma_ch[i].up)
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continue;
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|
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if (s->dma_ch[i].branch & FBR_BRA) {
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descptr = s->dma_ch[i].branch & FBR_SRCADDR; |
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if (s->dma_ch[i].branch & FBR_BINT)
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pxa2xx_dma_bs_set(s, i); |
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s->dma_ch[i].branch &= ~FBR_BRA; |
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} else
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descptr = s->dma_ch[i].descriptor; |
| 302 |
|
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if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
|
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sizeof(*desc[i]) <= PXA2XX_SDRAM_BASE + phys_ram_size))
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continue;
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|
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descptr -= PXA2XX_SDRAM_BASE; |
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desc[i] = (struct pxa_frame_descriptor_s *) (phys_ram_base + descptr);
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s->dma_ch[i].descriptor = desc[i]->fdaddr; |
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s->dma_ch[i].source = desc[i]->fsaddr; |
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s->dma_ch[i].id = desc[i]->fidr; |
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s->dma_ch[i].command = desc[i]->ldcmd; |
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} |
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} |
| 315 |
|
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static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset) |
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{
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struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
| 319 |
int ch;
|
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offset -= s->base; |
| 321 |
|
| 322 |
switch (offset) {
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case LCCR0:
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return s->control[0]; |
| 325 |
case LCCR1:
|
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return s->control[1]; |
| 327 |
case LCCR2:
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return s->control[2]; |
| 329 |
case LCCR3:
|
| 330 |
return s->control[3]; |
| 331 |
case LCCR4:
|
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return s->control[4]; |
| 333 |
case LCCR5:
|
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return s->control[5]; |
| 335 |
|
| 336 |
case OVL1C1:
|
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return s->ovl1c[0]; |
| 338 |
case OVL1C2:
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return s->ovl1c[1]; |
| 340 |
case OVL2C1:
|
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return s->ovl2c[0]; |
| 342 |
case OVL2C2:
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return s->ovl2c[1]; |
| 344 |
|
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case CCR:
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return s->ccr;
|
| 347 |
|
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case CMDCR:
|
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return s->cmdcr;
|
| 350 |
|
| 351 |
case TRGBR:
|
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return s->trgbr;
|
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case TCR:
|
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return s->tcr;
|
| 355 |
|
| 356 |
case 0x200 ... 0x1000: /* DMA per-channel registers */ |
| 357 |
ch = (offset - 0x200) >> 4; |
| 358 |
if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS)) |
| 359 |
goto fail;
|
| 360 |
|
| 361 |
switch (offset & 0xf) { |
| 362 |
case DMA_FDADR:
|
| 363 |
return s->dma_ch[ch].descriptor;
|
| 364 |
case DMA_FSADR:
|
| 365 |
return s->dma_ch[ch].source;
|
| 366 |
case DMA_FIDR:
|
| 367 |
return s->dma_ch[ch].id;
|
| 368 |
case DMA_LDCMD:
|
| 369 |
return s->dma_ch[ch].command;
|
| 370 |
default:
|
| 371 |
goto fail;
|
| 372 |
} |
| 373 |
|
| 374 |
case FBR0:
|
| 375 |
return s->dma_ch[0].branch; |
| 376 |
case FBR1:
|
| 377 |
return s->dma_ch[1].branch; |
| 378 |
case FBR2:
|
| 379 |
return s->dma_ch[2].branch; |
| 380 |
case FBR3:
|
| 381 |
return s->dma_ch[3].branch; |
| 382 |
case FBR4:
|
| 383 |
return s->dma_ch[4].branch; |
| 384 |
case FBR5:
|
| 385 |
return s->dma_ch[5].branch; |
| 386 |
case FBR6:
|
| 387 |
return s->dma_ch[6].branch; |
| 388 |
|
| 389 |
case BSCNTR:
|
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return s->bscntr;
|
| 391 |
|
| 392 |
case PRSR:
|
| 393 |
return 0; |
| 394 |
|
| 395 |
case LCSR0:
|
| 396 |
return s->status[0]; |
| 397 |
case LCSR1:
|
| 398 |
return s->status[1]; |
| 399 |
case LIIDR:
|
| 400 |
return s->liidr;
|
| 401 |
|
| 402 |
default:
|
| 403 |
fail:
|
| 404 |
cpu_abort(cpu_single_env, |
| 405 |
"%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); |
| 406 |
} |
| 407 |
|
| 408 |
return 0; |
| 409 |
} |
| 410 |
|
| 411 |
static void pxa2xx_lcdc_write(void *opaque, |
| 412 |
target_phys_addr_t offset, uint32_t value) |
| 413 |
{
|
| 414 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
| 415 |
int ch;
|
| 416 |
offset -= s->base; |
| 417 |
|
| 418 |
switch (offset) {
|
| 419 |
case LCCR0:
|
| 420 |
/* ACK Quick Disable done */
|
| 421 |
if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB)) |
| 422 |
s->status[0] |= LCSR0_QD;
|
| 423 |
|
| 424 |
if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT)) |
| 425 |
printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
|
| 426 |
|
| 427 |
if ((s->control[3] & LCCR3_API) && |
| 428 |
(value & LCCR0_ENB) && !(value & LCCR0_LCDT)) |
| 429 |
s->status[0] |= LCSR0_ABC;
|
| 430 |
|
| 431 |
s->control[0] = value & 0x07ffffff; |
| 432 |
pxa2xx_lcdc_int_update(s); |
| 433 |
|
| 434 |
s->dma_ch[0].up = !!(value & LCCR0_ENB);
|
| 435 |
s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS); |
| 436 |
break;
|
| 437 |
|
| 438 |
case LCCR1:
|
| 439 |
s->control[1] = value;
|
| 440 |
break;
|
| 441 |
|
| 442 |
case LCCR2:
|
| 443 |
s->control[2] = value;
|
| 444 |
break;
|
| 445 |
|
| 446 |
case LCCR3:
|
| 447 |
s->control[3] = value & 0xefffffff; |
| 448 |
s->bpp = LCCR3_BPP(value); |
| 449 |
break;
|
| 450 |
|
| 451 |
case LCCR4:
|
| 452 |
s->control[4] = value & 0x83ff81ff; |
| 453 |
break;
|
| 454 |
|
| 455 |
case LCCR5:
|
| 456 |
s->control[5] = value & 0x3f3f3f3f; |
| 457 |
break;
|
| 458 |
|
| 459 |
case OVL1C1:
|
| 460 |
if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN)) |
| 461 |
printf("%s: Overlay 1 not supported\n", __FUNCTION__);
|
| 462 |
|
| 463 |
s->ovl1c[0] = value & 0x80ffffff; |
| 464 |
s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS); |
| 465 |
break;
|
| 466 |
|
| 467 |
case OVL1C2:
|
| 468 |
s->ovl1c[1] = value & 0x000fffff; |
| 469 |
break;
|
| 470 |
|
| 471 |
case OVL2C1:
|
| 472 |
if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN)) |
| 473 |
printf("%s: Overlay 2 not supported\n", __FUNCTION__);
|
| 474 |
|
| 475 |
s->ovl2c[0] = value & 0x80ffffff; |
| 476 |
s->dma_ch[2].up = !!(value & OVLC1_EN);
|
| 477 |
s->dma_ch[3].up = !!(value & OVLC1_EN);
|
| 478 |
s->dma_ch[4].up = !!(value & OVLC1_EN);
|
| 479 |
break;
|
| 480 |
|
| 481 |
case OVL2C2:
|
| 482 |
s->ovl2c[1] = value & 0x007fffff; |
| 483 |
break;
|
| 484 |
|
| 485 |
case CCR:
|
| 486 |
if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
|
| 487 |
printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
|
| 488 |
|
| 489 |
s->ccr = value & 0x81ffffe7;
|
| 490 |
s->dma_ch[5].up = !!(value & CCR_CEN);
|
| 491 |
break;
|
| 492 |
|
| 493 |
case CMDCR:
|
| 494 |
s->cmdcr = value & 0xff;
|
| 495 |
break;
|
| 496 |
|
| 497 |
case TRGBR:
|
| 498 |
s->trgbr = value & 0x00ffffff;
|
| 499 |
break;
|
| 500 |
|
| 501 |
case TCR:
|
| 502 |
s->tcr = value & 0x7fff;
|
| 503 |
break;
|
| 504 |
|
| 505 |
case 0x200 ... 0x1000: /* DMA per-channel registers */ |
| 506 |
ch = (offset - 0x200) >> 4; |
| 507 |
if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS)) |
| 508 |
goto fail;
|
| 509 |
|
| 510 |
switch (offset & 0xf) { |
| 511 |
case DMA_FDADR:
|
| 512 |
s->dma_ch[ch].descriptor = value & 0xfffffff0;
|
| 513 |
break;
|
| 514 |
|
| 515 |
default:
|
| 516 |
goto fail;
|
| 517 |
} |
| 518 |
break;
|
| 519 |
|
| 520 |
case FBR0:
|
| 521 |
s->dma_ch[0].branch = value & 0xfffffff3; |
| 522 |
break;
|
| 523 |
case FBR1:
|
| 524 |
s->dma_ch[1].branch = value & 0xfffffff3; |
| 525 |
break;
|
| 526 |
case FBR2:
|
| 527 |
s->dma_ch[2].branch = value & 0xfffffff3; |
| 528 |
break;
|
| 529 |
case FBR3:
|
| 530 |
s->dma_ch[3].branch = value & 0xfffffff3; |
| 531 |
break;
|
| 532 |
case FBR4:
|
| 533 |
s->dma_ch[4].branch = value & 0xfffffff3; |
| 534 |
break;
|
| 535 |
case FBR5:
|
| 536 |
s->dma_ch[5].branch = value & 0xfffffff3; |
| 537 |
break;
|
| 538 |
case FBR6:
|
| 539 |
s->dma_ch[6].branch = value & 0xfffffff3; |
| 540 |
break;
|
| 541 |
|
| 542 |
case BSCNTR:
|
| 543 |
s->bscntr = value & 0xf;
|
| 544 |
break;
|
| 545 |
|
| 546 |
case PRSR:
|
| 547 |
break;
|
| 548 |
|
| 549 |
case LCSR0:
|
| 550 |
s->status[0] &= ~(value & 0xfff); |
| 551 |
if (value & LCSR0_BER)
|
| 552 |
s->status[0] &= ~LCSR0_BERCH(7); |
| 553 |
break;
|
| 554 |
|
| 555 |
case LCSR1:
|
| 556 |
s->status[1] &= ~(value & 0x3e3f3f); |
| 557 |
break;
|
| 558 |
|
| 559 |
default:
|
| 560 |
fail:
|
| 561 |
cpu_abort(cpu_single_env, |
| 562 |
"%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); |
| 563 |
} |
| 564 |
} |
| 565 |
|
| 566 |
static CPUReadMemoryFunc *pxa2xx_lcdc_readfn[] = {
|
| 567 |
pxa2xx_lcdc_read, |
| 568 |
pxa2xx_lcdc_read, |
| 569 |
pxa2xx_lcdc_read |
| 570 |
}; |
| 571 |
|
| 572 |
static CPUWriteMemoryFunc *pxa2xx_lcdc_writefn[] = {
|
| 573 |
pxa2xx_lcdc_write, |
| 574 |
pxa2xx_lcdc_write, |
| 575 |
pxa2xx_lcdc_write |
| 576 |
}; |
| 577 |
|
| 578 |
static inline |
| 579 |
uint32_t rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b) |
| 580 |
{
|
| 581 |
return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6); |
| 582 |
} |
| 583 |
|
| 584 |
static inline |
| 585 |
uint32_t rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b) |
| 586 |
{
|
| 587 |
return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3); |
| 588 |
} |
| 589 |
|
| 590 |
static inline |
| 591 |
uint32_t rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b) |
| 592 |
{
|
| 593 |
return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3); |
| 594 |
} |
| 595 |
|
| 596 |
static inline |
| 597 |
uint32_t rgb_to_pixel24(unsigned int r, unsigned int g, unsigned b) |
| 598 |
{
|
| 599 |
return (r << 16) | (g << 8) | b; |
| 600 |
} |
| 601 |
|
| 602 |
static inline |
| 603 |
uint32_t rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b) |
| 604 |
{
|
| 605 |
return (r << 16) | (g << 8) | b; |
| 606 |
} |
| 607 |
|
| 608 |
/* Load new palette for a given DMA channel, convert to internal format */
|
| 609 |
static void pxa2xx_palette_parse(struct pxa2xx_lcdc_s *s, int ch, int bpp) |
| 610 |
{
|
| 611 |
int i, n, format, r, g, b, alpha;
|
| 612 |
uint32_t *dest, *src; |
| 613 |
s->pal_for = LCCR4_PALFOR(s->control[4]);
|
| 614 |
format = s->pal_for; |
| 615 |
|
| 616 |
switch (bpp) {
|
| 617 |
case pxa_lcdc_2bpp:
|
| 618 |
n = 4;
|
| 619 |
break;
|
| 620 |
case pxa_lcdc_4bpp:
|
| 621 |
n = 16;
|
| 622 |
break;
|
| 623 |
case pxa_lcdc_8bpp:
|
| 624 |
n = 256;
|
| 625 |
break;
|
| 626 |
default:
|
| 627 |
format = 0;
|
| 628 |
return;
|
| 629 |
} |
| 630 |
|
| 631 |
src = (uint32_t *) s->dma_ch[ch].pbuffer; |
| 632 |
dest = (uint32_t *) s->dma_ch[ch].palette; |
| 633 |
alpha = r = g = b = 0;
|
| 634 |
|
| 635 |
for (i = 0; i < n; i ++) { |
| 636 |
switch (format) {
|
| 637 |
case 0: /* 16 bpp, no transparency */ |
| 638 |
alpha = 0;
|
| 639 |
if (s->control[0] & LCCR0_CMS) |
| 640 |
r = g = b = *src & 0xff;
|
| 641 |
else {
|
| 642 |
r = (*src & 0xf800) >> 8; |
| 643 |
g = (*src & 0x07e0) >> 3; |
| 644 |
b = (*src & 0x001f) << 3; |
| 645 |
} |
| 646 |
break;
|
| 647 |
case 1: /* 16 bpp plus transparency */ |
| 648 |
alpha = *src & (1 << 24); |
| 649 |
if (s->control[0] & LCCR0_CMS) |
| 650 |
r = g = b = *src & 0xff;
|
| 651 |
else {
|
| 652 |
r = (*src & 0xf800) >> 8; |
| 653 |
g = (*src & 0x07e0) >> 3; |
| 654 |
b = (*src & 0x001f) << 3; |
| 655 |
} |
| 656 |
break;
|
| 657 |
case 2: /* 18 bpp plus transparency */ |
| 658 |
alpha = *src & (1 << 24); |
| 659 |
if (s->control[0] & LCCR0_CMS) |
| 660 |
r = g = b = *src & 0xff;
|
| 661 |
else {
|
| 662 |
r = (*src & 0xf80000) >> 16; |
| 663 |
g = (*src & 0x00fc00) >> 8; |
| 664 |
b = (*src & 0x0000f8);
|
| 665 |
} |
| 666 |
break;
|
| 667 |
case 3: /* 24 bpp plus transparency */ |
| 668 |
alpha = *src & (1 << 24); |
| 669 |
if (s->control[0] & LCCR0_CMS) |
| 670 |
r = g = b = *src & 0xff;
|
| 671 |
else {
|
| 672 |
r = (*src & 0xff0000) >> 16; |
| 673 |
g = (*src & 0x00ff00) >> 8; |
| 674 |
b = (*src & 0x0000ff);
|
| 675 |
} |
| 676 |
break;
|
| 677 |
} |
| 678 |
switch (s->ds->depth) {
|
| 679 |
case 8: |
| 680 |
*dest = rgb_to_pixel8(r, g, b) | alpha; |
| 681 |
break;
|
| 682 |
case 15: |
| 683 |
*dest = rgb_to_pixel15(r, g, b) | alpha; |
| 684 |
break;
|
| 685 |
case 16: |
| 686 |
*dest = rgb_to_pixel16(r, g, b) | alpha; |
| 687 |
break;
|
| 688 |
case 24: |
| 689 |
*dest = rgb_to_pixel24(r, g, b) | alpha; |
| 690 |
break;
|
| 691 |
case 32: |
| 692 |
*dest = rgb_to_pixel32(r, g, b) | alpha; |
| 693 |
break;
|
| 694 |
} |
| 695 |
src ++; |
| 696 |
dest ++; |
| 697 |
} |
| 698 |
} |
| 699 |
|
| 700 |
static void pxa2xx_lcdc_dma0_redraw_horiz(struct pxa2xx_lcdc_s *s, |
| 701 |
uint8_t *fb, int *miny, int *maxy) |
| 702 |
{
|
| 703 |
int y, src_width, dest_width, dirty[2]; |
| 704 |
uint8_t *src, *dest; |
| 705 |
ram_addr_t x, addr, new_addr, start, end; |
| 706 |
drawfn fn = 0;
|
| 707 |
if (s->dest_width)
|
| 708 |
fn = s->line_fn[s->transp][s->bpp]; |
| 709 |
if (!fn)
|
| 710 |
return;
|
| 711 |
|
| 712 |
src = fb; |
| 713 |
src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */ |
| 714 |
if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
|
| 715 |
src_width *= 3;
|
| 716 |
else if (s->bpp > pxa_lcdc_16bpp) |
| 717 |
src_width *= 4;
|
| 718 |
else if (s->bpp > pxa_lcdc_8bpp) |
| 719 |
src_width *= 2;
|
| 720 |
|
| 721 |
dest = s->ds->data; |
| 722 |
dest_width = s->xres * s->dest_width; |
| 723 |
|
| 724 |
addr = (ram_addr_t) (fb - phys_ram_base); |
| 725 |
start = addr + s->yres * src_width; |
| 726 |
end = addr; |
| 727 |
dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG); |
| 728 |
for (y = 0; y < s->yres; y ++) { |
| 729 |
new_addr = addr + src_width; |
| 730 |
for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
|
| 731 |
x += TARGET_PAGE_SIZE) {
|
| 732 |
dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
|
| 733 |
dirty[0] |= dirty[1]; |
| 734 |
} |
| 735 |
if (dirty[0] || s->invalidated) { |
| 736 |
fn((uint32_t *) s->dma_ch[0].palette,
|
| 737 |
dest, src, s->xres, s->dest_width); |
| 738 |
if (addr < start)
|
| 739 |
start = addr; |
| 740 |
end = new_addr; |
| 741 |
if (y < *miny)
|
| 742 |
*miny = y; |
| 743 |
if (y >= *maxy)
|
| 744 |
*maxy = y + 1;
|
| 745 |
} |
| 746 |
addr = new_addr; |
| 747 |
dirty[0] = dirty[1]; |
| 748 |
src += src_width; |
| 749 |
dest += dest_width; |
| 750 |
} |
| 751 |
|
| 752 |
if (end > start)
|
| 753 |
cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG); |
| 754 |
} |
| 755 |
|
| 756 |
static void pxa2xx_lcdc_dma0_redraw_vert(struct pxa2xx_lcdc_s *s, |
| 757 |
uint8_t *fb, int *miny, int *maxy) |
| 758 |
{
|
| 759 |
int y, src_width, dest_width, dirty[2]; |
| 760 |
uint8_t *src, *dest; |
| 761 |
ram_addr_t x, addr, new_addr, start, end; |
| 762 |
drawfn fn = 0;
|
| 763 |
if (s->dest_width)
|
| 764 |
fn = s->line_fn[s->transp][s->bpp]; |
| 765 |
if (!fn)
|
| 766 |
return;
|
| 767 |
|
| 768 |
src = fb; |
| 769 |
src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */ |
| 770 |
if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
|
| 771 |
src_width *= 3;
|
| 772 |
else if (s->bpp > pxa_lcdc_16bpp) |
| 773 |
src_width *= 4;
|
| 774 |
else if (s->bpp > pxa_lcdc_8bpp) |
| 775 |
src_width *= 2;
|
| 776 |
|
| 777 |
dest_width = s->yres * s->dest_width; |
| 778 |
dest = s->ds->data + dest_width * (s->xres - 1);
|
| 779 |
|
| 780 |
addr = (ram_addr_t) (fb - phys_ram_base); |
| 781 |
start = addr + s->yres * src_width; |
| 782 |
end = addr; |
| 783 |
dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG); |
| 784 |
for (y = 0; y < s->yres; y ++) { |
| 785 |
new_addr = addr + src_width; |
| 786 |
for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
|
| 787 |
x += TARGET_PAGE_SIZE) {
|
| 788 |
dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
|
| 789 |
dirty[0] |= dirty[1]; |
| 790 |
} |
| 791 |
if (dirty[0] || s->invalidated) { |
| 792 |
fn((uint32_t *) s->dma_ch[0].palette,
|
| 793 |
dest, src, s->xres, -dest_width); |
| 794 |
if (addr < start)
|
| 795 |
start = addr; |
| 796 |
if (new_addr > end)
|
| 797 |
end = new_addr; |
| 798 |
if (y < *miny)
|
| 799 |
*miny = y; |
| 800 |
if (y >= *maxy)
|
| 801 |
*maxy = y + 1;
|
| 802 |
} |
| 803 |
addr = new_addr; |
| 804 |
dirty[0] = dirty[1]; |
| 805 |
src += src_width; |
| 806 |
dest += s->dest_width; |
| 807 |
} |
| 808 |
|
| 809 |
if (end > start)
|
| 810 |
cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG); |
| 811 |
} |
| 812 |
|
| 813 |
static void pxa2xx_lcdc_resize(struct pxa2xx_lcdc_s *s) |
| 814 |
{
|
| 815 |
int width, height;
|
| 816 |
if (!(s->control[0] & LCCR0_ENB)) |
| 817 |
return;
|
| 818 |
|
| 819 |
width = LCCR1_PPL(s->control[1]) + 1; |
| 820 |
height = LCCR2_LPP(s->control[2]) + 1; |
| 821 |
|
| 822 |
if (width != s->xres || height != s->yres) {
|
| 823 |
if (s->orientation)
|
| 824 |
dpy_resize(s->ds, height, width); |
| 825 |
else
|
| 826 |
dpy_resize(s->ds, width, height); |
| 827 |
s->invalidated = 1;
|
| 828 |
s->xres = width; |
| 829 |
s->yres = height; |
| 830 |
} |
| 831 |
} |
| 832 |
|
| 833 |
static void pxa2xx_update_display(void *opaque) |
| 834 |
{
|
| 835 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
| 836 |
uint8_t *fb; |
| 837 |
target_phys_addr_t fbptr; |
| 838 |
int miny, maxy;
|
| 839 |
int ch;
|
| 840 |
if (!(s->control[0] & LCCR0_ENB)) |
| 841 |
return;
|
| 842 |
|
| 843 |
pxa2xx_descriptor_load(s); |
| 844 |
|
| 845 |
pxa2xx_lcdc_resize(s); |
| 846 |
miny = s->yres; |
| 847 |
maxy = 0;
|
| 848 |
s->transp = s->dma_ch[2].up || s->dma_ch[3].up; |
| 849 |
/* Note: With overlay planes the order depends on LCCR0 bit 25. */
|
| 850 |
for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++) |
| 851 |
if (s->dma_ch[ch].up) {
|
| 852 |
if (!s->dma_ch[ch].source) {
|
| 853 |
pxa2xx_dma_ber_set(s, ch); |
| 854 |
continue;
|
| 855 |
} |
| 856 |
fbptr = s->dma_ch[ch].source; |
| 857 |
if (!(fbptr >= PXA2XX_SDRAM_BASE &&
|
| 858 |
fbptr <= PXA2XX_SDRAM_BASE + phys_ram_size)) {
|
| 859 |
pxa2xx_dma_ber_set(s, ch); |
| 860 |
continue;
|
| 861 |
} |
| 862 |
fbptr -= PXA2XX_SDRAM_BASE; |
| 863 |
fb = phys_ram_base + fbptr; |
| 864 |
|
| 865 |
if (s->dma_ch[ch].command & LDCMD_PAL) {
|
| 866 |
memcpy(s->dma_ch[ch].pbuffer, fb, |
| 867 |
MAX(LDCMD_LENGTH(s->dma_ch[ch].command), |
| 868 |
sizeof(s->dma_ch[ch].pbuffer)));
|
| 869 |
pxa2xx_palette_parse(s, ch, s->bpp); |
| 870 |
} else {
|
| 871 |
/* Do we need to reparse palette */
|
| 872 |
if (LCCR4_PALFOR(s->control[4]) != s->pal_for) |
| 873 |
pxa2xx_palette_parse(s, ch, s->bpp); |
| 874 |
|
| 875 |
/* ACK frame start */
|
| 876 |
pxa2xx_dma_sof_set(s, ch); |
| 877 |
|
| 878 |
s->dma_ch[ch].redraw(s, fb, &miny, &maxy); |
| 879 |
s->invalidated = 0;
|
| 880 |
|
| 881 |
/* ACK frame completed */
|
| 882 |
pxa2xx_dma_eof_set(s, ch); |
| 883 |
} |
| 884 |
} |
| 885 |
|
| 886 |
if (s->control[0] & LCCR0_DIS) { |
| 887 |
/* ACK last frame completed */
|
| 888 |
s->control[0] &= ~LCCR0_ENB;
|
| 889 |
s->status[0] |= LCSR0_LDD;
|
| 890 |
} |
| 891 |
|
| 892 |
if (s->orientation)
|
| 893 |
dpy_update(s->ds, miny, 0, maxy, s->xres);
|
| 894 |
else
|
| 895 |
dpy_update(s->ds, 0, miny, s->xres, maxy);
|
| 896 |
pxa2xx_lcdc_int_update(s); |
| 897 |
|
| 898 |
if (s->vsync_cb)
|
| 899 |
s->vsync_cb(s->opaque); |
| 900 |
} |
| 901 |
|
| 902 |
static void pxa2xx_invalidate_display(void *opaque) |
| 903 |
{
|
| 904 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
| 905 |
s->invalidated = 1;
|
| 906 |
} |
| 907 |
|
| 908 |
static void pxa2xx_screen_dump(void *opaque, const char *filename) |
| 909 |
{
|
| 910 |
/* TODO */
|
| 911 |
} |
| 912 |
|
| 913 |
void pxa2xx_lcdc_orientation(void *opaque, int angle) |
| 914 |
{
|
| 915 |
struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque; |
| 916 |
|
| 917 |
if (angle) {
|
| 918 |
s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_vert;
|
| 919 |
} else {
|
| 920 |
s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_horiz;
|
| 921 |
} |
| 922 |
|
| 923 |
s->orientation = angle; |
| 924 |
s->xres = s->yres = -1;
|
| 925 |
pxa2xx_lcdc_resize(s); |
| 926 |
} |
| 927 |
|
| 928 |
#define BITS 8 |
| 929 |
#include "pxa2xx_template.h" |
| 930 |
#define BITS 15 |
| 931 |
#include "pxa2xx_template.h" |
| 932 |
#define BITS 16 |
| 933 |
#include "pxa2xx_template.h" |
| 934 |
#define BITS 24 |
| 935 |
#include "pxa2xx_template.h" |
| 936 |
#define BITS 32 |
| 937 |
#include "pxa2xx_template.h" |
| 938 |
|
| 939 |
struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq,
|
| 940 |
DisplayState *ds) |
| 941 |
{
|
| 942 |
int iomemtype;
|
| 943 |
struct pxa2xx_lcdc_s *s;
|
| 944 |
|
| 945 |
s = (struct pxa2xx_lcdc_s *) qemu_mallocz(sizeof(struct pxa2xx_lcdc_s)); |
| 946 |
s->base = base; |
| 947 |
s->invalidated = 1;
|
| 948 |
s->irq = irq; |
| 949 |
s->ds = ds; |
| 950 |
|
| 951 |
pxa2xx_lcdc_orientation(s, graphic_rotate); |
| 952 |
|
| 953 |
iomemtype = cpu_register_io_memory(0, pxa2xx_lcdc_readfn,
|
| 954 |
pxa2xx_lcdc_writefn, s); |
| 955 |
cpu_register_physical_memory(base, 0x000fffff, iomemtype);
|
| 956 |
|
| 957 |
graphic_console_init(ds, pxa2xx_update_display, |
| 958 |
pxa2xx_invalidate_display, pxa2xx_screen_dump, s); |
| 959 |
|
| 960 |
switch (s->ds->depth) {
|
| 961 |
case 0: |
| 962 |
s->dest_width = 0;
|
| 963 |
break;
|
| 964 |
case 8: |
| 965 |
s->line_fn[0] = pxa2xx_draw_fn_8;
|
| 966 |
s->line_fn[1] = pxa2xx_draw_fn_8t;
|
| 967 |
s->dest_width = 1;
|
| 968 |
break;
|
| 969 |
case 15: |
| 970 |
s->line_fn[0] = pxa2xx_draw_fn_15;
|
| 971 |
s->line_fn[1] = pxa2xx_draw_fn_15t;
|
| 972 |
s->dest_width = 2;
|
| 973 |
break;
|
| 974 |
case 16: |
| 975 |
s->line_fn[0] = pxa2xx_draw_fn_16;
|
| 976 |
s->line_fn[1] = pxa2xx_draw_fn_16t;
|
| 977 |
s->dest_width = 2;
|
| 978 |
break;
|
| 979 |
case 24: |
| 980 |
s->line_fn[0] = pxa2xx_draw_fn_24;
|
| 981 |
s->line_fn[1] = pxa2xx_draw_fn_24t;
|
| 982 |
s->dest_width = 3;
|
| 983 |
break;
|
| 984 |
case 32: |
| 985 |
s->line_fn[0] = pxa2xx_draw_fn_32;
|
| 986 |
s->line_fn[1] = pxa2xx_draw_fn_32t;
|
| 987 |
s->dest_width = 4;
|
| 988 |
break;
|
| 989 |
default:
|
| 990 |
fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
|
| 991 |
exit(1);
|
| 992 |
} |
| 993 |
return s;
|
| 994 |
} |
| 995 |
|
| 996 |
void pxa2xx_lcd_vsync_cb(struct pxa2xx_lcdc_s *s, |
| 997 |
void (*cb)(void *opaque), void *opaque) { |
| 998 |
s->vsync_cb = cb; |
| 999 |
s->opaque = opaque; |
| 1000 |
} |