Archipelago » qemu

    pci_register_bar (&d->dev, 0, 256 * 4, PCI_ADDRESS_SPACE_IO, ac97_map);

    pci_register_bar (&d->dev, 1, 64 * 4, PCI_ADDRESS_SPACE_IO, ac97_map);

    register_savevm ("ac97", 0, 2, ac97_save, ac97_load, s);

    AUD_register_card ("ac97", &s->card);

    ac97_on_reset (s);

    return 0;

    s->smbus = i2c_init_bus(NULL, "i2c");

    s->irq = sci_irq;

    return s->smbus;

}

    d->devreq = devreq;

    d->devreset = devreset;

    d->opaque = opaque;

    d->devreset(d);

    return d;

}

    s->timer = qemu_new_timer(vm_clock, apic_timer, s);

    register_savevm("apic", s->idx, 2, apic_save, apic_load, s);

    local_apics[s->idx] = s;

    return 0;

        if (info->nb_cpus == 0)

            info->nb_cpus = 1;

        env->boot_info = info;

    }

    /* Assume that raw images are linux kernels, and ELF images are not.  */

        cpu_model = "crisv32";

    }

    env = cpu_init(cpu_model);

    /* allocate RAM */

    phys_ram = qemu_ram_alloc(ram_size);

    s->vga.cursor_invalidate = cirrus_cursor_invalidate;

    s->vga.cursor_draw_line = cirrus_cursor_draw_line;

    cirrus_reset(s);

    register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);

}

    cs_io_memory = cpu_register_io_memory(cs_mem_read, cs_mem_write, s);

    cpu_register_physical_memory(base, CS_SIZE, cs_io_memory);

    register_savevm("cs4231", base, 1, cs_save, cs_load, s);

    cs_reset(s);

}

    DMA_register_channel (s->dma, cs_dma_read, s);

    register_savevm ("cs4231a", 0, 1, cs_save, cs_load, s);

    cs_reset (s);

    AUD_register_card ("cs4231a", &s->card);

    s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);

    *cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s);

    register_savevm("cuda", -1, 1, cuda_save, cuda_load, s);

    cuda_reset(s);

}

        register_ioport_read (base + ((i + 8) << dshift), 1, 1,

                              read_cont, d);

    }

    dma_reset(d);

    for (i = 0; i < ARRAY_SIZE (d->regs); ++i) {

        d->regs[i].transfer_handler = dma_phony_handler;

                                 nic_receive, NULL, nic_cleanup, s);

    qemu_format_nic_info_str(s->vc, nd->macaddr);

    nic_reset(s);

    s->mmio_index = cpu_register_io_memory(dp8393x_read, dp8393x_write, s);

    register_savevm(info_str, -1, 2, nic_save, nic_load, d);

    d->dev.unregister = pci_e1000_uninit;

    e1000_reset(d);

}

                                     ecc_io_memory);

    }

    register_savevm("ECC", base, 3, ecc_save, ecc_load, s);

    ecc_reset(s);

    return s;

}

    qemu_format_nic_info_str(s->vc, s->macaddr);

    register_savevm(s->vc->model, -1, 3, nic_save, nic_load, s);

}

    pci_register_bar (&d->dev, 0, 256, PCI_ADDRESS_SPACE_IO, es1370_map);

    register_savevm ("es1370", 0, 2, es1370_save, es1370_load, s);

    AUD_register_card ("es1370", &s->card);

    es1370_reset (s);

        register_savevm("escc", base, 2, escc_save, escc_load, s);

    else

        register_savevm("escc", -1, 2, escc_save, escc_load, s);

    escc_reset(s);

    return escc_io_memory;

}

                                 "QEMU Sun Mouse");

    qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]);

    register_savevm("slavio_serial_mouse", base, 2, escc_save, escc_load, s);

    escc_reset(s);

}

    esp_reset(s);

    register_savevm("esp", -1, 3, esp_save, esp_load, s);

    qdev_init_gpio_in(&dev->qdev, parent_esp_reset, 1);

        cpu_model = "crisv32";

    }

    env = cpu_init(cpu_model);

    /* allocate RAM */

    phys_ram = qemu_ram_alloc(ram_size);

    timer_regs = cpu_register_io_memory(timer_read, timer_write, t);

    sysbus_init_mmio(dev, 0x5c, timer_regs);

}

static void etraxfs_timer_register(void)

    }

    fdctrl_external_reset(fdctrl);

    register_savevm("fdc", io_base, 2, fdc_save, fdc_load, fdctrl);

    for (i = 0; i < MAX_FD; i++) {

        fd_revalidate(&fdctrl->drives[i]);

    }

    fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);

    register_savevm("fw_cfg", -1, 1, fw_cfg_save, fw_cfg_load, s);

    fw_cfg_reset(s);

    return s;

    s->vram = qemu_get_ram_ptr(s->vram_offset);

    s->irq = irq;

    register_savevm("g364fb", 0, 1, g364fb_save, g364fb_load, s);

    g364fb_reset(s);

    d->config[0x27] = 0x85;

#endif

    register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load, d);

    pci_grackle_reset(d);

    return s->bus;

    register_savevm("heathrow_pic", -1, 1, heathrow_pic_save,

                    heathrow_pic_load, s);

    heathrow_pic_reset(s);

    return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64);

}

    }

    hpet_reset(s);

    register_savevm("hpet", -1, 1, hpet_save, hpet_load, s);

    /* HPET Area */

    iomemtype = cpu_register_io_memory(hpet_ram_read,

                                       hpet_ram_write, s);

typedef void QEMUResetHandler(void *opaque);

/* handler to set the boot_device for a specific type of QEMUMachine */

/* return 0 if success */

    register_savevm("i8254", base, 1, pit_save, pit_load, pit);

    register_ioport_write(base, 4, 1, pit_ioport_write, pit);

    register_ioport_read(base, 3, 1, pit_ioport_read, pit);

        register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);

    }

    register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);

}

void pic_info(Monitor *mon)

    ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], irq[1]);

    register_savevm("ide", 0, 2, pci_ide_save, pci_ide_load, d);

    cmd646_reset(d);

}

    pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);

    pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type

    piix3_reset(d);

    pci_register_bar((PCIDevice *)d, 4, 0x10,

    pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);

    pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type

    piix3_reset(d);

    pci_register_bar((PCIDevice *)d, 4, 0x10,

    pmac_ide_memory = cpu_register_io_memory(pmac_ide_read,

                                             pmac_ide_write, d);

    register_savevm("ide", 0, 1, pmac_ide_save, pmac_ide_load, d);

    pmac_ide_reset(d);

    return pmac_ide_memory;

    cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);

    register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);

    return s;

}

    cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);

    register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);

    iommu_reset(s);

    return s;

}

    lm_kbd_reset(s);

    register_savevm("LM8323", -1, 0, lm_kbd_save, lm_kbd_load, s);

}

    }

    qemu_get_timedate(&s->alarm, 0);

    save_base = mem_base ? mem_base : io_base;

    register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s);

    *dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s);

    register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, s);

    dbdma_reset(s);

    dbdma_bh = qemu_bh_new(DBDMA_run_bh, s);

    *mem_index = s->mem_index;

    register_savevm("macio_nvram", -1, 1, macio_nvram_save, macio_nvram_load,

                    s);

    macio_nvram_reset(s);

    return s;

    if (rtc_td_hack)

        register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s);

#endif

    return s;

}

    if (rtc_td_hack)

        register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s);

#endif

    return s;

}

        fprintf(stderr, "Unable to find CPU definition\n");

        exit(1);

    }

    /* allocate RAM */

    ram_offset = qemu_ram_alloc(ram_size);

    s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1);

    malta_fpga_reset(s);

    return s;

}

        fprintf(stderr, "Unable to find CPU definition\n");

        exit(1);

    }

    /* allocate RAM */

    if (ram_size > (256 << 20)) {

        fprintf(stderr, "Unable to find CPU definition\n");

        exit(1);

    }

    /* Allocate RAM. */

    ram_offset = qemu_ram_alloc(ram_size);

        fprintf(stderr, "Unable to find CPU definition\n");

        exit(1);

    }

    /* allocate RAM */

    if (ram_size > (256 << 20)) {

                       musicpal_audio_writefn, s);

    cpu_register_physical_memory(MP_AUDIO_BASE, MP_AUDIO_SIZE, iomemtype);

    return i2c;

}

                                       mv88w8618_pic_writefn, s);

    sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype);

}

/* PIT register offsets */

        binfo->initrd_filename = initrd_filename;

        arm_load_kernel(s->cpu->env, binfo);

        n8x0_boot_init(s);

    }

    omap_setup_dsp_mapping(omap15xx_dsp_mm);

    omap_setup_mpui_io(s);

    return s;

}

     * GPMC registers	6800a000   6800afff

     */

    return s;

}

    opp->need_swap = 1;

    register_savevm("openpic", 0, 2, openpic_save, openpic_load, opp);

    opp->irq_raise = openpic_irq_raise;

    opp->reset = openpic_reset;

    mpp->reset = mpic_reset;

    register_savevm("mpic", 0, 2, openpic_save, openpic_load, mpp);

    mpp->reset(mpp);

    return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);

    s->irq = irq;

    s->chr = chr;

    parallel_reset(s);

    if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {

        s->hw_driver = 1;

    s->chr = chr;

    s->it_shift = it_shift;

    parallel_reset(s);

    io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw, s);

    cpu_register_physical_memory(base, 8 << it_shift, io_sw);

    cpu_physical_memory_read(addr, rrd->data, size);

    rrd->addr = addr;

    rrd->size = size;

}

static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)

            /* APIC reset callback resets cpu */

            apic_init(env);

        } else {

        }

    }

    bus->next = first_bus;

    first_bus = bus;

    register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);

    return bus;

}

#ifdef TARGET_I386

    vmmouse_init(s->mouse);

#endif

}

/* Memory mapped interface */

#ifdef TARGET_I386

    vmmouse_init(s->mouse);

#endif

}

    env = cpu_init(cpu_model);

    env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family.  */

    /* Attach emulated BRAM through the LMB.  */

    phys_lmb_bram = qemu_ram_alloc(LMB_BRAM_SIZE);

        PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic

    piix3_reset(d);

    return d->devfn;

}

    piix4_reset(d);

    return d->devfn;

}

    sysbus_init_irq(dev, &s->irq[1]);

    bd = qdev_init_bdrv(&dev->qdev, IF_SD);

    s->card = sd_init(bd, 0);

    pl181_reset(s);

    /* ??? Save/restore.  */

}

                                         ref405ep_fpga_write, fpga);

    cpu_register_physical_memory(base, 0x00000100, fpga_memory);

    ref405ep_fpga_reset(fpga);

}

static void ref405ep_init (ram_addr_t ram_size,

                                         taihu_cpld_write, cpld);

    cpu_register_physical_memory(base, 0x00000100, cpld_memory);

    taihu_cpld_reset(cpld);

}

static void taihu_405ep_init(ram_addr_t ram_size,

    ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);

    ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);

    ppc4xx_plb_reset(plb);

}

/*****************************************************************************/

    ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);

    ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);

    ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);

    ppc4xx_pob_reset(env);

}

#endif

    ppc4xx_mmio_register(env, mmio, offset, 0x002,

                         opba_read, opba_write, opba);

    ppc4xx_opba_reset(opba);

}

    ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));

    ebc_reset(ebc);

    ppc_dcr_register(env, EBC0_CFGADDR,

                     ebc, &dcr_read_ebc, &dcr_write_ebc);

    ppc_dcr_register(env, EBC0_CFGDATA,

    dma = qemu_mallocz(sizeof(ppc405_dma_t));

    memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));

    ppc405_dma_reset(dma);

    ppc_dcr_register(env, DMA0_CR0,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_CT0,

    gpio = qemu_mallocz(sizeof(ppc405_gpio_t));

    gpio->base = offset;

    ppc405_gpio_reset(gpio);

#ifdef DEBUG_GPIO

    printf("%s: offset " PADDRX "\n", __func__, offset);

#endif

    ocm = qemu_mallocz(sizeof(ppc405_ocm_t));

    ocm->offset = qemu_ram_alloc(4096);

    ocm_reset(ocm);

    ppc_dcr_register(env, OCM0_ISARC,

                     ocm, &dcr_read_ocm, &dcr_write_ocm);

    ppc_dcr_register(env, OCM0_ISACNTL,

#endif

    ppc4xx_mmio_register(env, mmio, offset, 0x011,

                         i2c_read, i2c_write, i2c);

}

/*****************************************************************************/

#endif

    ppc4xx_mmio_register(env, mmio, offset, 0x0D4,

                         gpt_read, gpt_write, gpt);

}

/*****************************************************************************/

    for (i = 0; i < 4; i++)

        mal->irqs[i] = irqs[i];

    ppc40x_mal_reset(mal);

    ppc_dcr_register(env, MAL0_CFG,

                     mal, &dcr_read_mal, &dcr_write_mal);

    ppc_dcr_register(env, MAL0_ESR,

    ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,

                     &dcr_read_crcpc, &dcr_write_crcpc);

    ppc405cr_clk_init(cpc);

    ppc405cr_cpc_reset(cpc);

}

    cpc->jtagid = 0x20267049;

    cpc->sysclk = sysclk;

    ppc405ep_cpc_reset(cpc);

    ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,

                     &dcr_read_epcpc, &dcr_write_epcpc);

    ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,

    tb_clk->opaque = env;

    ppc_dcr_init(env, NULL, NULL);

    /* Register qemu callbacks */

    return env;

}

        ppc_dcr_register(env, dcr_base + i, uic,

                         &dcr_read_uic, &dcr_write_uic);

    }

    ppcuic_reset(uic);

    return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);

    memcpy(sdram->ram_sizes, ram_sizes,

           nbanks * sizeof(target_phys_addr_t));

    sdram_reset(sdram);

    ppc_dcr_register(env, SDRAM0_CFGADDR,

                     sdram, &dcr_read_sdram, &dcr_write_sdram);

    ppc_dcr_register(env, SDRAM0_CFGDATA,

        goto free;

    cpu_register_physical_memory(registers, PCI_REG_SIZE, index);

    /* XXX load/save code not tested. */

    register_savevm("ppc4xx_pci", ppc4xx_pci_id++, 1,

#if 0

        env->osi_call = vga_osi_call;

#endif

        envs[i] = env;

    }

        /* Set time-base frequency to 16.6 Mhz */

        cpu_ppc_tb_init(env,  16600000UL);

        env->osi_call = vga_osi_call;

        envs[i] = env;

    }

            /* Set time-base frequency to 100 Mhz */

            cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);

        }

        envs[i] = env;

    }

    ps2_reset(&s->common);

    register_savevm("ps2kbd", 0, 3, ps2_kbd_save, ps2_kbd_load, s);

    qemu_add_kbd_event_handler(ps2_put_keycode, s);

    return s;

}

    ps2_reset(&s->common);

    register_savevm("ps2mouse", 0, 2, ps2_mouse_save, ps2_mouse_load, s);

    qemu_add_mouse_event_handler(ps2_mouse_event, s, 0, "QEMU PS/2 Mouse");

    return s;

}

    s->timer_irq = timer;

    s->jazz_bus_irq = jazz_bus;

    register_savevm("rc4030", 0, 2, rc4030_save, rc4030_load, s);

    rc4030_reset(s);

    s->pci_dev = (PCIDevice *)d;

    qdev_get_macaddr(&dev->qdev, s->macaddr);

    rtl8139_reset(s);

    s->vc = qdev_get_vlan_client(&dev->qdev,

                                 rtl8139_can_receive, rtl8139_receive, NULL,

    cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory);

    register_savevm("sbi", addr, 1, sbi_save, sbi_load, s);

    *irq = qemu_allocate_irqs(sbi_set_irq, s, 32);

    *cpu_irq = qemu_allocate_irqs(sbi_set_timer_irq_cpu, s, MAX_CPUS);

    sbi_reset(s);

    s->fifo_timeout_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);

    s->transmit_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_xmit, s);

    serial_reset(s);

    qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,

    register_savevm("slavio_intctl", addr, 1, slavio_intctl_save,

                    slavio_intctl_load, s);

    *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);

    *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);

    register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,

                    s);

    slavio_misc_reset(s);

    return s;

                                     slavio_timer_io_memory);

    register_savevm("slavio_timer", addr, 3, slavio_timer_save,

                    slavio_timer_load, s);

    slavio_timer_reset(s);

    return s;

    cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory);

    register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);

    *dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);

    *reset = &s->dev_reset;

    register_savevm("sun4c_intctl", addr, 1, sun4c_intctl_save,

                    sun4c_intctl_load, s);

    *irq = qemu_allocate_irqs(sun4c_set_irq, s, 8);

    sun4c_intctl_reset(s);

        cpu_sparc_set_id(env, i);

        envs[i] = env;

        if (i == 0) {

        } else {

            env->halted = 1;

        }

        cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);

        cpu_sparc_set_id(env, i);

        envs[i] = env;

        if (i == 0) {

        } else {

            env->halted = 1;

        }

        cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);

    cpu_sparc_set_id(env, 0);

    cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);

    env->prom_addr = hwdef->slavio_base;

    reset_info = qemu_mallocz(sizeof(ResetData));

    reset_info->env = env;

    reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;

    main_cpu_reset(reset_info);

    // Override warm reset address with cold start address

    env->pc = hwdef->prom_addr + 0x20ULL;

    proxy->id = ((uint32_t)0x1af4 << 16) | vdev->device_id;

    virtio_bind_device(vdev, &syborg_virtio_bindings, proxy);

}

                                 dummy_memory);

    register_savevm("tcx", addr, 4, tcx_save, tcx_load, s);

    tcx_reset(s);

    qemu_console_resize(s->ds, width, height);

}

    qemu_add_mouse_event_handler(tsc2005_touchscreen_event, s, 1,

                    "QEMU TSC2005-driven Touchscreen");

    register_savevm("tsc2005", -1, 0, tsc2005_save, tsc2005_load, s);

    return s;

    AUD_register_card(s->name, &s->card);

    register_savevm(s->name, -1, 0,

                    tsc210x_save, tsc210x_load, s);

    AUD_register_card(s->name, &s->card);

    register_savevm(s->name, -1, 0, tsc210x_save, tsc210x_load, s);

    return &s->chip;

    d->config[0x34] = 0x00; // capabilities_pointer

#endif

    register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, d);

    pci_unin_reset(d);

    return s->bus;

    }

    ohci->async_td = 0;

    ohci_reset(ohci);

}

    }

    s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s);

    uhci_reset(s);

    /* Use region 4 for consistency with real hardware.  BSD guests seem

    }

    s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s);

    uhci_reset(s);

    /* Use region 4 for consistency with real hardware.  BSD guests seem

{

    int vga_io_memory;

    register_savevm("vga", 0, 2, vga_save, vga_load, s);

    register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);

    pci_register_bar(&proxy->pci_dev, 0, size, PCI_ADDRESS_SPACE_IO,

                           virtio_map);

    virtio_bind_device(vdev, &virtio_pci_bindings, proxy);

}

    ret = kvm_arch_init_vcpu(env);

    if (ret == 0) {

        ret = kvm_arch_put_registers(env);

    }

err:

typedef struct QEMUResetEntry {

    QEMUResetHandler *func;

    void *opaque;

    struct QEMUResetEntry *next;

} QEMUResetEntry;

    }

}

{

    QEMUResetEntry **pre, *re;

    pre = &first_reset_entry;

        pre = &(*pre)->next;

    re = qemu_mallocz(sizeof(QEMUResetEntry));

    re->func = func;

    re->opaque = opaque;

    re->next = NULL;

    *pre = re;

}