Revision a08d4367 hw/ppc4xx_devs.c

b/hw/ppc4xx_devs.c
60 60 
    tb_clk->opaque = env;
61 61 
    ppc_dcr_init(env, NULL, NULL);
62 62 
    /* Register qemu callbacks */
63 
    qemu_register_reset(&cpu_ppc_reset, 0, env);
63 
    qemu_register_reset(&cpu_ppc_reset, env);
64 64 

  		





  65
  65
  
    
    return env;


  		





  66
  66
  
    
}


  		





  ......




  498
  498
  
    
        ppc_dcr_register(env, dcr_base + i, uic,


  		





  499
  499
  
    
                         &dcr_read_uic, &dcr_write_uic);


  		





  500
  500
  
    
    }


  		





  501
  
  
    
    qemu_register_reset(ppcuic_reset, 0, uic);


  		





  
  501
  
    
    qemu_register_reset(ppcuic_reset, uic);


  		





  502
  502
  
    
    ppcuic_reset(uic);


  		





  503
  503
  
    

  		





  504
  504
  
    
    return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);


  		





  ......




  834
  834
  
    
    memcpy(sdram->ram_sizes, ram_sizes,


  		





  835
  835
  
    
           nbanks * sizeof(target_phys_addr_t));


  		





  836
  836
  
    
    sdram_reset(sdram);


  		





  837
  
  
    
    qemu_register_reset(&sdram_reset, 0, sdram);


  		





  
  837
  
    
    qemu_register_reset(&sdram_reset, sdram);


  		





  838
  838
  
    
    ppc_dcr_register(env, SDRAM0_CFGADDR,


  		





  839
  839
  
    
                     sdram, &dcr_read_sdram, &dcr_write_sdram);


  		





  840
  840
  
    
    ppc_dcr_register(env, SDRAM0_CFGDATA,


  		












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