Archipelago » qemu

arm: add dummy gic security registers

Implement handling for the RAZ/WI gic security registers.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

hw/arm_gic: Expose GIC CPU interfaces as sysbus memory regions

Expose the ARM GIC CPU interfaces as memory regions, rather than
just providing read and write functions for them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

hw/arm_gic.c: Ignore attempts to complete nonexistent IRQs

Ignore attempts to complete non-existent IRQs; this fixes a buffer
overrun if the guest writes a bad value to the GICC_EOIR register.
(This case is UNPREDICTABLE so ignoring it is a valid choice.)...

hw/arm_gic.c: Fix save/load of irq_target array

irq_target array saving/loading is in the wrong loop.
Version bump.

Signed-off-by: Dmitry Koshelev <karaghiozis@gmail.com>
Acked-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>

Correct spelling of licensed

Correct typos of "licenced" to "licensed".

Reviewed-by: Stefan Weil <weil@mail.berlios.de>
Reviewed-by: Andreas F=E4rber <andreas.faerber@web.de>
Signed-off-by: Matthew Fernandez <matthew.fernandez@gmail.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>

Add endianness as io mem parameter

As stated before, devices can be little, big or native endian. The
target endianness is not of their concern, so we need to push things
down a level.

This patch adds a parameter to cpu_register_io_memory that allows a
device to choose its endianness. For now, all devices simply choose...

ARM PBX-A9 board support

Implement ARM RealView PBX-A9 board support.

Signed-off-by: Paul Brook <paul@codesourcery.com>

Revert "Get rid of _t suffix"

In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem. Something
like this must be presented on the list first so people can provide input...

Make CPURead/WriteFunc structure 'const'

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>

Remove qdev irq sink handling

We have both IRQ sinks and GPIO inputs. These are in principle exactly
the same thing, so remove the former.

Signed-off-by: Paul Brook <paul@codesourcery.com>

Replace gcc variadic macro extension with C99 version

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>

arm: Fix gic_irq_state.level bitfield type

Found while cleaning up compiler warnings: GIC_*_LEVEL macros strongly
suggest that gic_irq_state.level is intended to be per-CPU and not just
a single, global bit. I'm unable to test the effect, but it seems to be...

Change MMIO callbacks to use offsets, not absolute addresses.

Signed-off-by: Paul Brook <paul@codesourcery.com>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5849 c046a42c-6fe2-441c-8c8c-71466251a162

Force correct evaluation order in a a == b != c condition.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4358 c046a42c-6fe2-441c-8c8c-71466251a162

ARMv7 support.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3572 c046a42c-6fe2-441c-8c8c-71466251a162

arm_gic.c error message fix, by Adam Lackorzynski.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3153 c046a42c-6fe2-441c-8c8c-71466251a162

Unify IRQ handling.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2635 c046a42c-6fe2-441c-8c8c-71466251a162

ARM GIC bug.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2187 c046a42c-6fe2-441c-8c8c-71466251a162