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1
/*
2
 *  PowerPC emulation helpers for qemu.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
16
 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
 */
20
#include <stdarg.h>
21
#include <stdlib.h>
22
#include <stdio.h>
23
#include <string.h>
24
#include <inttypes.h>
25
#include <signal.h>
26
#include <assert.h>
27

    
28
#include "cpu.h"
29
#include "exec-all.h"
30

    
31
//#define DEBUG_MMU
32
//#define DEBUG_BATS
33
//#define DEBUG_SOFTWARE_TLB
34
//#define DEBUG_EXCEPTIONS
35
//#define FLUSH_ALL_TLBS
36

    
37
/*****************************************************************************/
38
/* PowerPC MMU emulation */
39

    
40
#if defined(CONFIG_USER_ONLY)
41
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
42
                              int mmu_idx, int is_softmmu)
43
{
44
    int exception, error_code;
45

    
46
    if (rw == 2) {
47
        exception = POWERPC_EXCP_ISI;
48
        error_code = 0x40000000;
49
    } else {
50
        exception = POWERPC_EXCP_DSI;
51
        error_code = 0x40000000;
52
        if (rw)
53
            error_code |= 0x02000000;
54
        env->spr[SPR_DAR] = address;
55
        env->spr[SPR_DSISR] = error_code;
56
    }
57
    env->exception_index = exception;
58
    env->error_code = error_code;
59

    
60
    return 1;
61
}
62

    
63
target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
64
{
65
    return addr;
66
}
67

    
68
#else
69
/* Common routines used by software and hardware TLBs emulation */
70
static always_inline int pte_is_valid (target_ulong pte0)
71
{
72
    return pte0 & 0x80000000 ? 1 : 0;
73
}
74

    
75
static always_inline void pte_invalidate (target_ulong *pte0)
76
{
77
    *pte0 &= ~0x80000000;
78
}
79

    
80
#if defined(TARGET_PPC64)
81
static always_inline int pte64_is_valid (target_ulong pte0)
82
{
83
    return pte0 & 0x0000000000000001ULL ? 1 : 0;
84
}
85

    
86
static always_inline void pte64_invalidate (target_ulong *pte0)
87
{
88
    *pte0 &= ~0x0000000000000001ULL;
89
}
90
#endif
91

    
92
#define PTE_PTEM_MASK 0x7FFFFFBF
93
#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
94
#if defined(TARGET_PPC64)
95
#define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
96
#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
97
#endif
98

    
99
static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
100
                                     target_ulong pte0, target_ulong pte1,
101
                                     int h, int rw)
102
{
103
    target_ulong ptem, mmask;
104
    int access, ret, pteh, ptev;
105

    
106
    access = 0;
107
    ret = -1;
108
    /* Check validity and table match */
109
#if defined(TARGET_PPC64)
110
    if (is_64b) {
111
        ptev = pte64_is_valid(pte0);
112
        pteh = (pte0 >> 1) & 1;
113
    } else
114
#endif
115
    {
116
        ptev = pte_is_valid(pte0);
117
        pteh = (pte0 >> 6) & 1;
118
    }
119
    if (ptev && h == pteh) {
120
        /* Check vsid & api */
121
#if defined(TARGET_PPC64)
122
        if (is_64b) {
123
            ptem = pte0 & PTE64_PTEM_MASK;
124
            mmask = PTE64_CHECK_MASK;
125
        } else
126
#endif
127
        {
128
            ptem = pte0 & PTE_PTEM_MASK;
129
            mmask = PTE_CHECK_MASK;
130
        }
131
        if (ptem == ctx->ptem) {
132
            if (ctx->raddr != (target_ulong)-1) {
133
                /* all matches should have equal RPN, WIMG & PP */
134
                if ((ctx->raddr & mmask) != (pte1 & mmask)) {
135
                    if (loglevel != 0)
136
                        fprintf(logfile, "Bad RPN/WIMG/PP\n");
137
                    return -3;
138
                }
139
            }
140
            /* Compute access rights */
141
            if (ctx->key == 0) {
142
                access = PAGE_READ;
143
                if ((pte1 & 0x00000003) != 0x3)
144
                    access |= PAGE_WRITE;
145
            } else {
146
                switch (pte1 & 0x00000003) {
147
                case 0x0:
148
                    access = 0;
149
                    break;
150
                case 0x1:
151
                case 0x3:
152
                    access = PAGE_READ;
153
                    break;
154
                case 0x2:
155
                    access = PAGE_READ | PAGE_WRITE;
156
                    break;
157
                }
158
            }
159
            /* Keep the matching PTE informations */
160
            ctx->raddr = pte1;
161
            ctx->prot = access;
162
            if ((rw == 0 && (access & PAGE_READ)) ||
163
                (rw == 1 && (access & PAGE_WRITE))) {
164
                /* Access granted */
165
#if defined (DEBUG_MMU)
166
                if (loglevel != 0)
167
                    fprintf(logfile, "PTE access granted !\n");
168
#endif
169
                ret = 0;
170
            } else {
171
                /* Access right violation */
172
#if defined (DEBUG_MMU)
173
                if (loglevel != 0)
174
                    fprintf(logfile, "PTE access rejected\n");
175
#endif
176
                ret = -2;
177
            }
178
        }
179
    }
180

    
181
    return ret;
182
}
183

    
184
static int pte32_check (mmu_ctx_t *ctx,
185
                        target_ulong pte0, target_ulong pte1, int h, int rw)
186
{
187
    return _pte_check(ctx, 0, pte0, pte1, h, rw);
188
}
189

    
190
#if defined(TARGET_PPC64)
191
static int pte64_check (mmu_ctx_t *ctx,
192
                        target_ulong pte0, target_ulong pte1, int h, int rw)
193
{
194
    return _pte_check(ctx, 1, pte0, pte1, h, rw);
195
}
196
#endif
197

    
198
static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
199
                             int ret, int rw)
200
{
201
    int store = 0;
202

    
203
    /* Update page flags */
204
    if (!(*pte1p & 0x00000100)) {
205
        /* Update accessed flag */
206
        *pte1p |= 0x00000100;
207
        store = 1;
208
    }
209
    if (!(*pte1p & 0x00000080)) {
210
        if (rw == 1 && ret == 0) {
211
            /* Update changed flag */
212
            *pte1p |= 0x00000080;
213
            store = 1;
214
        } else {
215
            /* Force page fault for first write access */
216
            ctx->prot &= ~PAGE_WRITE;
217
        }
218
    }
219

    
220
    return store;
221
}
222

    
223
/* Software driven TLB helpers */
224
static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
225
                              int way, int is_code)
226
{
227
    int nr;
228

    
229
    /* Select TLB num in a way from address */
230
    nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
231
    /* Select TLB way */
232
    nr += env->tlb_per_way * way;
233
    /* 6xx have separate TLBs for instructions and data */
234
    if (is_code && env->id_tlbs == 1)
235
        nr += env->nb_tlb;
236

    
237
    return nr;
238
}
239

    
240
static void ppc6xx_tlb_invalidate_all (CPUState *env)
241
{
242
    ppc6xx_tlb_t *tlb;
243
    int nr, max;
244

    
245
#if defined (DEBUG_SOFTWARE_TLB) && 0
246
    if (loglevel != 0) {
247
        fprintf(logfile, "Invalidate all TLBs\n");
248
    }
249
#endif
250
    /* Invalidate all defined software TLB */
251
    max = env->nb_tlb;
252
    if (env->id_tlbs == 1)
253
        max *= 2;
254
    for (nr = 0; nr < max; nr++) {
255
        tlb = &env->tlb[nr].tlb6;
256
        pte_invalidate(&tlb->pte0);
257
    }
258
    tlb_flush(env, 1);
259
}
260

    
261
static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
262
                                                        target_ulong eaddr,
263
                                                        int is_code,
264
                                                        int match_epn)
265
{
266
#if !defined(FLUSH_ALL_TLBS)
267
    ppc6xx_tlb_t *tlb;
268
    int way, nr;
269

    
270
    /* Invalidate ITLB + DTLB, all ways */
271
    for (way = 0; way < env->nb_ways; way++) {
272
        nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
273
        tlb = &env->tlb[nr].tlb6;
274
        if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
275
#if defined (DEBUG_SOFTWARE_TLB)
276
            if (loglevel != 0) {
277
                fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
278
                        nr, env->nb_tlb, eaddr);
279
            }
280
#endif
281
            pte_invalidate(&tlb->pte0);
282
            tlb_flush_page(env, tlb->EPN);
283
        }
284
    }
285
#else
286
    /* XXX: PowerPC specification say this is valid as well */
287
    ppc6xx_tlb_invalidate_all(env);
288
#endif
289
}
290

    
291
static void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
292
                                        int is_code)
293
{
294
    __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
295
}
296

    
297
void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
298
                       target_ulong pte0, target_ulong pte1)
299
{
300
    ppc6xx_tlb_t *tlb;
301
    int nr;
302

    
303
    nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
304
    tlb = &env->tlb[nr].tlb6;
305
#if defined (DEBUG_SOFTWARE_TLB)
306
    if (loglevel != 0) {
307
        fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
308
                " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
309
    }
310
#endif
311
    /* Invalidate any pending reference in Qemu for this virtual address */
312
    __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
313
    tlb->pte0 = pte0;
314
    tlb->pte1 = pte1;
315
    tlb->EPN = EPN;
316
    /* Store last way for LRU mechanism */
317
    env->last_way = way;
318
}
319

    
320
static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
321
                             target_ulong eaddr, int rw, int access_type)
322
{
323
    ppc6xx_tlb_t *tlb;
324
    int nr, best, way;
325
    int ret;
326

    
327
    best = -1;
328
    ret = -1; /* No TLB found */
329
    for (way = 0; way < env->nb_ways; way++) {
330
        nr = ppc6xx_tlb_getnum(env, eaddr, way,
331
                               access_type == ACCESS_CODE ? 1 : 0);
332
        tlb = &env->tlb[nr].tlb6;
333
        /* This test "emulates" the PTE index match for hardware TLBs */
334
        if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
335
#if defined (DEBUG_SOFTWARE_TLB)
336
            if (loglevel != 0) {
337
                fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
338
                        "] <> " ADDRX "\n",
339
                        nr, env->nb_tlb,
340
                        pte_is_valid(tlb->pte0) ? "valid" : "inval",
341
                        tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
342
            }
343
#endif
344
            continue;
345
        }
346
#if defined (DEBUG_SOFTWARE_TLB)
347
        if (loglevel != 0) {
348
            fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
349
                    " %c %c\n",
350
                    nr, env->nb_tlb,
351
                    pte_is_valid(tlb->pte0) ? "valid" : "inval",
352
                    tlb->EPN, eaddr, tlb->pte1,
353
                    rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
354
        }
355
#endif
356
        switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {
357
        case -3:
358
            /* TLB inconsistency */
359
            return -1;
360
        case -2:
361
            /* Access violation */
362
            ret = -2;
363
            best = nr;
364
            break;
365
        case -1:
366
        default:
367
            /* No match */
368
            break;
369
        case 0:
370
            /* access granted */
371
            /* XXX: we should go on looping to check all TLBs consistency
372
             *      but we can speed-up the whole thing as the
373
             *      result would be undefined if TLBs are not consistent.
374
             */
375
            ret = 0;
376
            best = nr;
377
            goto done;
378
        }
379
    }
380
    if (best != -1) {
381
    done:
382
#if defined (DEBUG_SOFTWARE_TLB)
383
        if (loglevel != 0) {
384
            fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
385
                    ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
386
        }
387
#endif
388
        /* Update page flags */
389
        pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
390
    }
391

    
392
    return ret;
393
}
394

    
395
/* Perform BAT hit & translation */
396
static int get_bat (CPUState *env, mmu_ctx_t *ctx,
397
                    target_ulong virtual, int rw, int type)
398
{
399
    target_ulong *BATlt, *BATut, *BATu, *BATl;
400
    target_ulong base, BEPIl, BEPIu, bl;
401
    int i;
402
    int ret = -1;
403

    
404
#if defined (DEBUG_BATS)
405
    if (loglevel != 0) {
406
        fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
407
                type == ACCESS_CODE ? 'I' : 'D', virtual);
408
    }
409
#endif
410
    switch (type) {
411
    case ACCESS_CODE:
412
        BATlt = env->IBAT[1];
413
        BATut = env->IBAT[0];
414
        break;
415
    default:
416
        BATlt = env->DBAT[1];
417
        BATut = env->DBAT[0];
418
        break;
419
    }
420
#if defined (DEBUG_BATS)
421
    if (loglevel != 0) {
422
        fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
423
                type == ACCESS_CODE ? 'I' : 'D', virtual);
424
    }
425
#endif
426
    base = virtual & 0xFFFC0000;
427
    for (i = 0; i < 4; i++) {
428
        BATu = &BATut[i];
429
        BATl = &BATlt[i];
430
        BEPIu = *BATu & 0xF0000000;
431
        BEPIl = *BATu & 0x0FFE0000;
432
        bl = (*BATu & 0x00001FFC) << 15;
433
#if defined (DEBUG_BATS)
434
        if (loglevel != 0) {
435
            fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
436
                    " BATl 0x" ADDRX "\n",
437
                    __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
438
                    *BATu, *BATl);
439
        }
440
#endif
441
        if ((virtual & 0xF0000000) == BEPIu &&
442
            ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
443
            /* BAT matches */
444
            if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
445
                (msr_pr == 1 && (*BATu & 0x00000001))) {
446
                /* Get physical address */
447
                ctx->raddr = (*BATl & 0xF0000000) |
448
                    ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
449
                    (virtual & 0x0001F000);
450
                if (*BATl & 0x00000001)
451
                    ctx->prot = PAGE_READ;
452
                if (*BATl & 0x00000002)
453
                    ctx->prot = PAGE_WRITE | PAGE_READ;
454
#if defined (DEBUG_BATS)
455
                if (loglevel != 0) {
456
                    fprintf(logfile, "BAT %d match: r 0x" PADDRX
457
                            " prot=%c%c\n",
458
                            i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
459
                            ctx->prot & PAGE_WRITE ? 'W' : '-');
460
                }
461
#endif
462
                ret = 0;
463
                break;
464
            }
465
        }
466
    }
467
    if (ret < 0) {
468
#if defined (DEBUG_BATS)
469
        if (loglevel != 0) {
470
            fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual);
471
            for (i = 0; i < 4; i++) {
472
                BATu = &BATut[i];
473
                BATl = &BATlt[i];
474
                BEPIu = *BATu & 0xF0000000;
475
                BEPIl = *BATu & 0x0FFE0000;
476
                bl = (*BATu & 0x00001FFC) << 15;
477
                fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
478
                        " BATl 0x" ADDRX " \n\t"
479
                        "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
480
                        __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
481
                        *BATu, *BATl, BEPIu, BEPIl, bl);
482
            }
483
        }
484
#endif
485
    }
486
    /* No hit */
487
    return ret;
488
}
489

    
490
/* PTE table lookup */
491
static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, int rw)
492
{
493
    target_ulong base, pte0, pte1;
494
    int i, good = -1;
495
    int ret, r;
496

    
497
    ret = -1; /* No entry found */
498
    base = ctx->pg_addr[h];
499
    for (i = 0; i < 8; i++) {
500
#if defined(TARGET_PPC64)
501
        if (is_64b) {
502
            pte0 = ldq_phys(base + (i * 16));
503
            pte1 =  ldq_phys(base + (i * 16) + 8);
504
            r = pte64_check(ctx, pte0, pte1, h, rw);
505
#if defined (DEBUG_MMU)
506
            if (loglevel != 0) {
507
                fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
508
                        " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
509
                        base + (i * 16), pte0, pte1,
510
                        (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1),
511
                        ctx->ptem);
512
            }
513
#endif
514
        } else
515
#endif
516
        {
517
            pte0 = ldl_phys(base + (i * 8));
518
            pte1 =  ldl_phys(base + (i * 8) + 4);
519
            r = pte32_check(ctx, pte0, pte1, h, rw);
520
#if defined (DEBUG_MMU)
521
            if (loglevel != 0) {
522
                fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
523
                        " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
524
                        base + (i * 8), pte0, pte1,
525
                        (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1),
526
                        ctx->ptem);
527
            }
528
#endif
529
        }
530
        switch (r) {
531
        case -3:
532
            /* PTE inconsistency */
533
            return -1;
534
        case -2:
535
            /* Access violation */
536
            ret = -2;
537
            good = i;
538
            break;
539
        case -1:
540
        default:
541
            /* No PTE match */
542
            break;
543
        case 0:
544
            /* access granted */
545
            /* XXX: we should go on looping to check all PTEs consistency
546
             *      but if we can speed-up the whole thing as the
547
             *      result would be undefined if PTEs are not consistent.
548
             */
549
            ret = 0;
550
            good = i;
551
            goto done;
552
        }
553
    }
554
    if (good != -1) {
555
    done:
556
#if defined (DEBUG_MMU)
557
        if (loglevel != 0) {
558
            fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x "
559
                    "ret=%d\n",
560
                    ctx->raddr, ctx->prot, ret);
561
        }
562
#endif
563
        /* Update page flags */
564
        pte1 = ctx->raddr;
565
        if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
566
#if defined(TARGET_PPC64)
567
            if (is_64b) {
568
                stq_phys_notdirty(base + (good * 16) + 8, pte1);
569
            } else
570
#endif
571
            {
572
                stl_phys_notdirty(base + (good * 8) + 4, pte1);
573
            }
574
        }
575
    }
576

    
577
    return ret;
578
}
579

    
580
static int find_pte32 (mmu_ctx_t *ctx, int h, int rw)
581
{
582
    return _find_pte(ctx, 0, h, rw);
583
}
584

    
585
#if defined(TARGET_PPC64)
586
static int find_pte64 (mmu_ctx_t *ctx, int h, int rw)
587
{
588
    return _find_pte(ctx, 1, h, rw);
589
}
590
#endif
591

    
592
static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx,
593
                                   int h, int rw)
594
{
595
#if defined(TARGET_PPC64)
596
    if (env->mmu_model == POWERPC_MMU_64B)
597
        return find_pte64(ctx, h, rw);
598
#endif
599

    
600
    return find_pte32(ctx, h, rw);
601
}
602

    
603
#if defined(TARGET_PPC64)
604
static inline int slb_is_valid (uint64_t slb64)
605
{
606
    return slb64 & 0x0000000008000000ULL ? 1 : 0;
607
}
608

    
609
static inline void slb_invalidate (uint64_t *slb64)
610
{
611
    *slb64 &= ~0x0000000008000000ULL;
612
}
613

    
614
static int slb_lookup (CPUPPCState *env, target_ulong eaddr,
615
                       target_ulong *vsid, target_ulong *page_mask, int *attr)
616
{
617
    target_phys_addr_t sr_base;
618
    target_ulong mask;
619
    uint64_t tmp64;
620
    uint32_t tmp;
621
    int n, ret;
622

    
623
    ret = -5;
624
    sr_base = env->spr[SPR_ASR];
625
#if defined(DEBUG_SLB)
626
    if (loglevel != 0) {
627
        fprintf(logfile, "%s: eaddr " ADDRX " base " PADDRX "\n",
628
                __func__, eaddr, sr_base);
629
    }
630
#endif
631
    mask = 0x0000000000000000ULL; /* Avoid gcc warning */
632
    for (n = 0; n < env->slb_nr; n++) {
633
        tmp64 = ldq_phys(sr_base);
634
        tmp = ldl_phys(sr_base + 8);
635
#if defined(DEBUG_SLB)
636
        if (loglevel != 0) {
637
            fprintf(logfile, "%s: seg %d " PADDRX " %016" PRIx64 " %08"
638
                    PRIx32 "\n", __func__, n, sr_base, tmp64, tmp);
639
        }
640
#endif
641
        if (slb_is_valid(tmp64)) {
642
            /* SLB entry is valid */
643
            switch (tmp64 & 0x0000000006000000ULL) {
644
            case 0x0000000000000000ULL:
645
                /* 256 MB segment */
646
                mask = 0xFFFFFFFFF0000000ULL;
647
                break;
648
            case 0x0000000002000000ULL:
649
                /* 1 TB segment */
650
                mask = 0xFFFF000000000000ULL;
651
                break;
652
            case 0x0000000004000000ULL:
653
            case 0x0000000006000000ULL:
654
                /* Reserved => segment is invalid */
655
                continue;
656
            }
657
            if ((eaddr & mask) == (tmp64 & mask)) {
658
                /* SLB match */
659
                *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
660
                *page_mask = ~mask;
661
                *attr = tmp & 0xFF;
662
                ret = n;
663
                break;
664
            }
665
        }
666
        sr_base += 12;
667
    }
668

    
669
    return ret;
670
}
671

    
672
void ppc_slb_invalidate_all (CPUPPCState *env)
673
{
674
    target_phys_addr_t sr_base;
675
    uint64_t tmp64;
676
    int n, do_invalidate;
677

    
678
    do_invalidate = 0;
679
    sr_base = env->spr[SPR_ASR];
680
    for (n = 0; n < env->slb_nr; n++) {
681
        tmp64 = ldq_phys(sr_base);
682
        if (slb_is_valid(tmp64)) {
683
            slb_invalidate(&tmp64);
684
            stq_phys(sr_base, tmp64);
685
            /* XXX: given the fact that segment size is 256 MB or 1TB,
686
             *      and we still don't have a tlb_flush_mask(env, n, mask)
687
             *      in Qemu, we just invalidate all TLBs
688
             */
689
            do_invalidate = 1;
690
        }
691
        sr_base += 12;
692
    }
693
    if (do_invalidate)
694
        tlb_flush(env, 1);
695
}
696

    
697
void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
698
{
699
    target_phys_addr_t sr_base;
700
    target_ulong vsid, page_mask;
701
    uint64_t tmp64;
702
    int attr;
703
    int n;
704

    
705
    n = slb_lookup(env, T0, &vsid, &page_mask, &attr);
706
    if (n >= 0) {
707
        sr_base = env->spr[SPR_ASR];
708
        sr_base += 12 * n;
709
        tmp64 = ldq_phys(sr_base);
710
        if (slb_is_valid(tmp64)) {
711
            slb_invalidate(&tmp64);
712
            stq_phys(sr_base, tmp64);
713
            /* XXX: given the fact that segment size is 256 MB or 1TB,
714
             *      and we still don't have a tlb_flush_mask(env, n, mask)
715
             *      in Qemu, we just invalidate all TLBs
716
             */
717
            tlb_flush(env, 1);
718
        }
719
    }
720
}
721

    
722
target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
723
{
724
    target_phys_addr_t sr_base;
725
    target_ulong rt;
726
    uint64_t tmp64;
727
    uint32_t tmp;
728

    
729
    sr_base = env->spr[SPR_ASR];
730
    sr_base += 12 * slb_nr;
731
    tmp64 = ldq_phys(sr_base);
732
    tmp = ldl_phys(sr_base + 8);
733
    if (tmp64 & 0x0000000008000000ULL) {
734
        /* SLB entry is valid */
735
        /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
736
        rt = tmp >> 8;             /* 65:88 => 40:63 */
737
        rt |= (tmp64 & 0x7) << 24; /* 62:64 => 37:39 */
738
        /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
739
        rt |= ((tmp >> 4) & 0xF) << 27;
740
    } else {
741
        rt = 0;
742
    }
743
#if defined(DEBUG_SLB)
744
    if (loglevel != 0) {
745
        fprintf(logfile, "%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d "
746
                ADDRX "\n", __func__, sr_base, tmp64, tmp, slb_nr, rt);
747
    }
748
#endif
749

    
750
    return rt;
751
}
752

    
753
void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs)
754
{
755
    target_phys_addr_t sr_base;
756
    uint64_t tmp64;
757
    uint32_t tmp;
758

    
759
    sr_base = env->spr[SPR_ASR];
760
    sr_base += 12 * slb_nr;
761
    /* Copy Rs bits 37:63 to SLB 62:88 */
762
    tmp = rs << 8;
763
    tmp64 = (rs >> 24) & 0x7;
764
    /* Copy Rs bits 33:36 to SLB 89:92 */
765
    tmp |= ((rs >> 27) & 0xF) << 4;
766
    /* Set the valid bit */
767
    tmp64 |= 1 << 27;
768
    /* Set ESID */
769
    tmp64 |= (uint32_t)slb_nr << 28;
770
#if defined(DEBUG_SLB)
771
    if (loglevel != 0) {
772
        fprintf(logfile, "%s: %d " ADDRX " => " PADDRX " %016" PRIx64 " %08"
773
                PRIx32 "\n", __func__, slb_nr, rs, sr_base, tmp64, tmp);
774
    }
775
#endif
776
    /* Write SLB entry to memory */
777
    stq_phys(sr_base, tmp64);
778
    stl_phys(sr_base + 8, tmp);
779
}
780
#endif /* defined(TARGET_PPC64) */
781

    
782
/* Perform segment based translation */
783
static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
784
                                                    int sdr_sh,
785
                                                    target_phys_addr_t hash,
786
                                                    target_phys_addr_t mask)
787
{
788
    return (sdr1 & ((target_ulong)(-1ULL) << sdr_sh)) | (hash & mask);
789
}
790

    
791
static int get_segment (CPUState *env, mmu_ctx_t *ctx,
792
                        target_ulong eaddr, int rw, int type)
793
{
794
    target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;
795
    target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
796
#if defined(TARGET_PPC64)
797
    int attr;
798
#endif
799
    int ds, nx, vsid_sh, sdr_sh;
800
    int ret, ret2;
801

    
802
#if defined(TARGET_PPC64)
803
    if (env->mmu_model == POWERPC_MMU_64B) {
804
#if defined (DEBUG_MMU)
805
        if (loglevel != 0) {
806
            fprintf(logfile, "Check SLBs\n");
807
        }
808
#endif
809
        ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr);
810
        if (ret < 0)
811
            return ret;
812
        ctx->key = ((attr & 0x40) && msr_pr == 1) ||
813
            ((attr & 0x80) && msr_pr == 0) ? 1 : 0;
814
        ds = 0;
815
        nx = attr & 0x20 ? 1 : 0;
816
        vsid_mask = 0x00003FFFFFFFFF80ULL;
817
        vsid_sh = 7;
818
        sdr_sh = 18;
819
        sdr_mask = 0x3FF80;
820
    } else
821
#endif /* defined(TARGET_PPC64) */
822
    {
823
        sr = env->sr[eaddr >> 28];
824
        page_mask = 0x0FFFFFFF;
825
        ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
826
                    ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
827
        ds = sr & 0x80000000 ? 1 : 0;
828
        nx = sr & 0x10000000 ? 1 : 0;
829
        vsid = sr & 0x00FFFFFF;
830
        vsid_mask = 0x01FFFFC0;
831
        vsid_sh = 6;
832
        sdr_sh = 16;
833
        sdr_mask = 0xFFC0;
834
#if defined (DEBUG_MMU)
835
        if (loglevel != 0) {
836
            fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX
837
                    " nip=0x" ADDRX " lr=0x" ADDRX
838
                    " ir=%d dr=%d pr=%d %d t=%d\n",
839
                    eaddr, (int)(eaddr >> 28), sr, env->nip,
840
                    env->lr, msr_ir, msr_dr, msr_pr, rw, type);
841
        }
842
#endif
843
    }
844
#if defined (DEBUG_MMU)
845
    if (loglevel != 0) {
846
        fprintf(logfile, "pte segment: key=%d ds %d nx %d vsid " ADDRX "\n",
847
                ctx->key, ds, nx, vsid);
848
    }
849
#endif
850
    ret = -1;
851
    if (!ds) {
852
        /* Check if instruction fetch is allowed, if needed */
853
        if (type != ACCESS_CODE || nx == 0) {
854
            /* Page address translation */
855
            /* Primary table address */
856
            sdr = env->sdr1;
857
            pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS;
858
#if defined(TARGET_PPC64)
859
            if (env->mmu_model == POWERPC_MMU_64B) {
860
                htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F));
861
                /* XXX: this is false for 1 TB segments */
862
                hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
863
            } else
864
#endif
865
            {
866
                htab_mask = sdr & 0x000001FF;
867
                hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
868
            }
869
            mask = (htab_mask << sdr_sh) | sdr_mask;
870
#if defined (DEBUG_MMU)
871
            if (loglevel != 0) {
872
                fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX " mask "
873
                        PADDRX " " ADDRX "\n", sdr, sdr_sh, hash, mask,
874
                        page_mask);
875
            }
876
#endif
877
            ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
878
            /* Secondary table address */
879
            hash = (~hash) & vsid_mask;
880
#if defined (DEBUG_MMU)
881
            if (loglevel != 0) {
882
                fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX " mask "
883
                        PADDRX "\n", sdr, sdr_sh, hash, mask);
884
            }
885
#endif
886
            ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
887
#if defined(TARGET_PPC64)
888
            if (env->mmu_model == POWERPC_MMU_64B) {
889
                /* Only 5 bits of the page index are used in the AVPN */
890
                ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
891
            } else
892
#endif
893
            {
894
                ctx->ptem = (vsid << 7) | (pgidx >> 10);
895
            }
896
            /* Initialize real address with an invalid value */
897
            ctx->raddr = (target_ulong)-1;
898
            if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
899
                         env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
900
                /* Software TLB search */
901
                ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
902
            } else {
903
#if defined (DEBUG_MMU)
904
                if (loglevel != 0) {
905
                    fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x "
906
                            "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n",
907
                            sdr, (uint32_t)vsid, (uint32_t)pgidx,
908
                            (uint32_t)hash, ctx->pg_addr[0]);
909
                }
910
#endif
911
                /* Primary table lookup */
912
                ret = find_pte(env, ctx, 0, rw);
913
                if (ret < 0) {
914
                    /* Secondary table lookup */
915
#if defined (DEBUG_MMU)
916
                    if (eaddr != 0xEFFFFFFF && loglevel != 0) {
917
                        fprintf(logfile,
918
                                "1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x "
919
                                "hash=0x%05x pg_addr=0x" PADDRX "\n",
920
                                sdr, (uint32_t)vsid, (uint32_t)pgidx,
921
                                (uint32_t)hash, ctx->pg_addr[1]);
922
                    }
923
#endif
924
                    ret2 = find_pte(env, ctx, 1, rw);
925
                    if (ret2 != -1)
926
                        ret = ret2;
927
                }
928
            }
929
#if defined (DEBUG_MMU)
930
            if (loglevel != 0) {
931
                target_phys_addr_t curaddr;
932
                uint32_t a0, a1, a2, a3;
933
                fprintf(logfile,
934
                        "Page table: " PADDRX " len " PADDRX "\n",
935
                        sdr, mask + 0x80);
936
                for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
937
                     curaddr += 16) {
938
                    a0 = ldl_phys(curaddr);
939
                    a1 = ldl_phys(curaddr + 4);
940
                    a2 = ldl_phys(curaddr + 8);
941
                    a3 = ldl_phys(curaddr + 12);
942
                    if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
943
                        fprintf(logfile,
944
                                PADDRX ": %08x %08x %08x %08x\n",
945
                                curaddr, a0, a1, a2, a3);
946
                    }
947
                }
948
            }
949
#endif
950
        } else {
951
#if defined (DEBUG_MMU)
952
            if (loglevel != 0)
953
                fprintf(logfile, "No access allowed\n");
954
#endif
955
            ret = -3;
956
        }
957
    } else {
958
#if defined (DEBUG_MMU)
959
        if (loglevel != 0)
960
            fprintf(logfile, "direct store...\n");
961
#endif
962
        /* Direct-store segment : absolutely *BUGGY* for now */
963
        switch (type) {
964
        case ACCESS_INT:
965
            /* Integer load/store : only access allowed */
966
            break;
967
        case ACCESS_CODE:
968
            /* No code fetch is allowed in direct-store areas */
969
            return -4;
970
        case ACCESS_FLOAT:
971
            /* Floating point load/store */
972
            return -4;
973
        case ACCESS_RES:
974
            /* lwarx, ldarx or srwcx. */
975
            return -4;
976
        case ACCESS_CACHE:
977
            /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
978
            /* Should make the instruction do no-op.
979
             * As it already do no-op, it's quite easy :-)
980
             */
981
            ctx->raddr = eaddr;
982
            return 0;
983
        case ACCESS_EXT:
984
            /* eciwx or ecowx */
985
            return -4;
986
        default:
987
            if (logfile) {
988
                fprintf(logfile, "ERROR: instruction should not need "
989
                        "address translation\n");
990
            }
991
            return -4;
992
        }
993
        if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
994
            ctx->raddr = eaddr;
995
            ret = 2;
996
        } else {
997
            ret = -2;
998
        }
999
    }
1000

    
1001
    return ret;
1002
}
1003

    
1004
/* Generic TLB check function for embedded PowerPC implementations */
1005
static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
1006
                             target_phys_addr_t *raddrp,
1007
                             target_ulong address,
1008
                             uint32_t pid, int ext, int i)
1009
{
1010
    target_ulong mask;
1011

    
1012
    /* Check valid flag */
1013
    if (!(tlb->prot & PAGE_VALID)) {
1014
        if (loglevel != 0)
1015
            fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
1016
        return -1;
1017
    }
1018
    mask = ~(tlb->size - 1);
1019
#if defined (DEBUG_SOFTWARE_TLB)
1020
    if (loglevel != 0) {
1021
        fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
1022
                ADDRX " " ADDRX " %d\n",
1023
                __func__, i, address, pid, tlb->EPN, mask, (int)tlb->PID);
1024
    }
1025
#endif
1026
    /* Check PID */
1027
    if (tlb->PID != 0 && tlb->PID != pid)
1028
        return -1;
1029
    /* Check effective address */
1030
    if ((address & mask) != tlb->EPN)
1031
        return -1;
1032
    *raddrp = (tlb->RPN & mask) | (address & ~mask);
1033
#if (TARGET_PHYS_ADDR_BITS >= 36)
1034
    if (ext) {
1035
        /* Extend the physical address to 36 bits */
1036
        *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
1037
    }
1038
#endif
1039

    
1040
    return 0;
1041
}
1042

    
1043
/* Generic TLB search function for PowerPC embedded implementations */
1044
int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
1045
{
1046
    ppcemb_tlb_t *tlb;
1047
    target_phys_addr_t raddr;
1048
    int i, ret;
1049

    
1050
    /* Default return value is no match */
1051
    ret = -1;
1052
    for (i = 0; i < env->nb_tlb; i++) {
1053
        tlb = &env->tlb[i].tlbe;
1054
        if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
1055
            ret = i;
1056
            break;
1057
        }
1058
    }
1059

    
1060
    return ret;
1061
}
1062

    
1063
/* Helpers specific to PowerPC 40x implementations */
1064
static void ppc4xx_tlb_invalidate_all (CPUState *env)
1065
{
1066
    ppcemb_tlb_t *tlb;
1067
    int i;
1068

    
1069
    for (i = 0; i < env->nb_tlb; i++) {
1070
        tlb = &env->tlb[i].tlbe;
1071
        tlb->prot &= ~PAGE_VALID;
1072
    }
1073
    tlb_flush(env, 1);
1074
}
1075

    
1076
static void ppc4xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
1077
                                        uint32_t pid)
1078
{
1079
#if !defined(FLUSH_ALL_TLBS)
1080
    ppcemb_tlb_t *tlb;
1081
    target_phys_addr_t raddr;
1082
    target_ulong page, end;
1083
    int i;
1084

    
1085
    for (i = 0; i < env->nb_tlb; i++) {
1086
        tlb = &env->tlb[i].tlbe;
1087
        if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
1088
            end = tlb->EPN + tlb->size;
1089
            for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
1090
                tlb_flush_page(env, page);
1091
            tlb->prot &= ~PAGE_VALID;
1092
            break;
1093
        }
1094
    }
1095
#else
1096
    ppc4xx_tlb_invalidate_all(env);
1097
#endif
1098
}
1099

    
1100
int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1101
                                 target_ulong address, int rw, int access_type)
1102
{
1103
    ppcemb_tlb_t *tlb;
1104
    target_phys_addr_t raddr;
1105
    int i, ret, zsel, zpr;
1106

    
1107
    ret = -1;
1108
    raddr = -1;
1109
    for (i = 0; i < env->nb_tlb; i++) {
1110
        tlb = &env->tlb[i].tlbe;
1111
        if (ppcemb_tlb_check(env, tlb, &raddr, address,
1112
                             env->spr[SPR_40x_PID], 0, i) < 0)
1113
            continue;
1114
        zsel = (tlb->attr >> 4) & 0xF;
1115
        zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
1116
#if defined (DEBUG_SOFTWARE_TLB)
1117
        if (loglevel != 0) {
1118
            fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
1119
                    __func__, i, zsel, zpr, rw, tlb->attr);
1120
        }
1121
#endif
1122
        if (access_type == ACCESS_CODE) {
1123
            /* Check execute enable bit */
1124
            switch (zpr) {
1125
            case 0x2:
1126
                if (msr_pr)
1127
                    goto check_exec_perm;
1128
                goto exec_granted;
1129
            case 0x0:
1130
                if (msr_pr) {
1131
                    ctx->prot = 0;
1132
                    ret = -3;
1133
                    break;
1134
                }
1135
                /* No break here */
1136
            case 0x1:
1137
            check_exec_perm:
1138
                /* Check from TLB entry */
1139
                if (!(tlb->prot & PAGE_EXEC)) {
1140
                    ret = -3;
1141
                } else {
1142
                    if (tlb->prot & PAGE_WRITE) {
1143
                        ctx->prot = PAGE_READ | PAGE_WRITE;
1144
                    } else {
1145
                        ctx->prot = PAGE_READ;
1146
                    }
1147
                    ret = 0;
1148
                }
1149
                break;
1150
            case 0x3:
1151
            exec_granted:
1152
                /* All accesses granted */
1153
                ctx->prot = PAGE_READ | PAGE_WRITE;
1154
                ret = 0;
1155
                break;
1156
            }
1157
        } else {
1158
            switch (zpr) {
1159
            case 0x2:
1160
                if (msr_pr)
1161
                    goto check_rw_perm;
1162
                goto rw_granted;
1163
            case 0x0:
1164
                if (msr_pr) {
1165
                    ctx->prot = 0;
1166
                    ret = -2;
1167
                    break;
1168
                }
1169
                /* No break here */
1170
            case 0x1:
1171
            check_rw_perm:
1172
                /* Check from TLB entry */
1173
                /* Check write protection bit */
1174
                if (tlb->prot & PAGE_WRITE) {
1175
                    ctx->prot = PAGE_READ | PAGE_WRITE;
1176
                    ret = 0;
1177
                } else {
1178
                    ctx->prot = PAGE_READ;
1179
                    if (rw)
1180
                        ret = -2;
1181
                    else
1182
                        ret = 0;
1183
                }
1184
                break;
1185
            case 0x3:
1186
            rw_granted:
1187
                /* All accesses granted */
1188
                ctx->prot = PAGE_READ | PAGE_WRITE;
1189
                ret = 0;
1190
                break;
1191
            }
1192
        }
1193
        if (ret >= 0) {
1194
            ctx->raddr = raddr;
1195
#if defined (DEBUG_SOFTWARE_TLB)
1196
            if (loglevel != 0) {
1197
                fprintf(logfile, "%s: access granted " ADDRX " => " REGX
1198
                        " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
1199
                        ret);
1200
            }
1201
#endif
1202
            return 0;
1203
        }
1204
    }
1205
#if defined (DEBUG_SOFTWARE_TLB)
1206
    if (loglevel != 0) {
1207
        fprintf(logfile, "%s: access refused " ADDRX " => " REGX
1208
                " %d %d\n", __func__, address, raddr, ctx->prot,
1209
                ret);
1210
    }
1211
#endif
1212

    
1213
    return ret;
1214
}
1215

    
1216
void store_40x_sler (CPUPPCState *env, uint32_t val)
1217
{
1218
    /* XXX: TO BE FIXED */
1219
    if (val != 0x00000000) {
1220
        cpu_abort(env, "Little-endian regions are not supported by now\n");
1221
    }
1222
    env->spr[SPR_405_SLER] = val;
1223
}
1224

    
1225
int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1226
                                   target_ulong address, int rw,
1227
                                   int access_type)
1228
{
1229
    ppcemb_tlb_t *tlb;
1230
    target_phys_addr_t raddr;
1231
    int i, prot, ret;
1232

    
1233
    ret = -1;
1234
    raddr = -1;
1235
    for (i = 0; i < env->nb_tlb; i++) {
1236
        tlb = &env->tlb[i].tlbe;
1237
        if (ppcemb_tlb_check(env, tlb, &raddr, address,
1238
                             env->spr[SPR_BOOKE_PID], 1, i) < 0)
1239
            continue;
1240
        if (msr_pr)
1241
            prot = tlb->prot & 0xF;
1242
        else
1243
            prot = (tlb->prot >> 4) & 0xF;
1244
        /* Check the address space */
1245
        if (access_type == ACCESS_CODE) {
1246
            if (msr_ir != (tlb->attr & 1))
1247
                continue;
1248
            ctx->prot = prot;
1249
            if (prot & PAGE_EXEC) {
1250
                ret = 0;
1251
                break;
1252
            }
1253
            ret = -3;
1254
        } else {
1255
            if (msr_dr != (tlb->attr & 1))
1256
                continue;
1257
            ctx->prot = prot;
1258
            if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
1259
                ret = 0;
1260
                break;
1261
            }
1262
            ret = -2;
1263
        }
1264
    }
1265
    if (ret >= 0)
1266
        ctx->raddr = raddr;
1267

    
1268
    return ret;
1269
}
1270

    
1271
static int check_physical (CPUState *env, mmu_ctx_t *ctx,
1272
                           target_ulong eaddr, int rw)
1273
{
1274
    int in_plb, ret;
1275

    
1276
    ctx->raddr = eaddr;
1277
    ctx->prot = PAGE_READ;
1278
    ret = 0;
1279
    switch (env->mmu_model) {
1280
    case POWERPC_MMU_32B:
1281
    case POWERPC_MMU_SOFT_6xx:
1282
    case POWERPC_MMU_SOFT_74xx:
1283
    case POWERPC_MMU_SOFT_4xx:
1284
    case POWERPC_MMU_REAL_4xx:
1285
    case POWERPC_MMU_BOOKE:
1286
        ctx->prot |= PAGE_WRITE;
1287
        break;
1288
#if defined(TARGET_PPC64)
1289
    case POWERPC_MMU_64B:
1290
        /* Real address are 60 bits long */
1291
        ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
1292
        ctx->prot |= PAGE_WRITE;
1293
        break;
1294
#endif
1295
    case POWERPC_MMU_SOFT_4xx_Z:
1296
        if (unlikely(msr_pe != 0)) {
1297
            /* 403 family add some particular protections,
1298
             * using PBL/PBU registers for accesses with no translation.
1299
             */
1300
            in_plb =
1301
                /* Check PLB validity */
1302
                (env->pb[0] < env->pb[1] &&
1303
                 /* and address in plb area */
1304
                 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
1305
                (env->pb[2] < env->pb[3] &&
1306
                 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
1307
            if (in_plb ^ msr_px) {
1308
                /* Access in protected area */
1309
                if (rw == 1) {
1310
                    /* Access is not allowed */
1311
                    ret = -2;
1312
                }
1313
            } else {
1314
                /* Read-write access is allowed */
1315
                ctx->prot |= PAGE_WRITE;
1316
            }
1317
        }
1318
        break;
1319
    case POWERPC_MMU_BOOKE_FSL:
1320
        /* XXX: TODO */
1321
        cpu_abort(env, "BookE FSL MMU model not implemented\n");
1322
        break;
1323
    default:
1324
        cpu_abort(env, "Unknown or invalid MMU model\n");
1325
        return -1;
1326
    }
1327

    
1328
    return ret;
1329
}
1330

    
1331
int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
1332
                          int rw, int access_type, int check_BATs)
1333
{
1334
    int ret;
1335
#if 0
1336
    if (loglevel != 0) {
1337
        fprintf(logfile, "%s\n", __func__);
1338
    }
1339
#endif
1340
    if ((access_type == ACCESS_CODE && msr_ir == 0) ||
1341
        (access_type != ACCESS_CODE && msr_dr == 0)) {
1342
        /* No address translation */
1343
        ret = check_physical(env, ctx, eaddr, rw);
1344
    } else {
1345
        ret = -1;
1346
        switch (env->mmu_model) {
1347
        case POWERPC_MMU_32B:
1348
        case POWERPC_MMU_SOFT_6xx:
1349
        case POWERPC_MMU_SOFT_74xx:
1350
            /* Try to find a BAT */
1351
            if (check_BATs)
1352
                ret = get_bat(env, ctx, eaddr, rw, access_type);
1353
            /* No break here */
1354
#if defined(TARGET_PPC64)
1355
        case POWERPC_MMU_64B:
1356
#endif
1357
            if (ret < 0) {
1358
                /* We didn't match any BAT entry or don't have BATs */
1359
                ret = get_segment(env, ctx, eaddr, rw, access_type);
1360
            }
1361
            break;
1362
        case POWERPC_MMU_SOFT_4xx:
1363
        case POWERPC_MMU_SOFT_4xx_Z:
1364
            ret = mmu40x_get_physical_address(env, ctx, eaddr,
1365
                                              rw, access_type);
1366
            break;
1367
        case POWERPC_MMU_BOOKE:
1368
            ret = mmubooke_get_physical_address(env, ctx, eaddr,
1369
                                                rw, access_type);
1370
            break;
1371
        case POWERPC_MMU_BOOKE_FSL:
1372
            /* XXX: TODO */
1373
            cpu_abort(env, "BookE FSL MMU model not implemented\n");
1374
            return -1;
1375
        case POWERPC_MMU_REAL_4xx:
1376
            cpu_abort(env, "PowerPC 401 does not do any translation\n");
1377
            return -1;
1378
        default:
1379
            cpu_abort(env, "Unknown or invalid MMU model\n");
1380
            return -1;
1381
        }
1382
    }
1383
#if 0
1384
    if (loglevel != 0) {
1385
        fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
1386
                __func__, eaddr, ret, ctx->raddr);
1387
    }
1388
#endif
1389

    
1390
    return ret;
1391
}
1392

    
1393
target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
1394
{
1395
    mmu_ctx_t ctx;
1396

    
1397
    if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0))
1398
        return -1;
1399

    
1400
    return ctx.raddr & TARGET_PAGE_MASK;
1401
}
1402

    
1403
/* Perform address translation */
1404
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1405
                              int mmu_idx, int is_softmmu)
1406
{
1407
    mmu_ctx_t ctx;
1408
    int access_type;
1409
    int ret = 0;
1410

    
1411
    if (rw == 2) {
1412
        /* code access */
1413
        rw = 0;
1414
        access_type = ACCESS_CODE;
1415
    } else {
1416
        /* data access */
1417
        /* XXX: put correct access by using cpu_restore_state()
1418
           correctly */
1419
        access_type = ACCESS_INT;
1420
        //        access_type = env->access_type;
1421
    }
1422
    ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
1423
    if (ret == 0) {
1424
        ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
1425
                           ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
1426
                           mmu_idx, is_softmmu);
1427
    } else if (ret < 0) {
1428
#if defined (DEBUG_MMU)
1429
        if (loglevel != 0)
1430
            cpu_dump_state(env, logfile, fprintf, 0);
1431
#endif
1432
        if (access_type == ACCESS_CODE) {
1433
            switch (ret) {
1434
            case -1:
1435
                /* No matches in page tables or TLB */
1436
                switch (env->mmu_model) {
1437
                case POWERPC_MMU_SOFT_6xx:
1438
                    env->exception_index = POWERPC_EXCP_IFTLB;
1439
                    env->error_code = 1 << 18;
1440
                    env->spr[SPR_IMISS] = address;
1441
                    env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
1442
                    goto tlb_miss;
1443
                case POWERPC_MMU_SOFT_74xx:
1444
                    env->exception_index = POWERPC_EXCP_IFTLB;
1445
                    goto tlb_miss_74xx;
1446
                case POWERPC_MMU_SOFT_4xx:
1447
                case POWERPC_MMU_SOFT_4xx_Z:
1448
                    env->exception_index = POWERPC_EXCP_ITLB;
1449
                    env->error_code = 0;
1450
                    env->spr[SPR_40x_DEAR] = address;
1451
                    env->spr[SPR_40x_ESR] = 0x00000000;
1452
                    break;
1453
                case POWERPC_MMU_32B:
1454
#if defined(TARGET_PPC64)
1455
                case POWERPC_MMU_64B:
1456
#endif
1457
                    env->exception_index = POWERPC_EXCP_ISI;
1458
                    env->error_code = 0x40000000;
1459
                    break;
1460
                case POWERPC_MMU_BOOKE:
1461
                    /* XXX: TODO */
1462
                    cpu_abort(env, "MMU model not implemented\n");
1463
                    return -1;
1464
                case POWERPC_MMU_BOOKE_FSL:
1465
                    /* XXX: TODO */
1466
                    cpu_abort(env, "MMU model not implemented\n");
1467
                    return -1;
1468
                case POWERPC_MMU_REAL_4xx:
1469
                    cpu_abort(env, "PowerPC 401 should never raise any MMU "
1470
                              "exceptions\n");
1471
                    return -1;
1472
                default:
1473
                    cpu_abort(env, "Unknown or invalid MMU model\n");
1474
                    return -1;
1475
                }
1476
                break;
1477
            case -2:
1478
                /* Access rights violation */
1479
                env->exception_index = POWERPC_EXCP_ISI;
1480
                env->error_code = 0x08000000;
1481
                break;
1482
            case -3:
1483
                /* No execute protection violation */
1484
                env->exception_index = POWERPC_EXCP_ISI;
1485
                env->error_code = 0x10000000;
1486
                break;
1487
            case -4:
1488
                /* Direct store exception */
1489
                /* No code fetch is allowed in direct-store areas */
1490
                env->exception_index = POWERPC_EXCP_ISI;
1491
                env->error_code = 0x10000000;
1492
                break;
1493
#if defined(TARGET_PPC64)
1494
            case -5:
1495
                /* No match in segment table */
1496
                env->exception_index = POWERPC_EXCP_ISEG;
1497
                env->error_code = 0;
1498
                break;
1499
#endif
1500
            }
1501
        } else {
1502
            switch (ret) {
1503
            case -1:
1504
                /* No matches in page tables or TLB */
1505
                switch (env->mmu_model) {
1506
                case POWERPC_MMU_SOFT_6xx:
1507
                    if (rw == 1) {
1508
                        env->exception_index = POWERPC_EXCP_DSTLB;
1509
                        env->error_code = 1 << 16;
1510
                    } else {
1511
                        env->exception_index = POWERPC_EXCP_DLTLB;
1512
                        env->error_code = 0;
1513
                    }
1514
                    env->spr[SPR_DMISS] = address;
1515
                    env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
1516
                tlb_miss:
1517
                    env->error_code |= ctx.key << 19;
1518
                    env->spr[SPR_HASH1] = ctx.pg_addr[0];
1519
                    env->spr[SPR_HASH2] = ctx.pg_addr[1];
1520
                    break;
1521
                case POWERPC_MMU_SOFT_74xx:
1522
                    if (rw == 1) {
1523
                        env->exception_index = POWERPC_EXCP_DSTLB;
1524
                    } else {
1525
                        env->exception_index = POWERPC_EXCP_DLTLB;
1526
                    }
1527
                tlb_miss_74xx:
1528
                    /* Implement LRU algorithm */
1529
                    env->error_code = ctx.key << 19;
1530
                    env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
1531
                        ((env->last_way + 1) & (env->nb_ways - 1));
1532
                    env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
1533
                    break;
1534
                case POWERPC_MMU_SOFT_4xx:
1535
                case POWERPC_MMU_SOFT_4xx_Z:
1536
                    env->exception_index = POWERPC_EXCP_DTLB;
1537
                    env->error_code = 0;
1538
                    env->spr[SPR_40x_DEAR] = address;
1539
                    if (rw)
1540
                        env->spr[SPR_40x_ESR] = 0x00800000;
1541
                    else
1542
                        env->spr[SPR_40x_ESR] = 0x00000000;
1543
                    break;
1544
                case POWERPC_MMU_32B:
1545
#if defined(TARGET_PPC64)
1546
                case POWERPC_MMU_64B:
1547
#endif
1548
                    env->exception_index = POWERPC_EXCP_DSI;
1549
                    env->error_code = 0;
1550
                    env->spr[SPR_DAR] = address;
1551
                    if (rw == 1)
1552
                        env->spr[SPR_DSISR] = 0x42000000;
1553
                    else
1554
                        env->spr[SPR_DSISR] = 0x40000000;
1555
                    break;
1556
                case POWERPC_MMU_BOOKE:
1557
                    /* XXX: TODO */
1558
                    cpu_abort(env, "MMU model not implemented\n");
1559
                    return -1;
1560
                case POWERPC_MMU_BOOKE_FSL:
1561
                    /* XXX: TODO */
1562
                    cpu_abort(env, "MMU model not implemented\n");
1563
                    return -1;
1564
                case POWERPC_MMU_REAL_4xx:
1565
                    cpu_abort(env, "PowerPC 401 should never raise any MMU "
1566
                              "exceptions\n");
1567
                    return -1;
1568
                default:
1569
                    cpu_abort(env, "Unknown or invalid MMU model\n");
1570
                    return -1;
1571
                }
1572
                break;
1573
            case -2:
1574
                /* Access rights violation */
1575
                env->exception_index = POWERPC_EXCP_DSI;
1576
                env->error_code = 0;
1577
                env->spr[SPR_DAR] = address;
1578
                if (rw == 1)
1579
                    env->spr[SPR_DSISR] = 0x0A000000;
1580
                else
1581
                    env->spr[SPR_DSISR] = 0x08000000;
1582
                break;
1583
            case -4:
1584
                /* Direct store exception */
1585
                switch (access_type) {
1586
                case ACCESS_FLOAT:
1587
                    /* Floating point load/store */
1588
                    env->exception_index = POWERPC_EXCP_ALIGN;
1589
                    env->error_code = POWERPC_EXCP_ALIGN_FP;
1590
                    env->spr[SPR_DAR] = address;
1591
                    break;
1592
                case ACCESS_RES:
1593
                    /* lwarx, ldarx or stwcx. */
1594
                    env->exception_index = POWERPC_EXCP_DSI;
1595
                    env->error_code = 0;
1596
                    env->spr[SPR_DAR] = address;
1597
                    if (rw == 1)
1598
                        env->spr[SPR_DSISR] = 0x06000000;
1599
                    else
1600
                        env->spr[SPR_DSISR] = 0x04000000;
1601
                    break;
1602
                case ACCESS_EXT:
1603
                    /* eciwx or ecowx */
1604
                    env->exception_index = POWERPC_EXCP_DSI;
1605
                    env->error_code = 0;
1606
                    env->spr[SPR_DAR] = address;
1607
                    if (rw == 1)
1608
                        env->spr[SPR_DSISR] = 0x06100000;
1609
                    else
1610
                        env->spr[SPR_DSISR] = 0x04100000;
1611
                    break;
1612
                default:
1613
                    printf("DSI: invalid exception (%d)\n", ret);
1614
                    env->exception_index = POWERPC_EXCP_PROGRAM;
1615
                    env->error_code =
1616
                        POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
1617
                    env->spr[SPR_DAR] = address;
1618
                    break;
1619
                }
1620
                break;
1621
#if defined(TARGET_PPC64)
1622
            case -5:
1623
                /* No match in segment table */
1624
                env->exception_index = POWERPC_EXCP_DSEG;
1625
                env->error_code = 0;
1626
                env->spr[SPR_DAR] = address;
1627
                break;
1628
#endif
1629
            }
1630
        }
1631
#if 0
1632
        printf("%s: set exception to %d %02x\n", __func__,
1633
               env->exception, env->error_code);
1634
#endif
1635
        ret = 1;
1636
    }
1637

    
1638
    return ret;
1639
}
1640

    
1641
/*****************************************************************************/
1642
/* BATs management */
1643
#if !defined(FLUSH_ALL_TLBS)
1644
static always_inline void do_invalidate_BAT (CPUPPCState *env,
1645
                                             target_ulong BATu,
1646
                                             target_ulong mask)
1647
{
1648
    target_ulong base, end, page;
1649

    
1650
    base = BATu & ~0x0001FFFF;
1651
    end = base + mask + 0x00020000;
1652
#if defined (DEBUG_BATS)
1653
    if (loglevel != 0) {
1654
        fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
1655
                base, end, mask);
1656
    }
1657
#endif
1658
    for (page = base; page != end; page += TARGET_PAGE_SIZE)
1659
        tlb_flush_page(env, page);
1660
#if defined (DEBUG_BATS)
1661
    if (loglevel != 0)
1662
        fprintf(logfile, "Flush done\n");
1663
#endif
1664
}
1665
#endif
1666

    
1667
static always_inline void dump_store_bat (CPUPPCState *env, char ID,
1668
                                          int ul, int nr, target_ulong value)
1669
{
1670
#if defined (DEBUG_BATS)
1671
    if (loglevel != 0) {
1672
        fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n",
1673
                ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
1674
    }
1675
#endif
1676
}
1677

    
1678
target_ulong do_load_ibatu (CPUPPCState *env, int nr)
1679
{
1680
    return env->IBAT[0][nr];
1681
}
1682

    
1683
target_ulong do_load_ibatl (CPUPPCState *env, int nr)
1684
{
1685
    return env->IBAT[1][nr];
1686
}
1687

    
1688
void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1689
{
1690
    target_ulong mask;
1691

    
1692
    dump_store_bat(env, 'I', 0, nr, value);
1693
    if (env->IBAT[0][nr] != value) {
1694
        mask = (value << 15) & 0x0FFE0000UL;
1695
#if !defined(FLUSH_ALL_TLBS)
1696
        do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1697
#endif
1698
        /* When storing valid upper BAT, mask BEPI and BRPN
1699
         * and invalidate all TLBs covered by this BAT
1700
         */
1701
        mask = (value << 15) & 0x0FFE0000UL;
1702
        env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1703
            (value & ~0x0001FFFFUL & ~mask);
1704
        env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1705
            (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1706
#if !defined(FLUSH_ALL_TLBS)
1707
        do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1708
#else
1709
        tlb_flush(env, 1);
1710
#endif
1711
    }
1712
}
1713

    
1714
void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1715
{
1716
    dump_store_bat(env, 'I', 1, nr, value);
1717
    env->IBAT[1][nr] = value;
1718
}
1719

    
1720
target_ulong do_load_dbatu (CPUPPCState *env, int nr)
1721
{
1722
    return env->DBAT[0][nr];
1723
}
1724

    
1725
target_ulong do_load_dbatl (CPUPPCState *env, int nr)
1726
{
1727
    return env->DBAT[1][nr];
1728
}
1729

    
1730
void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1731
{
1732
    target_ulong mask;
1733

    
1734
    dump_store_bat(env, 'D', 0, nr, value);
1735
    if (env->DBAT[0][nr] != value) {
1736
        /* When storing valid upper BAT, mask BEPI and BRPN
1737
         * and invalidate all TLBs covered by this BAT
1738
         */
1739
        mask = (value << 15) & 0x0FFE0000UL;
1740
#if !defined(FLUSH_ALL_TLBS)
1741
        do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1742
#endif
1743
        mask = (value << 15) & 0x0FFE0000UL;
1744
        env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1745
            (value & ~0x0001FFFFUL & ~mask);
1746
        env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1747
            (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1748
#if !defined(FLUSH_ALL_TLBS)
1749
        do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1750
#else
1751
        tlb_flush(env, 1);
1752
#endif
1753
    }
1754
}
1755

    
1756
void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1757
{
1758
    dump_store_bat(env, 'D', 1, nr, value);
1759
    env->DBAT[1][nr] = value;
1760
}
1761

    
1762
/*****************************************************************************/
1763
/* TLB management */
1764
void ppc_tlb_invalidate_all (CPUPPCState *env)
1765
{
1766
    switch (env->mmu_model) {
1767
    case POWERPC_MMU_SOFT_6xx:
1768
    case POWERPC_MMU_SOFT_74xx:
1769
        ppc6xx_tlb_invalidate_all(env);
1770
        break;
1771
    case POWERPC_MMU_SOFT_4xx:
1772
    case POWERPC_MMU_SOFT_4xx_Z:
1773
        ppc4xx_tlb_invalidate_all(env);
1774
        break;
1775
    case POWERPC_MMU_REAL_4xx:
1776
        cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1777
        break;
1778
    case POWERPC_MMU_BOOKE:
1779
        /* XXX: TODO */
1780
        cpu_abort(env, "MMU model not implemented\n");
1781
        break;
1782
    case POWERPC_MMU_BOOKE_FSL:
1783
        /* XXX: TODO */
1784
        cpu_abort(env, "MMU model not implemented\n");
1785
        break;
1786
    case POWERPC_MMU_32B:
1787
#if defined(TARGET_PPC64)
1788
    case POWERPC_MMU_64B:
1789
#endif /* defined(TARGET_PPC64) */
1790
        tlb_flush(env, 1);
1791
        break;
1792
    default:
1793
        /* XXX: TODO */
1794
        cpu_abort(env, "Unknown MMU model\n");
1795
        break;
1796
    }
1797
}
1798

    
1799
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
1800
{
1801
#if !defined(FLUSH_ALL_TLBS)
1802
    addr &= TARGET_PAGE_MASK;
1803
    switch (env->mmu_model) {
1804
    case POWERPC_MMU_SOFT_6xx:
1805
    case POWERPC_MMU_SOFT_74xx:
1806
        ppc6xx_tlb_invalidate_virt(env, addr, 0);
1807
        if (env->id_tlbs == 1)
1808
            ppc6xx_tlb_invalidate_virt(env, addr, 1);
1809
        break;
1810
    case POWERPC_MMU_SOFT_4xx:
1811
    case POWERPC_MMU_SOFT_4xx_Z:
1812
        ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
1813
        break;
1814
    case POWERPC_MMU_REAL_4xx:
1815
        cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1816
        break;
1817
    case POWERPC_MMU_BOOKE:
1818
        /* XXX: TODO */
1819
        cpu_abort(env, "MMU model not implemented\n");
1820
        break;
1821
    case POWERPC_MMU_BOOKE_FSL:
1822
        /* XXX: TODO */
1823
        cpu_abort(env, "MMU model not implemented\n");
1824
        break;
1825
    case POWERPC_MMU_32B:
1826
        /* tlbie invalidate TLBs for all segments */
1827
        addr &= ~((target_ulong)-1 << 28);
1828
        /* XXX: this case should be optimized,
1829
         * giving a mask to tlb_flush_page
1830
         */
1831
        tlb_flush_page(env, addr | (0x0 << 28));
1832
        tlb_flush_page(env, addr | (0x1 << 28));
1833
        tlb_flush_page(env, addr | (0x2 << 28));
1834
        tlb_flush_page(env, addr | (0x3 << 28));
1835
        tlb_flush_page(env, addr | (0x4 << 28));
1836
        tlb_flush_page(env, addr | (0x5 << 28));
1837
        tlb_flush_page(env, addr | (0x6 << 28));
1838
        tlb_flush_page(env, addr | (0x7 << 28));
1839
        tlb_flush_page(env, addr | (0x8 << 28));
1840
        tlb_flush_page(env, addr | (0x9 << 28));
1841
        tlb_flush_page(env, addr | (0xA << 28));
1842
        tlb_flush_page(env, addr | (0xB << 28));
1843
        tlb_flush_page(env, addr | (0xC << 28));
1844
        tlb_flush_page(env, addr | (0xD << 28));
1845
        tlb_flush_page(env, addr | (0xE << 28));
1846
        tlb_flush_page(env, addr | (0xF << 28));
1847
        break;
1848
#if defined(TARGET_PPC64)
1849
    case POWERPC_MMU_64B:
1850
        /* tlbie invalidate TLBs for all segments */
1851
        /* XXX: given the fact that there are too many segments to invalidate,
1852
         *      and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
1853
         *      we just invalidate all TLBs
1854
         */
1855
        tlb_flush(env, 1);
1856
        break;
1857
#endif /* defined(TARGET_PPC64) */
1858
    default:
1859
        /* XXX: TODO */
1860
        cpu_abort(env, "Unknown MMU model\n");
1861
        break;
1862
    }
1863
#else
1864
    ppc_tlb_invalidate_all(env);
1865
#endif
1866
}
1867

    
1868
/*****************************************************************************/
1869
/* Special registers manipulation */
1870
#if defined(TARGET_PPC64)
1871
target_ulong ppc_load_asr (CPUPPCState *env)
1872
{
1873
    return env->asr;
1874
}
1875

    
1876
void ppc_store_asr (CPUPPCState *env, target_ulong value)
1877
{
1878
    if (env->asr != value) {
1879
        env->asr = value;
1880
        tlb_flush(env, 1);
1881
    }
1882
}
1883
#endif
1884

    
1885
target_ulong do_load_sdr1 (CPUPPCState *env)
1886
{
1887
    return env->sdr1;
1888
}
1889

    
1890
void do_store_sdr1 (CPUPPCState *env, target_ulong value)
1891
{
1892
#if defined (DEBUG_MMU)
1893
    if (loglevel != 0) {
1894
        fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value);
1895
    }
1896
#endif
1897
    if (env->sdr1 != value) {
1898
        /* XXX: for PowerPC 64, should check that the HTABSIZE value
1899
         *      is <= 28
1900
         */
1901
        env->sdr1 = value;
1902
        tlb_flush(env, 1);
1903
    }
1904
}
1905

    
1906
#if 0 // Unused
1907
target_ulong do_load_sr (CPUPPCState *env, int srnum)
1908
{
1909
    return env->sr[srnum];
1910
}
1911
#endif
1912

    
1913
void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1914
{
1915
#if defined (DEBUG_MMU)
1916
    if (loglevel != 0) {
1917
        fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n",
1918
                __func__, srnum, value, env->sr[srnum]);
1919
    }
1920
#endif
1921
    if (env->sr[srnum] != value) {
1922
        env->sr[srnum] = value;
1923
#if !defined(FLUSH_ALL_TLBS) && 0
1924
        {
1925
            target_ulong page, end;
1926
            /* Invalidate 256 MB of virtual memory */
1927
            page = (16 << 20) * srnum;
1928
            end = page + (16 << 20);
1929
            for (; page != end; page += TARGET_PAGE_SIZE)
1930
                tlb_flush_page(env, page);
1931
        }
1932
#else
1933
        tlb_flush(env, 1);
1934
#endif
1935
    }
1936
}
1937
#endif /* !defined (CONFIG_USER_ONLY) */
1938

    
1939
target_ulong ppc_load_xer (CPUPPCState *env)
1940
{
1941
    return (xer_so << XER_SO) |
1942
        (xer_ov << XER_OV) |
1943
        (xer_ca << XER_CA) |
1944
        (xer_bc << XER_BC) |
1945
        (xer_cmp << XER_CMP);
1946
}
1947

    
1948
void ppc_store_xer (CPUPPCState *env, target_ulong value)
1949
{
1950
    xer_so = (value >> XER_SO) & 0x01;
1951
    xer_ov = (value >> XER_OV) & 0x01;
1952
    xer_ca = (value >> XER_CA) & 0x01;
1953
    xer_cmp = (value >> XER_CMP) & 0xFF;
1954
    xer_bc = (value >> XER_BC) & 0x7F;
1955
}
1956

    
1957
/* Swap temporary saved registers with GPRs */
1958
static always_inline void swap_gpr_tgpr (CPUPPCState *env)
1959
{
1960
    ppc_gpr_t tmp;
1961

    
1962
    tmp = env->gpr[0];
1963
    env->gpr[0] = env->tgpr[0];
1964
    env->tgpr[0] = tmp;
1965
    tmp = env->gpr[1];
1966
    env->gpr[1] = env->tgpr[1];
1967
    env->tgpr[1] = tmp;
1968
    tmp = env->gpr[2];
1969
    env->gpr[2] = env->tgpr[2];
1970
    env->tgpr[2] = tmp;
1971
    tmp = env->gpr[3];
1972
    env->gpr[3] = env->tgpr[3];
1973
    env->tgpr[3] = tmp;
1974
}
1975

    
1976
/* GDBstub can read and write MSR... */
1977
target_ulong do_load_msr (CPUPPCState *env)
1978
{
1979
    return
1980
#if defined (TARGET_PPC64)
1981
        ((target_ulong)msr_sf   << MSR_SF)   |
1982
        ((target_ulong)msr_isf  << MSR_ISF)  |
1983
        ((target_ulong)msr_hv   << MSR_HV)   |
1984
#endif
1985
        ((target_ulong)msr_ucle << MSR_UCLE) |
1986
        ((target_ulong)msr_vr   << MSR_VR)   | /* VR / SPE */
1987
        ((target_ulong)msr_ap   << MSR_AP)   |
1988
        ((target_ulong)msr_sa   << MSR_SA)   |
1989
        ((target_ulong)msr_key  << MSR_KEY)  |
1990
        ((target_ulong)msr_pow  << MSR_POW)  |
1991
        ((target_ulong)msr_tgpr << MSR_TGPR) | /* TGPR / CE */
1992
        ((target_ulong)msr_ile  << MSR_ILE)  |
1993
        ((target_ulong)msr_ee   << MSR_EE)   |
1994
        ((target_ulong)msr_pr   << MSR_PR)   |
1995
        ((target_ulong)msr_fp   << MSR_FP)   |
1996
        ((target_ulong)msr_me   << MSR_ME)   |
1997
        ((target_ulong)msr_fe0  << MSR_FE0)  |
1998
        ((target_ulong)msr_se   << MSR_SE)   | /* SE / DWE / UBLE */
1999
        ((target_ulong)msr_be   << MSR_BE)   | /* BE / DE */
2000
        ((target_ulong)msr_fe1  << MSR_FE1)  |
2001
        ((target_ulong)msr_al   << MSR_AL)   |
2002
        ((target_ulong)msr_ep   << MSR_EP)   |
2003
        ((target_ulong)msr_ir   << MSR_IR)   |
2004
        ((target_ulong)msr_dr   << MSR_DR)   |
2005
        ((target_ulong)msr_pe   << MSR_PE)   |
2006
        ((target_ulong)msr_px   << MSR_PX)   | /* PX / PMM */
2007
        ((target_ulong)msr_ri   << MSR_RI)   |
2008
        ((target_ulong)msr_le   << MSR_LE);
2009
}
2010

    
2011
int do_store_msr (CPUPPCState *env, target_ulong value)
2012
{
2013
    int enter_pm;
2014

    
2015
    value &= env->msr_mask;
2016
    if (((value >> MSR_IR) & 1) != msr_ir ||
2017
        ((value >> MSR_DR) & 1) != msr_dr) {
2018
        /* Flush all tlb when changing translation mode */
2019
        tlb_flush(env, 1);
2020
        env->interrupt_request |= CPU_INTERRUPT_EXITTB;
2021
    }
2022
#if !defined (CONFIG_USER_ONLY)
2023
    if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
2024
                 ((value >> MSR_TGPR) & 1) != msr_tgpr)) {
2025
        /* Swap temporary saved registers with GPRs */
2026
        swap_gpr_tgpr(env);
2027
    }
2028
    if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
2029
        /* Change the exception prefix on PowerPC 601 */
2030
        env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
2031
    }
2032
#endif
2033
#if defined (TARGET_PPC64)
2034
    msr_sf   = (value >> MSR_SF)   & 1;
2035
    msr_isf  = (value >> MSR_ISF)  & 1;
2036
    msr_hv   = (value >> MSR_HV)   & 1;
2037
#endif
2038
    msr_ucle = (value >> MSR_UCLE) & 1;
2039
    msr_vr   = (value >> MSR_VR)   & 1; /* VR / SPE */
2040
    msr_ap   = (value >> MSR_AP)   & 1;
2041
    msr_sa   = (value >> MSR_SA)   & 1;
2042
    msr_key  = (value >> MSR_KEY)  & 1;
2043
    msr_pow  = (value >> MSR_POW)  & 1;
2044
    msr_tgpr = (value >> MSR_TGPR) & 1; /* TGPR / CE */
2045
    msr_ile  = (value >> MSR_ILE)  & 1;
2046
    msr_ee   = (value >> MSR_EE)   & 1;
2047
    msr_pr   = (value >> MSR_PR)   & 1;
2048
    msr_fp   = (value >> MSR_FP)   & 1;
2049
    msr_me   = (value >> MSR_ME)   & 1;
2050
    msr_fe0  = (value >> MSR_FE0)  & 1;
2051
    msr_se   = (value >> MSR_SE)   & 1; /* SE / DWE / UBLE */
2052
    msr_be   = (value >> MSR_BE)   & 1; /* BE / DE */
2053
    msr_fe1  = (value >> MSR_FE1)  & 1;
2054
    msr_al   = (value >> MSR_AL)   & 1;
2055
    msr_ep   = (value >> MSR_EP)   & 1;
2056
    msr_ir   = (value >> MSR_IR)   & 1;
2057
    msr_dr   = (value >> MSR_DR)   & 1;
2058
    msr_pe   = (value >> MSR_PE)   & 1;
2059
    msr_px   = (value >> MSR_PX)   & 1; /* PX / PMM */
2060
    msr_ri   = (value >> MSR_RI)   & 1;
2061
    msr_le   = (value >> MSR_LE)   & 1;
2062
    do_compute_hflags(env);
2063

    
2064
    enter_pm = 0;
2065
    switch (env->excp_model) {
2066
    case POWERPC_EXCP_603:
2067
    case POWERPC_EXCP_603E:
2068
    case POWERPC_EXCP_G2:
2069
        /* Don't handle SLEEP mode: we should disable all clocks...
2070
         * No dynamic power-management.
2071
         */
2072
        if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0)
2073
            enter_pm = 1;
2074
        break;
2075
    case POWERPC_EXCP_604:
2076
        if (msr_pow == 1)
2077
            enter_pm = 1;
2078
        break;
2079
    case POWERPC_EXCP_7x0:
2080
        if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
2081
            enter_pm = 1;
2082
        break;
2083
    default:
2084
        break;
2085
    }
2086

    
2087
    return enter_pm;
2088
}
2089

    
2090
#if defined(TARGET_PPC64)
2091
int ppc_store_msr_32 (CPUPPCState *env, uint32_t value)
2092
{
2093
    return do_store_msr(env, (do_load_msr(env) & ~0xFFFFFFFFULL) |
2094
                        (value & 0xFFFFFFFF));
2095
}
2096
#endif
2097

    
2098
void do_compute_hflags (CPUPPCState *env)
2099
{
2100
    /* Compute current hflags */
2101
    env->hflags = (msr_vr << MSR_VR) |
2102
        (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_pr << MSR_PR) |
2103
        (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) |
2104
        (msr_be << MSR_BE) | (msr_fe1 << MSR_FE1) | (msr_le << MSR_LE);
2105
#if defined (TARGET_PPC64)
2106
    env->hflags |= msr_cm << MSR_CM;
2107
    env->hflags |= (uint64_t)msr_sf << MSR_SF;
2108
    env->hflags |= (uint64_t)msr_hv << MSR_HV;
2109
    /* Precompute MMU index */
2110
    if (msr_pr == 0 && msr_hv == 1)
2111
        env->mmu_idx = 2;
2112
    else
2113
#endif
2114
        env->mmu_idx = 1 - msr_pr;
2115
}
2116

    
2117
/*****************************************************************************/
2118
/* Exception processing */
2119
#if defined (CONFIG_USER_ONLY)
2120
void do_interrupt (CPUState *env)
2121
{
2122
    env->exception_index = POWERPC_EXCP_NONE;
2123
    env->error_code = 0;
2124
}
2125

    
2126
void ppc_hw_interrupt (CPUState *env)
2127
{
2128
    env->exception_index = POWERPC_EXCP_NONE;
2129
    env->error_code = 0;
2130
}
2131
#else /* defined (CONFIG_USER_ONLY) */
2132
static void dump_syscall (CPUState *env)
2133
{
2134
    fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
2135
            " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",
2136
            env->gpr[0], env->gpr[3], env->gpr[4],
2137
            env->gpr[5], env->gpr[6], env->nip);
2138
}
2139

    
2140
/* Note that this function should be greatly optimized
2141
 * when called with a constant excp, from ppc_hw_interrupt
2142
 */
2143
static always_inline void powerpc_excp (CPUState *env,
2144
                                        int excp_model, int excp)
2145
{
2146
    target_ulong msr, vector;
2147
    int srr0, srr1, asrr0, asrr1;
2148

    
2149
    if (loglevel & CPU_LOG_INT) {
2150
        fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
2151
                env->nip, excp, env->error_code);
2152
    }
2153
    msr = do_load_msr(env);
2154
    srr0 = SPR_SRR0;
2155
    srr1 = SPR_SRR1;
2156
    asrr0 = -1;
2157
    asrr1 = -1;
2158
    msr &= ~((target_ulong)0x783F0000);
2159
    switch (excp) {
2160
    case POWERPC_EXCP_NONE:
2161
        /* Should never happen */
2162
        return;
2163
    case POWERPC_EXCP_CRITICAL:    /* Critical input                         */
2164
        msr_ri = 0; /* XXX: check this */
2165
        switch (excp_model) {
2166
        case POWERPC_EXCP_40x:
2167
            srr0 = SPR_40x_SRR2;
2168
            srr1 = SPR_40x_SRR3;
2169
            break;
2170
        case POWERPC_EXCP_BOOKE:
2171
            srr0 = SPR_BOOKE_CSRR0;
2172
            srr1 = SPR_BOOKE_CSRR1;
2173
            break;
2174
        case POWERPC_EXCP_G2:
2175
            break;
2176
        default:
2177
            goto excp_invalid;
2178
        }
2179
        goto store_next;
2180
    case POWERPC_EXCP_MCHECK:    /* Machine check exception                  */
2181
        if (msr_me == 0) {
2182
            /* Machine check exception is not enabled.
2183
             * Enter checkstop state.
2184
             */
2185
            if (loglevel != 0) {
2186
                fprintf(logfile, "Machine check while not allowed. "
2187
                        "Entering checkstop state\n");
2188
            } else {
2189
                fprintf(stderr, "Machine check while not allowed. "
2190
                        "Entering checkstop state\n");
2191
            }
2192
            env->halted = 1;
2193
            env->interrupt_request |= CPU_INTERRUPT_EXITTB;
2194
        }
2195
        msr_ri = 0;
2196
        msr_me = 0;
2197
#if defined(TARGET_PPC64H)
2198
        msr_hv = 1;
2199
#endif
2200
        /* XXX: should also have something loaded in DAR / DSISR */
2201
        switch (excp_model) {
2202
        case POWERPC_EXCP_40x:
2203
            srr0 = SPR_40x_SRR2;
2204
            srr1 = SPR_40x_SRR3;
2205
            break;
2206
        case POWERPC_EXCP_BOOKE:
2207
            srr0 = SPR_BOOKE_MCSRR0;
2208
            srr1 = SPR_BOOKE_MCSRR1;
2209
            asrr0 = SPR_BOOKE_CSRR0;
2210
            asrr1 = SPR_BOOKE_CSRR1;
2211
            break;
2212
        default:
2213
            break;
2214
        }
2215
        goto store_next;
2216
    case POWERPC_EXCP_DSI:       /* Data storage exception                   */
2217
#if defined (DEBUG_EXCEPTIONS)
2218
        if (loglevel != 0) {
2219
            fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
2220
                    "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
2221
        }
2222
#endif
2223
        msr_ri = 0;
2224
#if defined(TARGET_PPC64H)
2225
        if (lpes1 == 0)
2226
            msr_hv = 1;
2227
#endif
2228
        goto store_next;
2229
    case POWERPC_EXCP_ISI:       /* Instruction storage exception            */
2230
#if defined (DEBUG_EXCEPTIONS)
2231
        if (loglevel != 0) {
2232
            fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX
2233
                    "\n", msr, env->nip);
2234
        }
2235
#endif
2236
        msr_ri = 0;
2237
#if defined(TARGET_PPC64H)
2238
        if (lpes1 == 0)
2239
            msr_hv = 1;
2240
#endif
2241
        msr |= env->error_code;
2242
        goto store_next;
2243
    case POWERPC_EXCP_EXTERNAL:  /* External input                           */
2244
        msr_ri = 0;
2245
#if defined(TARGET_PPC64H)
2246
        if (lpes0 == 1)
2247
            msr_hv = 1;
2248
#endif
2249
        goto store_next;
2250
    case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
2251
        msr_ri = 0;
2252
#if defined(TARGET_PPC64H)
2253
        if (lpes1 == 0)
2254
            msr_hv = 1;
2255
#endif
2256
        /* XXX: this is false */
2257
        /* Get rS/rD and rA from faulting opcode */
2258
        env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
2259
        goto store_current;
2260
    case POWERPC_EXCP_PROGRAM:   /* Program exception                        */
2261
        switch (env->error_code & ~0xF) {
2262
        case POWERPC_EXCP_FP:
2263
            if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
2264
#if defined (DEBUG_EXCEPTIONS)
2265
                if (loglevel != 0) {
2266
                    fprintf(logfile, "Ignore floating point exception\n");
2267
                }
2268
#endif
2269
                return;
2270
            }
2271
            msr_ri = 0;
2272
#if defined(TARGET_PPC64H)
2273
            if (lpes1 == 0)
2274
                msr_hv = 1;
2275
#endif
2276
            msr |= 0x00100000;
2277
            /* Set FX */
2278
            env->fpscr[7] |= 0x8;
2279
            /* Finally, update FEX */
2280
            if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
2281
                ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
2282
                env->fpscr[7] |= 0x4;
2283
            if (msr_fe0 != msr_fe1) {
2284
                msr |= 0x00010000;
2285
                goto store_current;
2286
            }
2287
            break;
2288
        case POWERPC_EXCP_INVAL:
2289
#if defined (DEBUG_EXCEPTIONS)
2290
            if (loglevel != 0) {
2291
                fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n",
2292
                        env->nip);
2293
            }
2294
#endif
2295
            msr_ri = 0;
2296
#if defined(TARGET_PPC64H)
2297
            if (lpes1 == 0)
2298
                msr_hv = 1;
2299
#endif
2300
            msr |= 0x00080000;
2301
            break;
2302
        case POWERPC_EXCP_PRIV:
2303
            msr_ri = 0;
2304
#if defined(TARGET_PPC64H)
2305
            if (lpes1 == 0)
2306
                msr_hv = 1;
2307
#endif
2308
            msr |= 0x00040000;
2309
            break;
2310
        case POWERPC_EXCP_TRAP:
2311
            msr_ri = 0;
2312
#if defined(TARGET_PPC64H)
2313
            if (lpes1 == 0)
2314
                msr_hv = 1;
2315
#endif
2316
            msr |= 0x00020000;
2317
            break;
2318
        default:
2319
            /* Should never occur */
2320
            cpu_abort(env, "Invalid program exception %d. Aborting\n",
2321
                      env->error_code);
2322
            break;
2323
        }
2324
        goto store_next;
2325
    case POWERPC_EXCP_FPU:       /* Floating-point unavailable exception     */
2326
        msr_ri = 0;
2327
#if defined(TARGET_PPC64H)
2328
        if (lpes1 == 0)
2329
            msr_hv = 1;
2330
#endif
2331
        goto store_current;
2332
    case POWERPC_EXCP_SYSCALL:   /* System call exception                    */
2333
        /* NOTE: this is a temporary hack to support graphics OSI
2334
           calls from the MOL driver */
2335
        /* XXX: To be removed */
2336
        if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
2337
            env->osi_call) {
2338
            if (env->osi_call(env) != 0)
2339
                return;
2340
        }
2341
        if (loglevel & CPU_LOG_INT) {
2342
            dump_syscall(env);
2343
        }
2344
        msr_ri = 0;
2345
#if defined(TARGET_PPC64H)
2346
        if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
2347
            msr_hv = 1;
2348
#endif
2349
        goto store_next;
2350
    case POWERPC_EXCP_APU:       /* Auxiliary processor unavailable          */
2351
        msr_ri = 0;
2352
        goto store_current;
2353
    case POWERPC_EXCP_DECR:      /* Decrementer exception                    */
2354
        msr_ri = 0;
2355
#if defined(TARGET_PPC64H)
2356
        if (lpes1 == 0)
2357
            msr_hv = 1;
2358
#endif
2359
        goto store_next;
2360
    case POWERPC_EXCP_FIT:       /* Fixed-interval timer interrupt           */
2361
        /* FIT on 4xx */
2362
#if defined (DEBUG_EXCEPTIONS)
2363
        if (loglevel != 0)
2364
            fprintf(logfile, "FIT exception\n");
2365
#endif
2366
        msr_ri = 0; /* XXX: check this */
2367
        goto store_next;
2368
    case POWERPC_EXCP_WDT:       /* Watchdog timer interrupt                 */
2369
#if defined (DEBUG_EXCEPTIONS)
2370
        if (loglevel != 0)
2371
            fprintf(logfile, "WDT exception\n");
2372
#endif
2373
        switch (excp_model) {
2374
        case POWERPC_EXCP_BOOKE:
2375
            srr0 = SPR_BOOKE_CSRR0;
2376
            srr1 = SPR_BOOKE_CSRR1;
2377
            break;
2378
        default:
2379
            break;
2380
        }
2381
        msr_ri = 0; /* XXX: check this */
2382
        goto store_next;
2383
    case POWERPC_EXCP_DTLB:      /* Data TLB error                           */
2384
        msr_ri = 0; /* XXX: check this */
2385
        goto store_next;
2386
    case POWERPC_EXCP_ITLB:      /* Instruction TLB error                    */
2387
        msr_ri = 0; /* XXX: check this */
2388
        goto store_next;
2389
    case POWERPC_EXCP_DEBUG:     /* Debug interrupt                          */
2390
        switch (excp_model) {
2391
        case POWERPC_EXCP_BOOKE:
2392
            srr0 = SPR_BOOKE_DSRR0;
2393
            srr1 = SPR_BOOKE_DSRR1;
2394
            asrr0 = SPR_BOOKE_CSRR0;
2395
            asrr1 = SPR_BOOKE_CSRR1;
2396
            break;
2397
        default:
2398
            break;
2399
        }
2400
        /* XXX: TODO */
2401
        cpu_abort(env, "Debug exception is not implemented yet !\n");
2402
        goto store_next;
2403
#if defined(TARGET_PPCEMB)
2404
    case POWERPC_EXCP_SPEU:      /* SPE/embedded floating-point unavailable  */
2405
        msr_ri = 0; /* XXX: check this */
2406
        goto store_current;
2407
    case POWERPC_EXCP_EFPDI:     /* Embedded floating-point data interrupt   */
2408
        /* XXX: TODO */
2409
        cpu_abort(env, "Embedded floating point data exception "
2410
                  "is not implemented yet !\n");
2411
        goto store_next;
2412
    case POWERPC_EXCP_EFPRI:     /* Embedded floating-point round interrupt  */
2413
        /* XXX: TODO */
2414
        cpu_abort(env, "Embedded floating point round exception "
2415
                  "is not implemented yet !\n");
2416
        goto store_next;
2417
    case POWERPC_EXCP_EPERFM:    /* Embedded performance monitor interrupt   */
2418
        msr_ri = 0;
2419
        /* XXX: TODO */
2420
        cpu_abort(env,
2421
                  "Performance counter exception is not implemented yet !\n");
2422
        goto store_next;
2423
    case POWERPC_EXCP_DOORI:     /* Embedded doorbell interrupt              */
2424
        /* XXX: TODO */
2425
        cpu_abort(env,
2426
                  "Embedded doorbell interrupt is not implemented yet !\n");
2427
        goto store_next;
2428
    case POWERPC_EXCP_DOORCI:    /* Embedded doorbell critical interrupt     */
2429
        switch (excp_model) {
2430
        case POWERPC_EXCP_BOOKE:
2431
            srr0 = SPR_BOOKE_CSRR0;
2432
            srr1 = SPR_BOOKE_CSRR1;
2433
            break;
2434
        default:
2435
            break;
2436
        }
2437
        /* XXX: TODO */
2438
        cpu_abort(env, "Embedded doorbell critical interrupt "
2439
                  "is not implemented yet !\n");
2440
        goto store_next;
2441
#endif /* defined(TARGET_PPCEMB) */
2442
    case POWERPC_EXCP_RESET:     /* System reset exception                   */
2443
        msr_ri = 0;
2444
#if defined(TARGET_PPC64H)
2445
        msr_hv = 1;
2446
#endif
2447
        goto store_next;
2448
#if defined(TARGET_PPC64)
2449
    case POWERPC_EXCP_DSEG:      /* Data segment exception                   */
2450
        msr_ri = 0;
2451
#if defined(TARGET_PPC64H)
2452
        if (lpes1 == 0)
2453
            msr_hv = 1;
2454
#endif
2455
        goto store_next;
2456
    case POWERPC_EXCP_ISEG:      /* Instruction segment exception            */
2457
        msr_ri = 0;
2458
#if defined(TARGET_PPC64H)
2459
        if (lpes1 == 0)
2460
            msr_hv = 1;
2461
#endif
2462
        goto store_next;
2463
#endif /* defined(TARGET_PPC64) */
2464
#if defined(TARGET_PPC64H)
2465
    case POWERPC_EXCP_HDECR:     /* Hypervisor decrementer exception         */
2466
        srr0 = SPR_HSRR0;
2467
        srr1 = SPR_HSSR1;
2468
        msr_hv = 1;
2469
        goto store_next;
2470
#endif
2471
    case POWERPC_EXCP_TRACE:     /* Trace exception                          */
2472
        msr_ri = 0;
2473
#if defined(TARGET_PPC64H)
2474
        if (lpes1 == 0)
2475
            msr_hv = 1;
2476
#endif
2477
        goto store_next;
2478
#if defined(TARGET_PPC64H)
2479
    case POWERPC_EXCP_HDSI:      /* Hypervisor data storage exception        */
2480
        srr0 = SPR_HSRR0;
2481
        srr1 = SPR_HSSR1;
2482
        msr_hv = 1;
2483
        goto store_next;
2484
    case POWERPC_EXCP_HISI:      /* Hypervisor instruction storage exception */
2485
        srr0 = SPR_HSRR0;
2486
        srr1 = SPR_HSSR1;
2487
        msr_hv = 1;
2488
        /* XXX: TODO */
2489
        cpu_abort(env, "Hypervisor instruction storage exception "
2490
                  "is not implemented yet !\n");
2491
        goto store_next;
2492
    case POWERPC_EXCP_HDSEG:     /* Hypervisor data segment exception        */
2493
        srr0 = SPR_HSRR0;
2494
        srr1 = SPR_HSSR1;
2495
        msr_hv = 1;
2496
        goto store_next;
2497
    case POWERPC_EXCP_HISEG:     /* Hypervisor instruction segment exception */
2498
        srr0 = SPR_HSRR0;
2499
        srr1 = SPR_HSSR1;
2500
        msr_hv = 1;
2501
        goto store_next;
2502
#endif /* defined(TARGET_PPC64H) */
2503
    case POWERPC_EXCP_VPU:       /* Vector unavailable exception             */
2504
        msr_ri = 0;
2505
#if defined(TARGET_PPC64H)
2506
        if (lpes1 == 0)
2507
            msr_hv = 1;
2508
#endif
2509
        goto store_current;
2510
    case POWERPC_EXCP_PIT:       /* Programmable interval timer interrupt    */
2511
#if defined (DEBUG_EXCEPTIONS)
2512
        if (loglevel != 0)
2513
            fprintf(logfile, "PIT exception\n");
2514
#endif
2515
        msr_ri = 0; /* XXX: check this */
2516
        goto store_next;
2517
    case POWERPC_EXCP_IO:        /* IO error exception                       */
2518
        /* XXX: TODO */
2519
        cpu_abort(env, "601 IO error exception is not implemented yet !\n");
2520
        goto store_next;
2521
    case POWERPC_EXCP_RUNM:      /* Run mode exception                       */
2522
        /* XXX: TODO */
2523
        cpu_abort(env, "601 run mode exception is not implemented yet !\n");
2524
        goto store_next;
2525
    case POWERPC_EXCP_EMUL:      /* Emulation trap exception                 */
2526
        /* XXX: TODO */
2527
        cpu_abort(env, "602 emulation trap exception "
2528
                  "is not implemented yet !\n");
2529
        goto store_next;
2530
    case POWERPC_EXCP_IFTLB:     /* Instruction fetch TLB error              */
2531
        msr_ri = 0; /* XXX: check this */
2532
#if defined(TARGET_PPC64H) /* XXX: check this */
2533
        if (lpes1 == 0)
2534
            msr_hv = 1;
2535
#endif
2536
        switch (excp_model) {
2537
        case POWERPC_EXCP_602:
2538
        case POWERPC_EXCP_603:
2539
        case POWERPC_EXCP_603E:
2540
        case POWERPC_EXCP_G2:
2541
            goto tlb_miss_tgpr;
2542
        case POWERPC_EXCP_7x5:
2543
            goto tlb_miss;
2544
        case POWERPC_EXCP_74xx:
2545
            goto tlb_miss_74xx;
2546
        default:
2547
            cpu_abort(env, "Invalid instruction TLB miss exception\n");
2548
            break;
2549
        }
2550
        break;
2551
    case POWERPC_EXCP_DLTLB:     /* Data load TLB miss                       */
2552
        msr_ri = 0; /* XXX: check this */
2553
#if defined(TARGET_PPC64H) /* XXX: check this */
2554
        if (lpes1 == 0)
2555
            msr_hv = 1;
2556
#endif
2557
        switch (excp_model) {
2558
        case POWERPC_EXCP_602:
2559
        case POWERPC_EXCP_603:
2560
        case POWERPC_EXCP_603E:
2561
        case POWERPC_EXCP_G2:
2562
            goto tlb_miss_tgpr;
2563
        case POWERPC_EXCP_7x5:
2564
            goto tlb_miss;
2565
        case POWERPC_EXCP_74xx:
2566
            goto tlb_miss_74xx;
2567
        default:
2568
            cpu_abort(env, "Invalid data load TLB miss exception\n");
2569
            break;
2570
        }
2571
        break;
2572
    case POWERPC_EXCP_DSTLB:     /* Data store TLB miss                      */
2573
        msr_ri = 0; /* XXX: check this */
2574
#if defined(TARGET_PPC64H) /* XXX: check this */
2575
        if (lpes1 == 0)
2576
            msr_hv = 1;
2577
#endif
2578
        switch (excp_model) {
2579
        case POWERPC_EXCP_602:
2580
        case POWERPC_EXCP_603:
2581
        case POWERPC_EXCP_603E:
2582
        case POWERPC_EXCP_G2:
2583
        tlb_miss_tgpr:
2584
            /* Swap temporary saved registers with GPRs */
2585
            swap_gpr_tgpr(env);
2586
            msr_tgpr = 1;
2587
            goto tlb_miss;
2588
        case POWERPC_EXCP_7x5:
2589
        tlb_miss:
2590
#if defined (DEBUG_SOFTWARE_TLB)
2591
            if (loglevel != 0) {
2592
                const unsigned char *es;
2593
                target_ulong *miss, *cmp;
2594
                int en;
2595
                if (excp == POWERPC_EXCP_IFTLB) {
2596
                    es = "I";
2597
                    en = 'I';
2598
                    miss = &env->spr[SPR_IMISS];
2599
                    cmp = &env->spr[SPR_ICMP];
2600
                } else {
2601
                    if (excp == POWERPC_EXCP_DLTLB)
2602
                        es = "DL";
2603
                    else
2604
                        es = "DS";
2605
                    en = 'D';
2606
                    miss = &env->spr[SPR_DMISS];
2607
                    cmp = &env->spr[SPR_DCMP];
2608
                }
2609
                fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
2610
                        " H1 " ADDRX " H2 " ADDRX " %08x\n",
2611
                        es, en, *miss, en, *cmp,
2612
                        env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2613
                        env->error_code);
2614
            }
2615
#endif
2616
            msr |= env->crf[0] << 28;
2617
            msr |= env->error_code; /* key, D/I, S/L bits */
2618
            /* Set way using a LRU mechanism */
2619
            msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
2620
            break;
2621
        case POWERPC_EXCP_74xx:
2622
        tlb_miss_74xx:
2623
#if defined (DEBUG_SOFTWARE_TLB)
2624
            if (loglevel != 0) {
2625
                const unsigned char *es;
2626
                target_ulong *miss, *cmp;
2627
                int en;
2628
                if (excp == POWERPC_EXCP_IFTLB) {
2629
                    es = "I";
2630
                    en = 'I';
2631
                    miss = &env->spr[SPR_IMISS];
2632
                    cmp = &env->spr[SPR_ICMP];
2633
                } else {
2634
                    if (excp == POWERPC_EXCP_DLTLB)
2635
                        es = "DL";
2636
                    else
2637
                        es = "DS";
2638
                    en = 'D';
2639
                    miss = &env->spr[SPR_TLBMISS];
2640
                    cmp = &env->spr[SPR_PTEHI];
2641
                }
2642
                fprintf(logfile, "74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
2643
                        " %08x\n",
2644
                        es, en, *miss, en, *cmp, env->error_code);
2645
            }
2646
#endif
2647
            msr |= env->error_code; /* key bit */
2648
            break;
2649
        default:
2650
            cpu_abort(env, "Invalid data store TLB miss exception\n");
2651
            break;
2652
        }
2653
        goto store_next;
2654
    case POWERPC_EXCP_FPA:       /* Floating-point assist exception          */
2655
        /* XXX: TODO */
2656
        cpu_abort(env, "Floating point assist exception "
2657
                  "is not implemented yet !\n");
2658
        goto store_next;
2659
    case POWERPC_EXCP_IABR:      /* Instruction address breakpoint           */
2660
        /* XXX: TODO */
2661
        cpu_abort(env, "IABR exception is not implemented yet !\n");
2662
        goto store_next;
2663
    case POWERPC_EXCP_SMI:       /* System management interrupt              */
2664
        /* XXX: TODO */
2665
        cpu_abort(env, "SMI exception is not implemented yet !\n");
2666
        goto store_next;
2667
    case POWERPC_EXCP_THERM:     /* Thermal interrupt                        */
2668
        /* XXX: TODO */
2669
        cpu_abort(env, "Thermal management exception "
2670
                  "is not implemented yet !\n");
2671
        goto store_next;
2672
    case POWERPC_EXCP_PERFM:     /* Embedded performance monitor interrupt   */
2673
        msr_ri = 0;
2674
#if defined(TARGET_PPC64H)
2675
        if (lpes1 == 0)
2676
            msr_hv = 1;
2677
#endif
2678
        /* XXX: TODO */
2679
        cpu_abort(env,
2680
                  "Performance counter exception is not implemented yet !\n");
2681
        goto store_next;
2682
    case POWERPC_EXCP_VPUA:      /* Vector assist exception                  */
2683
        /* XXX: TODO */
2684
        cpu_abort(env, "VPU assist exception is not implemented yet !\n");
2685
        goto store_next;
2686
    case POWERPC_EXCP_SOFTP:     /* Soft patch exception                     */
2687
        /* XXX: TODO */
2688
        cpu_abort(env,
2689
                  "970 soft-patch exception is not implemented yet !\n");
2690
        goto store_next;
2691
    case POWERPC_EXCP_MAINT:     /* Maintenance exception                    */
2692
        /* XXX: TODO */
2693
        cpu_abort(env,
2694
                  "970 maintenance exception is not implemented yet !\n");
2695
        goto store_next;
2696
    default:
2697
    excp_invalid:
2698
        cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
2699
        break;
2700
    store_current:
2701
        /* save current instruction location */
2702
        env->spr[srr0] = env->nip - 4;
2703
        break;
2704
    store_next:
2705
        /* save next instruction location */
2706
        env->spr[srr0] = env->nip;
2707
        break;
2708
    }
2709
    /* Save MSR */
2710
    env->spr[srr1] = msr;
2711
    /* If any alternate SRR register are defined, duplicate saved values */
2712
    if (asrr0 != -1)
2713
        env->spr[asrr0] = env->spr[srr0];
2714
    if (asrr1 != -1)
2715
        env->spr[asrr1] = env->spr[srr1];
2716
    /* If we disactivated any translation, flush TLBs */
2717
    if (msr_ir || msr_dr)
2718
        tlb_flush(env, 1);
2719
    /* reload MSR with correct bits */
2720
    msr_ee = 0;
2721
    msr_pr = 0;
2722
    msr_fp = 0;
2723
    msr_fe0 = 0;
2724
    msr_se = 0;
2725
    msr_be = 0;
2726
    msr_fe1 = 0;
2727
    msr_ir = 0;
2728
    msr_dr = 0;
2729
#if 0 /* Fix this: not on all targets */
2730
    msr_pmm = 0;
2731
#endif
2732
    msr_le = msr_ile;
2733
    do_compute_hflags(env);
2734
    /* Jump to handler */
2735
    vector = env->excp_vectors[excp];
2736
    if (vector == (target_ulong)-1) {
2737
        cpu_abort(env, "Raised an exception without defined vector %d\n",
2738
                  excp);
2739
    }
2740
    vector |= env->excp_prefix;
2741
#if defined(TARGET_PPC64)
2742
    if (excp_model == POWERPC_EXCP_BOOKE) {
2743
        msr_cm = msr_icm;
2744
        if (!msr_cm)
2745
            vector = (uint32_t)vector;
2746
    } else {
2747
        msr_sf = msr_isf;
2748
        if (!msr_sf)
2749
            vector = (uint32_t)vector;
2750
    }
2751
#endif
2752
    env->nip = vector;
2753
    /* Reset exception state */
2754
    env->exception_index = POWERPC_EXCP_NONE;
2755
    env->error_code = 0;
2756
}
2757

    
2758
void do_interrupt (CPUState *env)
2759
{
2760
    powerpc_excp(env, env->excp_model, env->exception_index);
2761
}
2762

    
2763
void ppc_hw_interrupt (CPUPPCState *env)
2764
{
2765
#if 1
2766
    if (loglevel & CPU_LOG_INT) {
2767
        fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
2768
                __func__, env, env->pending_interrupts,
2769
                env->interrupt_request, msr_me, msr_ee);
2770
    }
2771
#endif
2772
    /* External reset */
2773
    if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
2774
        env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
2775
        powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET);
2776
        return;
2777
    }
2778
    /* Machine check exception */
2779
    if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
2780
        env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
2781
        powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK);
2782
        return;
2783
    }
2784
#if 0 /* TODO */
2785
    /* External debug exception */
2786
    if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2787
        env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2788
        powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
2789
        return;
2790
    }
2791
#endif
2792
#if defined(TARGET_PPC64H)
2793
    if ((msr_ee != 0 || msr_hv == 0 || msr_pr == 1) & hdice != 0) {
2794
        /* Hypervisor decrementer exception */
2795
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
2796
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
2797
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR);
2798
            return;
2799
        }
2800
    }
2801
#endif
2802
    if (msr_ce != 0) {
2803
        /* External critical interrupt */
2804
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
2805
            /* Taking a critical external interrupt does not clear the external
2806
             * critical interrupt status
2807
             */
2808
#if 0
2809
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
2810
#endif
2811
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL);
2812
            return;
2813
        }
2814
    }
2815
    if (msr_ee != 0) {
2816
        /* Watchdog timer on embedded PowerPC */
2817
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2818
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2819
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT);
2820
            return;
2821
        }
2822
#if defined(TARGET_PPCEMB)
2823
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
2824
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
2825
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI);
2826
            return;
2827
        }
2828
#endif
2829
#if defined(TARGET_PPCEMB)
2830
        /* External interrupt */
2831
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2832
            /* Taking an external interrupt does not clear the external
2833
             * interrupt status
2834
             */
2835
#if 0
2836
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2837
#endif
2838
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2839
            return;
2840
        }
2841
#endif
2842
        /* Fixed interval timer on embedded PowerPC */
2843
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2844
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2845
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT);
2846
            return;
2847
        }
2848
        /* Programmable interval timer on embedded PowerPC */
2849
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2850
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2851
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT);
2852
            return;
2853
        }
2854
        /* Decrementer exception */
2855
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
2856
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
2857
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR);
2858
            return;
2859
        }
2860
#if !defined(TARGET_PPCEMB)
2861
        /* External interrupt */
2862
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2863
            /* Taking an external interrupt does not clear the external
2864
             * interrupt status
2865
             */
2866
#if 0
2867
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2868
#endif
2869
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2870
            return;
2871
        }
2872
#endif
2873
#if defined(TARGET_PPCEMB)
2874
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
2875
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
2876
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI);
2877
            return;
2878
        }
2879
#endif
2880
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
2881
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
2882
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM);
2883
            return;
2884
        }
2885
        /* Thermal interrupt */
2886
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2887
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2888
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM);
2889
            return;
2890
        }
2891
    }
2892
}
2893
#endif /* !CONFIG_USER_ONLY */
2894

    
2895
void cpu_dump_EA (target_ulong EA)
2896
{
2897
    FILE *f;
2898

    
2899
    if (logfile) {
2900
        f = logfile;
2901
    } else {
2902
        f = stdout;
2903
        return;
2904
    }
2905
    fprintf(f, "Memory access at address " ADDRX "\n", EA);
2906
}
2907

    
2908
void cpu_dump_rfi (target_ulong RA, target_ulong msr)
2909
{
2910
    FILE *f;
2911

    
2912
    if (logfile) {
2913
        f = logfile;
2914
    } else {
2915
        f = stdout;
2916
        return;
2917
    }
2918
    fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n",
2919
            RA, msr);
2920
}
2921

    
2922
void cpu_ppc_reset (void *opaque)
2923
{
2924
    CPUPPCState *env;
2925
    int i;
2926

    
2927
    env = opaque;
2928
    /* XXX: some of those flags initialisation values could depend
2929
     *      on the actual PowerPC implementation
2930
     */
2931
    for (i = 0; i < 63; i++)
2932
        env->msr[i] = 0;
2933
#if defined(TARGET_PPC64)
2934
    msr_hv = 0; /* Should be 1... */
2935
#endif
2936
    msr_ap = 0; /* TO BE CHECKED */
2937
    msr_sa = 0; /* TO BE CHECKED */
2938
    msr_ep = 1;
2939
#if defined (DO_SINGLE_STEP) && 0
2940
    /* Single step trace mode */
2941
    msr_se = 1;
2942
    msr_be = 1;
2943
#endif
2944
#if defined(CONFIG_USER_ONLY)
2945
    msr_fp = 1; /* Allow floating point exceptions */
2946
    msr_pr = 1;
2947
#else
2948
    env->nip = env->hreset_vector | env->excp_prefix;
2949
    if (env->mmu_model != POWERPC_MMU_REAL_4xx)
2950
        ppc_tlb_invalidate_all(env);
2951
#endif
2952
    do_compute_hflags(env);
2953
    env->reserve = -1;
2954
    /* Be sure no exception or interrupt is pending */
2955
    env->pending_interrupts = 0;
2956
    env->exception_index = POWERPC_EXCP_NONE;
2957
    env->error_code = 0;
2958
    /* Flush all TLBs */
2959
    tlb_flush(env, 1);
2960
}
2961

    
2962
CPUPPCState *cpu_ppc_init (void)
2963
{
2964
    CPUPPCState *env;
2965

    
2966
    env = qemu_mallocz(sizeof(CPUPPCState));
2967
    if (!env)
2968
        return NULL;
2969
    cpu_exec_init(env);
2970

    
2971
    return env;
2972
}
2973

    
2974
void cpu_ppc_close (CPUPPCState *env)
2975
{
2976
    /* Should also remove all opcode tables... */
2977
    free(env);
2978
}