Revision a1516744

b/target-alpha/translate.c
290 290

  
291 291
static always_inline void gen_bcond (DisasContext *ctx,
292 292
                                     TCGCond cond,
293
                                     int ra, int32_t disp16, int mask)
293
                                     int ra, int32_t disp, int mask)
294 294
{
295 295
    int l1, l2;
296 296

  
......
313 313
    tcg_gen_movi_i64(cpu_pc, ctx->pc);
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    tcg_gen_br(l2);
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    gen_set_label(l1);
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    tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2));
316
    tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp << 2));
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    gen_set_label(l2);
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}
319 319

  
......
2285 2285
        break;
2286 2286
    case 0x38:
2287 2287
        /* BLBC */
2288
        gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 1);
2288
        gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 1);
2289 2289
        ret = 1;
2290 2290
        break;
2291 2291
    case 0x39:
2292 2292
        /* BEQ */
2293
        gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 0);
2293
        gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 0);
2294 2294
        ret = 1;
2295 2295
        break;
2296 2296
    case 0x3A:
2297 2297
        /* BLT */
2298
        gen_bcond(ctx, TCG_COND_LT, ra, disp16, 0);
2298
        gen_bcond(ctx, TCG_COND_LT, ra, disp21, 0);
2299 2299
        ret = 1;
2300 2300
        break;
2301 2301
    case 0x3B:
2302 2302
        /* BLE */
2303
        gen_bcond(ctx, TCG_COND_LE, ra, disp16, 0);
2303
        gen_bcond(ctx, TCG_COND_LE, ra, disp21, 0);
2304 2304
        ret = 1;
2305 2305
        break;
2306 2306
    case 0x3C:
2307 2307
        /* BLBS */
2308
        gen_bcond(ctx, TCG_COND_NE, ra, disp16, 1);
2308
        gen_bcond(ctx, TCG_COND_NE, ra, disp21, 1);
2309 2309
        ret = 1;
2310 2310
        break;
2311 2311
    case 0x3D:
2312 2312
        /* BNE */
2313
        gen_bcond(ctx, TCG_COND_NE, ra, disp16, 0);
2313
        gen_bcond(ctx, TCG_COND_NE, ra, disp21, 0);
2314 2314
        ret = 1;
2315 2315
        break;
2316 2316
    case 0x3E:
2317 2317
        /* BGE */
2318
        gen_bcond(ctx, TCG_COND_GE, ra, disp16, 0);
2318
        gen_bcond(ctx, TCG_COND_GE, ra, disp21, 0);
2319 2319
        ret = 1;
2320 2320
        break;
2321 2321
    case 0x3F:
2322 2322
        /* BGT */
2323
        gen_bcond(ctx, TCG_COND_GT, ra, disp16, 0);
2323
        gen_bcond(ctx, TCG_COND_GT, ra, disp21, 0);
2324 2324
        ret = 1;
2325 2325
        break;
2326 2326
    invalid_opc:

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