Revision a158f92f
b/hw/xio3130_upstream.c | ||
---|---|---|
41 | 41 |
pci_bridge_write_config(d, address, val, len); |
42 | 42 |
pcie_cap_flr_write_config(d, address, val, len); |
43 | 43 |
msi_write_config(d, address, val, len); |
44 |
/* TODO: AER */
|
|
44 |
pcie_aer_write_config(d, address, val, len);
|
|
45 | 45 |
} |
46 | 46 |
|
47 | 47 |
static void xio3130_upstream_reset(DeviceState *qdev) |
... | ... | |
57 | 57 |
PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); |
58 | 58 |
PCIEPort *p = DO_UPCAST(PCIEPort, br, br); |
59 | 59 |
int rc; |
60 |
int tmp; |
|
60 | 61 |
|
61 | 62 |
rc = pci_bridge_initfn(d); |
62 | 63 |
if (rc < 0) { |
... | ... | |
72 | 73 |
XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, |
73 | 74 |
XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); |
74 | 75 |
if (rc < 0) { |
75 |
return rc;
|
|
76 |
goto err_bridge;
|
|
76 | 77 |
} |
77 | 78 |
rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, |
78 | 79 |
XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); |
79 | 80 |
if (rc < 0) { |
80 |
return rc;
|
|
81 |
goto err_bridge;
|
|
81 | 82 |
} |
82 | 83 |
rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, |
83 | 84 |
p->port); |
84 | 85 |
if (rc < 0) { |
85 |
return rc;
|
|
86 |
goto err_msi;
|
|
86 | 87 |
} |
87 | 88 |
|
88 | 89 |
/* TODO: implement FLR */ |
89 | 90 |
pcie_cap_flr_init(d); |
90 | 91 |
|
91 | 92 |
pcie_cap_deverr_init(d); |
92 |
/* TODO: AER */ |
|
93 |
rc = pcie_aer_init(d, XIO3130_AER_OFFSET); |
|
94 |
if (rc < 0) { |
|
95 |
goto err; |
|
96 |
} |
|
93 | 97 |
|
94 | 98 |
return 0; |
99 |
|
|
100 |
err: |
|
101 |
pcie_cap_exit(d); |
|
102 |
err_msi: |
|
103 |
msi_uninit(d); |
|
104 |
err_bridge: |
|
105 |
tmp = pci_bridge_exitfn(d); |
|
106 |
assert(!tmp); |
|
107 |
return rc; |
|
95 | 108 |
} |
96 | 109 |
|
97 | 110 |
static int xio3130_upstream_exitfn(PCIDevice *d) |
98 | 111 |
{ |
99 |
/* TODO: AER */ |
|
100 |
msi_uninit(d); |
|
112 |
pcie_aer_exit(d); |
|
101 | 113 |
pcie_cap_exit(d); |
114 |
msi_uninit(d); |
|
102 | 115 |
return pci_bridge_exitfn(d); |
103 | 116 |
} |
104 | 117 |
|
... | ... | |
131 | 144 |
.minimum_version_id_old = 1, |
132 | 145 |
.fields = (VMStateField[]) { |
133 | 146 |
VMSTATE_PCIE_DEVICE(br.dev, PCIEPort), |
134 |
/* TODO: AER */ |
|
147 |
VMSTATE_STRUCT(br.dev.exp.aer_log, PCIEPort, 0, vmstate_pcie_aer_log, |
|
148 |
PCIEAERLog), |
|
135 | 149 |
VMSTATE_END_OF_LIST() |
136 | 150 |
} |
137 | 151 |
}; |
... | ... | |
151 | 165 |
|
152 | 166 |
.qdev.props = (Property[]) { |
153 | 167 |
DEFINE_PROP_UINT8("port", PCIEPort, port, 0), |
154 |
/* TODO: AER */ |
|
168 |
DEFINE_PROP_UINT16("aer_log_max", PCIEPort, br.dev.exp.aer_log.log_max, |
|
169 |
PCIE_AER_LOG_MAX_DEFAULT), |
|
155 | 170 |
DEFINE_PROP_END_OF_LIST(), |
156 | 171 |
} |
157 | 172 |
}; |
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