root / hw / pxa2xx_timer.c @ a171fe39
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1 | a171fe39 | balrog | /*
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2 | a171fe39 | balrog | * Intel XScale PXA255/270 OS Timers.
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3 | a171fe39 | balrog | *
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4 | a171fe39 | balrog | * Copyright (c) 2006 Openedhand Ltd.
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5 | a171fe39 | balrog | * Copyright (c) 2006 Thorsten Zitterell
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6 | a171fe39 | balrog | *
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7 | a171fe39 | balrog | * This code is licenced under the GPL.
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8 | a171fe39 | balrog | */
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9 | a171fe39 | balrog | |
10 | a171fe39 | balrog | #include "vl.h" |
11 | a171fe39 | balrog | |
12 | a171fe39 | balrog | #define OSMR0 0x00 |
13 | a171fe39 | balrog | #define OSMR1 0x04 |
14 | a171fe39 | balrog | #define OSMR2 0x08 |
15 | a171fe39 | balrog | #define OSMR3 0x0c |
16 | a171fe39 | balrog | #define OSMR4 0x80 |
17 | a171fe39 | balrog | #define OSMR5 0x84 |
18 | a171fe39 | balrog | #define OSMR6 0x88 |
19 | a171fe39 | balrog | #define OSMR7 0x8c |
20 | a171fe39 | balrog | #define OSMR8 0x90 |
21 | a171fe39 | balrog | #define OSMR9 0x94 |
22 | a171fe39 | balrog | #define OSMR10 0x98 |
23 | a171fe39 | balrog | #define OSMR11 0x9c |
24 | a171fe39 | balrog | #define OSCR 0x10 /* OS Timer Count */ |
25 | a171fe39 | balrog | #define OSCR4 0x40 |
26 | a171fe39 | balrog | #define OSCR5 0x44 |
27 | a171fe39 | balrog | #define OSCR6 0x48 |
28 | a171fe39 | balrog | #define OSCR7 0x4c |
29 | a171fe39 | balrog | #define OSCR8 0x50 |
30 | a171fe39 | balrog | #define OSCR9 0x54 |
31 | a171fe39 | balrog | #define OSCR10 0x58 |
32 | a171fe39 | balrog | #define OSCR11 0x5c |
33 | a171fe39 | balrog | #define OSSR 0x14 /* Timer status register */ |
34 | a171fe39 | balrog | #define OWER 0x18 |
35 | a171fe39 | balrog | #define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */ |
36 | a171fe39 | balrog | #define OMCR4 0xc0 /* OS Match Control registers */ |
37 | a171fe39 | balrog | #define OMCR5 0xc4 |
38 | a171fe39 | balrog | #define OMCR6 0xc8 |
39 | a171fe39 | balrog | #define OMCR7 0xcc |
40 | a171fe39 | balrog | #define OMCR8 0xd0 |
41 | a171fe39 | balrog | #define OMCR9 0xd4 |
42 | a171fe39 | balrog | #define OMCR10 0xd8 |
43 | a171fe39 | balrog | #define OMCR11 0xdc |
44 | a171fe39 | balrog | #define OSNR 0x20 |
45 | a171fe39 | balrog | |
46 | a171fe39 | balrog | #define PXA25X_FREQ 3686400 /* 3.6864 MHz */ |
47 | a171fe39 | balrog | #define PXA27X_FREQ 3250000 /* 3.25 MHz */ |
48 | a171fe39 | balrog | |
49 | a171fe39 | balrog | static int pxa2xx_timer4_freq[8] = { |
50 | a171fe39 | balrog | [0] = 0, |
51 | a171fe39 | balrog | [1] = 32768, |
52 | a171fe39 | balrog | [2] = 1000, |
53 | a171fe39 | balrog | [3] = 1, |
54 | a171fe39 | balrog | [4] = 1000000, |
55 | a171fe39 | balrog | /* [5] is the "Externally supplied clock". Assign if necessary. */
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56 | a171fe39 | balrog | [5 ... 7] = 0, |
57 | a171fe39 | balrog | }; |
58 | a171fe39 | balrog | |
59 | a171fe39 | balrog | struct pxa2xx_timer0_s {
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60 | a171fe39 | balrog | uint32_t value; |
61 | a171fe39 | balrog | int level;
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62 | a171fe39 | balrog | qemu_irq irq; |
63 | a171fe39 | balrog | QEMUTimer *qtimer; |
64 | a171fe39 | balrog | int num;
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65 | a171fe39 | balrog | void *info;
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66 | a171fe39 | balrog | }; |
67 | a171fe39 | balrog | |
68 | a171fe39 | balrog | struct pxa2xx_timer4_s {
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69 | a171fe39 | balrog | uint32_t value; |
70 | a171fe39 | balrog | int level;
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71 | a171fe39 | balrog | qemu_irq irq; |
72 | a171fe39 | balrog | QEMUTimer *qtimer; |
73 | a171fe39 | balrog | int num;
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74 | a171fe39 | balrog | void *info;
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75 | a171fe39 | balrog | int32_t oldclock; |
76 | a171fe39 | balrog | int32_t clock; |
77 | a171fe39 | balrog | uint64_t lastload; |
78 | a171fe39 | balrog | uint32_t freq; |
79 | a171fe39 | balrog | uint32_t control; |
80 | a171fe39 | balrog | }; |
81 | a171fe39 | balrog | |
82 | a171fe39 | balrog | typedef struct { |
83 | a171fe39 | balrog | uint32_t base; |
84 | a171fe39 | balrog | int32_t clock; |
85 | a171fe39 | balrog | int32_t oldclock; |
86 | a171fe39 | balrog | uint64_t lastload; |
87 | a171fe39 | balrog | uint32_t freq; |
88 | a171fe39 | balrog | struct pxa2xx_timer0_s timer[4]; |
89 | a171fe39 | balrog | struct pxa2xx_timer4_s *tm4;
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90 | a171fe39 | balrog | uint32_t events; |
91 | a171fe39 | balrog | uint32_t irq_enabled; |
92 | a171fe39 | balrog | uint32_t reset3; |
93 | a171fe39 | balrog | CPUState *cpustate; |
94 | a171fe39 | balrog | int64_t qemu_ticks; |
95 | a171fe39 | balrog | uint32_t snapshot; |
96 | a171fe39 | balrog | } pxa2xx_timer_info; |
97 | a171fe39 | balrog | |
98 | a171fe39 | balrog | static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu) |
99 | a171fe39 | balrog | { |
100 | a171fe39 | balrog | pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque; |
101 | a171fe39 | balrog | int i;
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102 | a171fe39 | balrog | uint32_t now_vm; |
103 | a171fe39 | balrog | uint64_t new_qemu; |
104 | a171fe39 | balrog | |
105 | a171fe39 | balrog | now_vm = s->clock + |
106 | a171fe39 | balrog | muldiv64(now_qemu - s->lastload, s->freq, ticks_per_sec); |
107 | a171fe39 | balrog | |
108 | a171fe39 | balrog | for (i = 0; i < 4; i ++) { |
109 | a171fe39 | balrog | new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm), |
110 | a171fe39 | balrog | ticks_per_sec, s->freq); |
111 | a171fe39 | balrog | qemu_mod_timer(s->timer[i].qtimer, new_qemu); |
112 | a171fe39 | balrog | } |
113 | a171fe39 | balrog | } |
114 | a171fe39 | balrog | |
115 | a171fe39 | balrog | static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n) |
116 | a171fe39 | balrog | { |
117 | a171fe39 | balrog | pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque; |
118 | a171fe39 | balrog | uint32_t now_vm; |
119 | a171fe39 | balrog | uint64_t new_qemu; |
120 | a171fe39 | balrog | static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 }; |
121 | a171fe39 | balrog | int counter;
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122 | a171fe39 | balrog | |
123 | a171fe39 | balrog | if (s->tm4[n].control & (1 << 7)) |
124 | a171fe39 | balrog | counter = n; |
125 | a171fe39 | balrog | else
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126 | a171fe39 | balrog | counter = counters[n]; |
127 | a171fe39 | balrog | |
128 | a171fe39 | balrog | if (!s->tm4[counter].freq) {
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129 | a171fe39 | balrog | qemu_del_timer(s->timer[n].qtimer); |
130 | a171fe39 | balrog | return;
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131 | a171fe39 | balrog | } |
132 | a171fe39 | balrog | |
133 | a171fe39 | balrog | now_vm = s->tm4[counter].clock + muldiv64(now_qemu - |
134 | a171fe39 | balrog | s->tm4[counter].lastload, |
135 | a171fe39 | balrog | s->tm4[counter].freq, ticks_per_sec); |
136 | a171fe39 | balrog | |
137 | a171fe39 | balrog | new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].value - now_vm), |
138 | a171fe39 | balrog | ticks_per_sec, s->tm4[counter].freq); |
139 | a171fe39 | balrog | qemu_mod_timer(s->timer[n].qtimer, new_qemu); |
140 | a171fe39 | balrog | } |
141 | a171fe39 | balrog | |
142 | a171fe39 | balrog | static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset) |
143 | a171fe39 | balrog | { |
144 | a171fe39 | balrog | pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque; |
145 | a171fe39 | balrog | int tm = 0; |
146 | a171fe39 | balrog | |
147 | a171fe39 | balrog | offset -= s->base; |
148 | a171fe39 | balrog | |
149 | a171fe39 | balrog | switch (offset) {
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150 | a171fe39 | balrog | case OSMR3: tm ++;
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151 | a171fe39 | balrog | case OSMR2: tm ++;
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152 | a171fe39 | balrog | case OSMR1: tm ++;
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153 | a171fe39 | balrog | case OSMR0:
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154 | a171fe39 | balrog | return s->timer[tm].value;
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155 | a171fe39 | balrog | case OSMR11: tm ++;
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156 | a171fe39 | balrog | case OSMR10: tm ++;
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157 | a171fe39 | balrog | case OSMR9: tm ++;
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158 | a171fe39 | balrog | case OSMR8: tm ++;
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159 | a171fe39 | balrog | case OSMR7: tm ++;
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160 | a171fe39 | balrog | case OSMR6: tm ++;
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161 | a171fe39 | balrog | case OSMR5: tm ++;
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162 | a171fe39 | balrog | case OSMR4:
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163 | a171fe39 | balrog | if (!s->tm4)
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164 | a171fe39 | balrog | goto badreg;
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165 | a171fe39 | balrog | return s->tm4[tm].value;
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166 | a171fe39 | balrog | case OSCR:
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167 | a171fe39 | balrog | return s->clock + muldiv64(qemu_get_clock(vm_clock) -
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168 | a171fe39 | balrog | s->lastload, s->freq, ticks_per_sec); |
169 | a171fe39 | balrog | case OSCR11: tm ++;
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170 | a171fe39 | balrog | case OSCR10: tm ++;
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171 | a171fe39 | balrog | case OSCR9: tm ++;
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172 | a171fe39 | balrog | case OSCR8: tm ++;
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173 | a171fe39 | balrog | case OSCR7: tm ++;
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174 | a171fe39 | balrog | case OSCR6: tm ++;
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175 | a171fe39 | balrog | case OSCR5: tm ++;
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176 | a171fe39 | balrog | case OSCR4:
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177 | a171fe39 | balrog | if (!s->tm4)
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178 | a171fe39 | balrog | goto badreg;
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179 | a171fe39 | balrog | |
180 | a171fe39 | balrog | if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) { |
181 | a171fe39 | balrog | if (s->tm4[tm - 1].freq) |
182 | a171fe39 | balrog | s->snapshot = s->tm4[tm - 1].clock + muldiv64(
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183 | a171fe39 | balrog | qemu_get_clock(vm_clock) - |
184 | a171fe39 | balrog | s->tm4[tm - 1].lastload,
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185 | a171fe39 | balrog | s->tm4[tm - 1].freq, ticks_per_sec);
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186 | a171fe39 | balrog | else
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187 | a171fe39 | balrog | s->snapshot = s->tm4[tm - 1].clock;
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188 | a171fe39 | balrog | } |
189 | a171fe39 | balrog | |
190 | a171fe39 | balrog | if (!s->tm4[tm].freq)
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191 | a171fe39 | balrog | return s->tm4[tm].clock;
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192 | a171fe39 | balrog | return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) -
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193 | a171fe39 | balrog | s->tm4[tm].lastload, s->tm4[tm].freq, ticks_per_sec); |
194 | a171fe39 | balrog | case OIER:
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195 | a171fe39 | balrog | return s->irq_enabled;
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196 | a171fe39 | balrog | case OSSR: /* Status register */ |
197 | a171fe39 | balrog | return s->events;
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198 | a171fe39 | balrog | case OWER:
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199 | a171fe39 | balrog | return s->reset3;
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200 | a171fe39 | balrog | case OMCR11: tm ++;
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201 | a171fe39 | balrog | case OMCR10: tm ++;
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202 | a171fe39 | balrog | case OMCR9: tm ++;
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203 | a171fe39 | balrog | case OMCR8: tm ++;
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204 | a171fe39 | balrog | case OMCR7: tm ++;
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205 | a171fe39 | balrog | case OMCR6: tm ++;
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206 | a171fe39 | balrog | case OMCR5: tm ++;
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207 | a171fe39 | balrog | case OMCR4:
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208 | a171fe39 | balrog | if (!s->tm4)
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209 | a171fe39 | balrog | goto badreg;
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210 | a171fe39 | balrog | return s->tm4[tm].control;
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211 | a171fe39 | balrog | case OSNR:
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212 | a171fe39 | balrog | return s->snapshot;
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213 | a171fe39 | balrog | default:
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214 | a171fe39 | balrog | badreg:
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215 | a171fe39 | balrog | cpu_abort(cpu_single_env, "pxa2xx_timer_read: Bad offset "
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216 | a171fe39 | balrog | REG_FMT "\n", offset);
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217 | a171fe39 | balrog | } |
218 | a171fe39 | balrog | |
219 | a171fe39 | balrog | return 0; |
220 | a171fe39 | balrog | } |
221 | a171fe39 | balrog | |
222 | a171fe39 | balrog | static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset, |
223 | a171fe39 | balrog | uint32_t value) |
224 | a171fe39 | balrog | { |
225 | a171fe39 | balrog | int i, tm = 0; |
226 | a171fe39 | balrog | pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque; |
227 | a171fe39 | balrog | |
228 | a171fe39 | balrog | offset -= s->base; |
229 | a171fe39 | balrog | |
230 | a171fe39 | balrog | switch (offset) {
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231 | a171fe39 | balrog | case OSMR3: tm ++;
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232 | a171fe39 | balrog | case OSMR2: tm ++;
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233 | a171fe39 | balrog | case OSMR1: tm ++;
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234 | a171fe39 | balrog | case OSMR0:
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235 | a171fe39 | balrog | s->timer[tm].value = value; |
236 | a171fe39 | balrog | pxa2xx_timer_update(s, qemu_get_clock(vm_clock)); |
237 | a171fe39 | balrog | break;
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238 | a171fe39 | balrog | case OSMR11: tm ++;
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239 | a171fe39 | balrog | case OSMR10: tm ++;
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240 | a171fe39 | balrog | case OSMR9: tm ++;
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241 | a171fe39 | balrog | case OSMR8: tm ++;
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242 | a171fe39 | balrog | case OSMR7: tm ++;
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243 | a171fe39 | balrog | case OSMR6: tm ++;
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244 | a171fe39 | balrog | case OSMR5: tm ++;
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245 | a171fe39 | balrog | case OSMR4:
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246 | a171fe39 | balrog | if (!s->tm4)
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247 | a171fe39 | balrog | goto badreg;
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248 | a171fe39 | balrog | s->tm4[tm].value = value; |
249 | a171fe39 | balrog | pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); |
250 | a171fe39 | balrog | break;
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251 | a171fe39 | balrog | case OSCR:
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252 | a171fe39 | balrog | s->oldclock = s->clock; |
253 | a171fe39 | balrog | s->lastload = qemu_get_clock(vm_clock); |
254 | a171fe39 | balrog | s->clock = value; |
255 | a171fe39 | balrog | pxa2xx_timer_update(s, s->lastload); |
256 | a171fe39 | balrog | break;
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257 | a171fe39 | balrog | case OSCR11: tm ++;
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258 | a171fe39 | balrog | case OSCR10: tm ++;
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259 | a171fe39 | balrog | case OSCR9: tm ++;
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260 | a171fe39 | balrog | case OSCR8: tm ++;
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261 | a171fe39 | balrog | case OSCR7: tm ++;
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262 | a171fe39 | balrog | case OSCR6: tm ++;
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263 | a171fe39 | balrog | case OSCR5: tm ++;
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264 | a171fe39 | balrog | case OSCR4:
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265 | a171fe39 | balrog | if (!s->tm4)
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266 | a171fe39 | balrog | goto badreg;
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267 | a171fe39 | balrog | s->tm4[tm].oldclock = s->tm4[tm].clock; |
268 | a171fe39 | balrog | s->tm4[tm].lastload = qemu_get_clock(vm_clock); |
269 | a171fe39 | balrog | s->tm4[tm].clock = value; |
270 | a171fe39 | balrog | pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm); |
271 | a171fe39 | balrog | break;
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272 | a171fe39 | balrog | case OIER:
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273 | a171fe39 | balrog | s->irq_enabled = value & 0xfff;
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274 | a171fe39 | balrog | break;
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275 | a171fe39 | balrog | case OSSR: /* Status register */ |
276 | a171fe39 | balrog | s->events &= ~value; |
277 | a171fe39 | balrog | for (i = 0; i < 4; i ++, value >>= 1) { |
278 | a171fe39 | balrog | if (s->timer[i].level && (value & 1)) { |
279 | a171fe39 | balrog | s->timer[i].level = 0;
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280 | a171fe39 | balrog | qemu_irq_lower(s->timer[i].irq); |
281 | a171fe39 | balrog | } |
282 | a171fe39 | balrog | } |
283 | a171fe39 | balrog | if (s->tm4) {
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284 | a171fe39 | balrog | for (i = 0; i < 8; i ++, value >>= 1) |
285 | a171fe39 | balrog | if (s->tm4[i].level && (value & 1)) |
286 | a171fe39 | balrog | s->tm4[i].level = 0;
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287 | a171fe39 | balrog | if (!(s->events & 0xff0)) |
288 | a171fe39 | balrog | qemu_irq_lower(s->tm4->irq); |
289 | a171fe39 | balrog | } |
290 | a171fe39 | balrog | break;
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291 | a171fe39 | balrog | case OWER: /* XXX: Reset on OSMR3 match? */ |
292 | a171fe39 | balrog | s->reset3 = value; |
293 | a171fe39 | balrog | break;
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294 | a171fe39 | balrog | case OMCR7: tm ++;
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295 | a171fe39 | balrog | case OMCR6: tm ++;
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296 | a171fe39 | balrog | case OMCR5: tm ++;
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297 | a171fe39 | balrog | case OMCR4:
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298 | a171fe39 | balrog | if (!s->tm4)
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299 | a171fe39 | balrog | goto badreg;
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300 | a171fe39 | balrog | s->tm4[tm].control = value & 0x0ff;
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301 | a171fe39 | balrog | /* XXX Stop if running (shouldn't happen) */
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302 | a171fe39 | balrog | if ((value & (1 << 7)) || tm == 0) |
303 | a171fe39 | balrog | s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
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304 | a171fe39 | balrog | else {
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305 | a171fe39 | balrog | s->tm4[tm].freq = 0;
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306 | a171fe39 | balrog | pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); |
307 | a171fe39 | balrog | } |
308 | a171fe39 | balrog | break;
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309 | a171fe39 | balrog | case OMCR11: tm ++;
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310 | a171fe39 | balrog | case OMCR10: tm ++;
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311 | a171fe39 | balrog | case OMCR9: tm ++;
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312 | a171fe39 | balrog | case OMCR8: tm += 4; |
313 | a171fe39 | balrog | if (!s->tm4)
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314 | a171fe39 | balrog | goto badreg;
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315 | a171fe39 | balrog | s->tm4[tm].control = value & 0x3ff;
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316 | a171fe39 | balrog | /* XXX Stop if running (shouldn't happen) */
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317 | a171fe39 | balrog | if ((value & (1 << 7)) || !(tm & 1)) |
318 | a171fe39 | balrog | s->tm4[tm].freq = |
319 | a171fe39 | balrog | pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)]; |
320 | a171fe39 | balrog | else {
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321 | a171fe39 | balrog | s->tm4[tm].freq = 0;
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322 | a171fe39 | balrog | pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm); |
323 | a171fe39 | balrog | } |
324 | a171fe39 | balrog | break;
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325 | a171fe39 | balrog | default:
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326 | a171fe39 | balrog | badreg:
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327 | a171fe39 | balrog | cpu_abort(cpu_single_env, "pxa2xx_timer_write: Bad offset "
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328 | a171fe39 | balrog | REG_FMT "\n", offset);
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329 | a171fe39 | balrog | } |
330 | a171fe39 | balrog | } |
331 | a171fe39 | balrog | |
332 | a171fe39 | balrog | static CPUReadMemoryFunc *pxa2xx_timer_readfn[] = {
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333 | a171fe39 | balrog | pxa2xx_timer_read, |
334 | a171fe39 | balrog | pxa2xx_timer_read, |
335 | a171fe39 | balrog | pxa2xx_timer_read, |
336 | a171fe39 | balrog | }; |
337 | a171fe39 | balrog | |
338 | a171fe39 | balrog | static CPUWriteMemoryFunc *pxa2xx_timer_writefn[] = {
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339 | a171fe39 | balrog | pxa2xx_timer_write, |
340 | a171fe39 | balrog | pxa2xx_timer_write, |
341 | a171fe39 | balrog | pxa2xx_timer_write, |
342 | a171fe39 | balrog | }; |
343 | a171fe39 | balrog | |
344 | a171fe39 | balrog | static void pxa2xx_timer_tick(void *opaque) |
345 | a171fe39 | balrog | { |
346 | a171fe39 | balrog | struct pxa2xx_timer0_s *t = (struct pxa2xx_timer0_s *) opaque; |
347 | a171fe39 | balrog | pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info; |
348 | a171fe39 | balrog | |
349 | a171fe39 | balrog | if (i->irq_enabled & (1 << t->num)) { |
350 | a171fe39 | balrog | t->level = 1;
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351 | a171fe39 | balrog | i->events |= 1 << t->num;
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352 | a171fe39 | balrog | qemu_irq_raise(t->irq); |
353 | a171fe39 | balrog | } |
354 | a171fe39 | balrog | |
355 | a171fe39 | balrog | if (t->num == 3) |
356 | a171fe39 | balrog | if (i->reset3 & 1) { |
357 | a171fe39 | balrog | i->reset3 = 0;
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358 | a171fe39 | balrog | cpu_reset(i->cpustate); |
359 | a171fe39 | balrog | } |
360 | a171fe39 | balrog | } |
361 | a171fe39 | balrog | |
362 | a171fe39 | balrog | static void pxa2xx_timer_tick4(void *opaque) |
363 | a171fe39 | balrog | { |
364 | a171fe39 | balrog | struct pxa2xx_timer4_s *t = (struct pxa2xx_timer4_s *) opaque; |
365 | a171fe39 | balrog | pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info; |
366 | a171fe39 | balrog | |
367 | a171fe39 | balrog | pxa2xx_timer_tick4(opaque); |
368 | a171fe39 | balrog | if (t->control & (1 << 3)) |
369 | a171fe39 | balrog | t->clock = 0;
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370 | a171fe39 | balrog | if (t->control & (1 << 6)) |
371 | a171fe39 | balrog | pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->num - 4);
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372 | a171fe39 | balrog | } |
373 | a171fe39 | balrog | |
374 | a171fe39 | balrog | static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
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375 | a171fe39 | balrog | qemu_irq *irqs, CPUState *cpustate) |
376 | a171fe39 | balrog | { |
377 | a171fe39 | balrog | int i;
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378 | a171fe39 | balrog | int iomemtype;
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379 | a171fe39 | balrog | pxa2xx_timer_info *s; |
380 | a171fe39 | balrog | |
381 | a171fe39 | balrog | s = (pxa2xx_timer_info *) qemu_mallocz(sizeof(pxa2xx_timer_info));
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382 | a171fe39 | balrog | s->base = base; |
383 | a171fe39 | balrog | s->irq_enabled = 0;
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384 | a171fe39 | balrog | s->oldclock = 0;
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385 | a171fe39 | balrog | s->clock = 0;
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386 | a171fe39 | balrog | s->lastload = qemu_get_clock(vm_clock); |
387 | a171fe39 | balrog | s->reset3 = 0;
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388 | a171fe39 | balrog | s->cpustate = cpustate; |
389 | a171fe39 | balrog | |
390 | a171fe39 | balrog | for (i = 0; i < 4; i ++) { |
391 | a171fe39 | balrog | s->timer[i].value = 0;
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392 | a171fe39 | balrog | s->timer[i].irq = irqs[i]; |
393 | a171fe39 | balrog | s->timer[i].info = s; |
394 | a171fe39 | balrog | s->timer[i].num = i; |
395 | a171fe39 | balrog | s->timer[i].level = 0;
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396 | a171fe39 | balrog | s->timer[i].qtimer = qemu_new_timer(vm_clock, |
397 | a171fe39 | balrog | pxa2xx_timer_tick, &s->timer[i]); |
398 | a171fe39 | balrog | } |
399 | a171fe39 | balrog | |
400 | a171fe39 | balrog | iomemtype = cpu_register_io_memory(0, pxa2xx_timer_readfn,
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401 | a171fe39 | balrog | pxa2xx_timer_writefn, s); |
402 | a171fe39 | balrog | cpu_register_physical_memory(base, 0x00000fff, iomemtype);
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403 | a171fe39 | balrog | return s;
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404 | a171fe39 | balrog | } |
405 | a171fe39 | balrog | |
406 | a171fe39 | balrog | void pxa25x_timer_init(target_phys_addr_t base,
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407 | a171fe39 | balrog | qemu_irq *irqs, CPUState *cpustate) |
408 | a171fe39 | balrog | { |
409 | a171fe39 | balrog | pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs, cpustate); |
410 | a171fe39 | balrog | s->freq = PXA25X_FREQ; |
411 | a171fe39 | balrog | s->tm4 = 0;
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412 | a171fe39 | balrog | } |
413 | a171fe39 | balrog | |
414 | a171fe39 | balrog | void pxa27x_timer_init(target_phys_addr_t base,
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415 | a171fe39 | balrog | qemu_irq *irqs, qemu_irq irq4, CPUState *cpustate) |
416 | a171fe39 | balrog | { |
417 | a171fe39 | balrog | pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs, cpustate); |
418 | a171fe39 | balrog | int i;
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419 | a171fe39 | balrog | s->freq = PXA27X_FREQ; |
420 | a171fe39 | balrog | s->tm4 = (struct pxa2xx_timer4_s *) qemu_mallocz(8 * |
421 | a171fe39 | balrog | sizeof(struct pxa2xx_timer4_s)); |
422 | a171fe39 | balrog | for (i = 0; i < 8; i ++) { |
423 | a171fe39 | balrog | s->tm4[i].value = 0;
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424 | a171fe39 | balrog | s->tm4[i].irq = irq4; |
425 | a171fe39 | balrog | s->tm4[i].info = s; |
426 | a171fe39 | balrog | s->tm4[i].num = i + 4;
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427 | a171fe39 | balrog | s->tm4[i].level = 0;
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428 | a171fe39 | balrog | s->tm4[i].freq = 0;
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429 | a171fe39 | balrog | s->tm4[i].control = 0x0;
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430 | a171fe39 | balrog | s->tm4[i].qtimer = qemu_new_timer(vm_clock, |
431 | a171fe39 | balrog | pxa2xx_timer_tick4, &s->tm4[i]); |
432 | a171fe39 | balrog | } |
433 | a171fe39 | balrog | } |