root / hw / pxa2xx.c @ a171fe39
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/*
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* Intel XScale PXA255/270 processor support.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Written by Andrzej Zaborowski <balrog@zabor.org>
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*
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* This code is licenced under the GPL.
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*/
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|
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# include "vl.h" |
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|
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static struct { |
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target_phys_addr_t io_base; |
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int irqn;
|
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} pxa255_serial[] = { |
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{ 0x40100000, PXA2XX_PIC_FFUART },
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{ 0x40200000, PXA2XX_PIC_BTUART },
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{ 0x40700000, PXA2XX_PIC_STUART },
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{ 0x41600000, PXA25X_PIC_HWUART },
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{ 0, 0 } |
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}, pxa270_serial[] = { |
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{ 0x40100000, PXA2XX_PIC_FFUART },
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{ 0x40200000, PXA2XX_PIC_BTUART },
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{ 0x40700000, PXA2XX_PIC_STUART },
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{ 0, 0 } |
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}; |
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|
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static struct { |
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target_phys_addr_t io_base; |
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int irqn;
|
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} pxa250_ssp[] = { |
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{ 0x41000000, PXA2XX_PIC_SSP },
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{ 0, 0 } |
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}, pxa255_ssp[] = { |
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{ 0x41000000, PXA2XX_PIC_SSP },
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{ 0x41400000, PXA25X_PIC_NSSP },
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{ 0, 0 } |
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}, pxa26x_ssp[] = { |
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{ 0x41000000, PXA2XX_PIC_SSP },
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{ 0x41400000, PXA25X_PIC_NSSP },
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{ 0x41500000, PXA26X_PIC_ASSP },
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{ 0, 0 } |
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}, pxa27x_ssp[] = { |
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{ 0x41000000, PXA2XX_PIC_SSP },
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{ 0x41700000, PXA27X_PIC_SSP2 },
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{ 0x41900000, PXA2XX_PIC_SSP3 },
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{ 0, 0 } |
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}; |
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|
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#define PMCR 0x00 /* Power Manager Control register */ |
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#define PSSR 0x04 /* Power Manager Sleep Status register */ |
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#define PSPR 0x08 /* Power Manager Scratch-Pad register */ |
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#define PWER 0x0c /* Power Manager Wake-Up Enable register */ |
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#define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */ |
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#define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */ |
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#define PEDR 0x18 /* Power Manager Edge-Detect Status register */ |
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#define PCFR 0x1c /* Power Manager General Configuration register */ |
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#define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */ |
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#define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */ |
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#define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */ |
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#define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */ |
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#define RCSR 0x30 /* Reset Controller Status register */ |
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#define PSLR 0x34 /* Power Manager Sleep Configuration register */ |
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#define PTSR 0x38 /* Power Manager Standby Configuration register */ |
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#define PVCR 0x40 /* Power Manager Voltage Change Control register */ |
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#define PUCR 0x4c /* Power Manager USIM Card Control/Status register */ |
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#define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */ |
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#define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */ |
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#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ |
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#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ |
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|
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static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr) |
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{ |
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struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
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addr -= s->pm_base; |
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|
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switch (addr) {
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case PMCR ... PCMD31:
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if (addr & 3) |
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goto fail;
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|
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return s->pm_regs[addr >> 2]; |
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default:
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fail:
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printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
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break;
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} |
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return 0; |
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} |
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|
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static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{ |
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struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
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addr -= s->pm_base; |
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|
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switch (addr) {
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case PMCR:
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s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a); |
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s->pm_regs[addr >> 2] |= value & 0x15; |
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break;
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|
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case PSSR: /* Read-clean registers */ |
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case RCSR:
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case PKSR:
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s->pm_regs[addr >> 2] &= ~value;
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break;
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default: /* Read-write registers */ |
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if (addr >= PMCR && addr <= PCMD31 && !(addr & 3)) { |
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s->pm_regs[addr >> 2] = value;
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break;
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} |
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|
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printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
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break;
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} |
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} |
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static CPUReadMemoryFunc *pxa2xx_pm_readfn[] = {
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pxa2xx_pm_read, |
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pxa2xx_pm_read, |
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pxa2xx_pm_read, |
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}; |
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|
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static CPUWriteMemoryFunc *pxa2xx_pm_writefn[] = {
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pxa2xx_pm_write, |
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pxa2xx_pm_write, |
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pxa2xx_pm_write, |
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}; |
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|
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#define CCCR 0x00 /* Core Clock Configuration register */ |
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#define CKEN 0x04 /* Clock Enable register */ |
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#define OSCC 0x08 /* Oscillator Configuration register */ |
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#define CCSR 0x0c /* Core Clock Status register */ |
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|
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static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr) |
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{ |
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struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
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addr -= s->cm_base; |
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|
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switch (addr) {
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case CCCR:
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case CKEN:
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case OSCC:
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return s->cm_regs[addr >> 2]; |
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|
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case CCSR:
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return s->cm_regs[CCCR >> 2] | (3 << 28); |
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default:
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printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
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break;
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} |
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return 0; |
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} |
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|
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static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{ |
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struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
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addr -= s->cm_base; |
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|
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switch (addr) {
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case CCCR:
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case CKEN:
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s->cm_regs[addr >> 2] = value;
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break;
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case OSCC:
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s->cm_regs[addr >> 2] &= ~0x6e; |
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s->cm_regs[addr >> 2] |= value & 0x6e; |
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break;
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default:
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printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
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break;
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} |
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} |
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|
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static CPUReadMemoryFunc *pxa2xx_cm_readfn[] = {
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pxa2xx_cm_read, |
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pxa2xx_cm_read, |
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pxa2xx_cm_read, |
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}; |
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|
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static CPUWriteMemoryFunc *pxa2xx_cm_writefn[] = {
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pxa2xx_cm_write, |
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pxa2xx_cm_write, |
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pxa2xx_cm_write, |
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}; |
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|
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static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm) |
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{ |
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struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
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switch (reg) {
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case 6: /* Clock Configuration register */ |
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return s->clkcfg;
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|
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case 7: /* Power Mode register */ |
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return 0; |
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default:
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printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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break;
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} |
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return 0; |
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} |
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|
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static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm, |
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uint32_t value) |
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{ |
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struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
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static const char *pwrmode[8] = { |
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"Normal", "Idle", "Deep-idle", "Standby", |
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"Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", |
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}; |
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switch (reg) {
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case 6: /* Clock Configuration register */ |
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s->clkcfg = value & 0xf;
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if (value & 2) |
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printf("%s: CPU frequency change attempt\n", __FUNCTION__);
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break;
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case 7: /* Power Mode register */ |
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if (value & 8) |
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printf("%s: CPU voltage change attempt\n", __FUNCTION__);
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switch (value & 7) { |
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case 0: |
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/* Do nothing */
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break;
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case 1: |
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/* Idle */
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if (!(s->cm_regs[CCCR] & (1 << 31))) { /* CPDIS */ |
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cpu_interrupt(s->env, CPU_INTERRUPT_HALT); |
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break;
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} |
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/* Fall through. */
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case 2: |
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/* Deep-Idle */
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cpu_interrupt(s->env, CPU_INTERRUPT_HALT); |
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s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ |
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goto message;
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|
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case 3: |
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cpu_reset(s->env); |
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s->env->cp15.c1_sys = 0;
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s->env->cp15.c1_coproc = 0;
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s->env->cp15.c2 = 0;
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s->env->cp15.c3 = 0;
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s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ |
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s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ |
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|
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/*
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* The scratch-pad register is almost universally used
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* for storing the return address on suspend. For the
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* lack of a resuming bootloader, perform a jump
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* directly to that address.
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*/
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memset(s->env->regs, 0, 4 * 15); |
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s->env->regs[15] = s->pm_regs[PSPR >> 2]; |
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|
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#if 0
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buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
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cpu_physical_memory_write(0, &buffer, 4);
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buffer = s->pm_regs[PSPR >> 2];
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cpu_physical_memory_write(8, &buffer, 4);
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#endif
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/* Suspend */
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cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); |
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goto message;
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default:
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message:
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printf("%s: machine entered %s mode\n", __FUNCTION__,
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pwrmode[value & 7]);
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} |
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break;
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|
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default:
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printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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break;
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} |
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} |
291 |
|
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/* Performace Monitoring Registers */
|
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#define CPPMNC 0 /* Performance Monitor Control register */ |
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#define CPCCNT 1 /* Clock Counter register */ |
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#define CPINTEN 4 /* Interrupt Enable register */ |
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#define CPFLAG 5 /* Overflow Flag register */ |
297 |
#define CPEVTSEL 8 /* Event Selection register */ |
298 |
|
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#define CPPMN0 0 /* Performance Count register 0 */ |
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#define CPPMN1 1 /* Performance Count register 1 */ |
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#define CPPMN2 2 /* Performance Count register 2 */ |
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#define CPPMN3 3 /* Performance Count register 3 */ |
303 |
|
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static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm) |
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{ |
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struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
307 |
|
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switch (reg) {
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309 |
case CPPMNC:
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return s->pmnc;
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case CPCCNT:
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312 |
if (s->pmnc & 1) |
313 |
return qemu_get_clock(vm_clock);
|
314 |
else
|
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return 0; |
316 |
case CPINTEN:
|
317 |
case CPFLAG:
|
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case CPEVTSEL:
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return 0; |
320 |
|
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default:
|
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printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
|
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break;
|
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} |
325 |
return 0; |
326 |
} |
327 |
|
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static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm, |
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uint32_t value) |
330 |
{ |
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struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
332 |
|
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switch (reg) {
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case CPPMNC:
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s->pmnc = value; |
336 |
break;
|
337 |
|
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case CPCCNT:
|
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case CPINTEN:
|
340 |
case CPFLAG:
|
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case CPEVTSEL:
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break;
|
343 |
|
344 |
default:
|
345 |
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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break;
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} |
348 |
} |
349 |
|
350 |
static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm) |
351 |
{ |
352 |
switch (crm) {
|
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case 0: |
354 |
return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
|
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case 1: |
356 |
return pxa2xx_perf_read(opaque, op2, reg, crm);
|
357 |
case 2: |
358 |
switch (reg) {
|
359 |
case CPPMN0:
|
360 |
case CPPMN1:
|
361 |
case CPPMN2:
|
362 |
case CPPMN3:
|
363 |
return 0; |
364 |
} |
365 |
/* Fall through */
|
366 |
default:
|
367 |
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
|
368 |
break;
|
369 |
} |
370 |
return 0; |
371 |
} |
372 |
|
373 |
static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm, |
374 |
uint32_t value) |
375 |
{ |
376 |
switch (crm) {
|
377 |
case 0: |
378 |
pxa2xx_clkpwr_write(opaque, op2, reg, crm, value); |
379 |
break;
|
380 |
case 1: |
381 |
pxa2xx_perf_write(opaque, op2, reg, crm, value); |
382 |
break;
|
383 |
case 2: |
384 |
switch (reg) {
|
385 |
case CPPMN0:
|
386 |
case CPPMN1:
|
387 |
case CPPMN2:
|
388 |
case CPPMN3:
|
389 |
return;
|
390 |
} |
391 |
/* Fall through */
|
392 |
default:
|
393 |
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
|
394 |
break;
|
395 |
} |
396 |
} |
397 |
|
398 |
#define MDCNFG 0x00 /* SDRAM Configuration register */ |
399 |
#define MDREFR 0x04 /* SDRAM Refresh Control register */ |
400 |
#define MSC0 0x08 /* Static Memory Control register 0 */ |
401 |
#define MSC1 0x0c /* Static Memory Control register 1 */ |
402 |
#define MSC2 0x10 /* Static Memory Control register 2 */ |
403 |
#define MECR 0x14 /* Expansion Memory Bus Config register */ |
404 |
#define SXCNFG 0x1c /* Synchronous Static Memory Config register */ |
405 |
#define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */ |
406 |
#define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */ |
407 |
#define MCATT0 0x30 /* PC Card Attribute Socket 0 register */ |
408 |
#define MCATT1 0x34 /* PC Card Attribute Socket 1 register */ |
409 |
#define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */ |
410 |
#define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */ |
411 |
#define MDMRS 0x40 /* SDRAM Mode Register Set Config register */ |
412 |
#define BOOT_DEF 0x44 /* Boot-time Default Configuration register */ |
413 |
#define ARB_CNTL 0x48 /* Arbiter Control register */ |
414 |
#define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */ |
415 |
#define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */ |
416 |
#define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */ |
417 |
#define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */ |
418 |
#define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */ |
419 |
#define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ |
420 |
#define SA1110 0x64 /* SA-1110 Memory Compatibility register */ |
421 |
|
422 |
static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr) |
423 |
{ |
424 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
425 |
addr -= s->mm_base; |
426 |
|
427 |
switch (addr) {
|
428 |
case MDCNFG ... SA1110:
|
429 |
if ((addr & 3) == 0) |
430 |
return s->mm_regs[addr >> 2]; |
431 |
|
432 |
default:
|
433 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
434 |
break;
|
435 |
} |
436 |
return 0; |
437 |
} |
438 |
|
439 |
static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr, |
440 |
uint32_t value) |
441 |
{ |
442 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
443 |
addr -= s->mm_base; |
444 |
|
445 |
switch (addr) {
|
446 |
case MDCNFG ... SA1110:
|
447 |
if ((addr & 3) == 0) { |
448 |
s->mm_regs[addr >> 2] = value;
|
449 |
break;
|
450 |
} |
451 |
|
452 |
default:
|
453 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
454 |
break;
|
455 |
} |
456 |
} |
457 |
|
458 |
static CPUReadMemoryFunc *pxa2xx_mm_readfn[] = {
|
459 |
pxa2xx_mm_read, |
460 |
pxa2xx_mm_read, |
461 |
pxa2xx_mm_read, |
462 |
}; |
463 |
|
464 |
static CPUWriteMemoryFunc *pxa2xx_mm_writefn[] = {
|
465 |
pxa2xx_mm_write, |
466 |
pxa2xx_mm_write, |
467 |
pxa2xx_mm_write, |
468 |
}; |
469 |
|
470 |
/* Synchronous Serial Ports */
|
471 |
struct pxa2xx_ssp_s {
|
472 |
target_phys_addr_t base; |
473 |
qemu_irq irq; |
474 |
int enable;
|
475 |
|
476 |
uint32_t sscr[2];
|
477 |
uint32_t sspsp; |
478 |
uint32_t ssto; |
479 |
uint32_t ssitr; |
480 |
uint32_t sssr; |
481 |
uint8_t sstsa; |
482 |
uint8_t ssrsa; |
483 |
uint8_t ssacd; |
484 |
|
485 |
uint32_t rx_fifo[16];
|
486 |
int rx_level;
|
487 |
int rx_start;
|
488 |
|
489 |
uint32_t (*readfn)(void *opaque);
|
490 |
void (*writefn)(void *opaque, uint32_t value); |
491 |
void *opaque;
|
492 |
}; |
493 |
|
494 |
#define SSCR0 0x00 /* SSP Control register 0 */ |
495 |
#define SSCR1 0x04 /* SSP Control register 1 */ |
496 |
#define SSSR 0x08 /* SSP Status register */ |
497 |
#define SSITR 0x0c /* SSP Interrupt Test register */ |
498 |
#define SSDR 0x10 /* SSP Data register */ |
499 |
#define SSTO 0x28 /* SSP Time-Out register */ |
500 |
#define SSPSP 0x2c /* SSP Programmable Serial Protocol register */ |
501 |
#define SSTSA 0x30 /* SSP TX Time Slot Active register */ |
502 |
#define SSRSA 0x34 /* SSP RX Time Slot Active register */ |
503 |
#define SSTSS 0x38 /* SSP Time Slot Status register */ |
504 |
#define SSACD 0x3c /* SSP Audio Clock Divider register */ |
505 |
|
506 |
/* Bitfields for above registers */
|
507 |
#define SSCR0_SPI(x) (((x) & 0x30) == 0x00) |
508 |
#define SSCR0_SSP(x) (((x) & 0x30) == 0x10) |
509 |
#define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20) |
510 |
#define SSCR0_PSP(x) (((x) & 0x30) == 0x30) |
511 |
#define SSCR0_SSE (1 << 7) |
512 |
#define SSCR0_RIM (1 << 22) |
513 |
#define SSCR0_TIM (1 << 23) |
514 |
#define SSCR0_MOD (1 << 31) |
515 |
#define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1) |
516 |
#define SSCR1_RIE (1 << 0) |
517 |
#define SSCR1_TIE (1 << 1) |
518 |
#define SSCR1_LBM (1 << 2) |
519 |
#define SSCR1_MWDS (1 << 5) |
520 |
#define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1) |
521 |
#define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1) |
522 |
#define SSCR1_EFWR (1 << 14) |
523 |
#define SSCR1_PINTE (1 << 18) |
524 |
#define SSCR1_TINTE (1 << 19) |
525 |
#define SSCR1_RSRE (1 << 20) |
526 |
#define SSCR1_TSRE (1 << 21) |
527 |
#define SSCR1_EBCEI (1 << 29) |
528 |
#define SSITR_INT (7 << 5) |
529 |
#define SSSR_TNF (1 << 2) |
530 |
#define SSSR_RNE (1 << 3) |
531 |
#define SSSR_TFS (1 << 5) |
532 |
#define SSSR_RFS (1 << 6) |
533 |
#define SSSR_ROR (1 << 7) |
534 |
#define SSSR_PINT (1 << 18) |
535 |
#define SSSR_TINT (1 << 19) |
536 |
#define SSSR_EOC (1 << 20) |
537 |
#define SSSR_TUR (1 << 21) |
538 |
#define SSSR_BCE (1 << 23) |
539 |
#define SSSR_RW 0x00bc0080 |
540 |
|
541 |
static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s *s) |
542 |
{ |
543 |
int level = 0; |
544 |
|
545 |
level |= s->ssitr & SSITR_INT; |
546 |
level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
|
547 |
level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
|
548 |
level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT)); |
549 |
level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
|
550 |
level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
|
551 |
level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
|
552 |
level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
|
553 |
level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
|
554 |
qemu_set_irq(s->irq, !!level); |
555 |
} |
556 |
|
557 |
static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s *s) |
558 |
{ |
559 |
s->sssr &= ~(0xf << 12); /* Clear RFL */ |
560 |
s->sssr &= ~(0xf << 8); /* Clear TFL */ |
561 |
s->sssr &= ~SSSR_TNF; |
562 |
if (s->enable) {
|
563 |
s->sssr |= ((s->rx_level - 1) & 0xf) << 12; |
564 |
if (s->rx_level >= SSCR1_RFT(s->sscr[1])) |
565 |
s->sssr |= SSSR_RFS; |
566 |
else
|
567 |
s->sssr &= ~SSSR_RFS; |
568 |
if (0 <= SSCR1_TFT(s->sscr[1])) |
569 |
s->sssr |= SSSR_TFS; |
570 |
else
|
571 |
s->sssr &= ~SSSR_TFS; |
572 |
if (s->rx_level)
|
573 |
s->sssr |= SSSR_RNE; |
574 |
else
|
575 |
s->sssr &= ~SSSR_RNE; |
576 |
s->sssr |= SSSR_TNF; |
577 |
} |
578 |
|
579 |
pxa2xx_ssp_int_update(s); |
580 |
} |
581 |
|
582 |
static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr) |
583 |
{ |
584 |
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque; |
585 |
uint32_t retval; |
586 |
addr -= s->base; |
587 |
|
588 |
switch (addr) {
|
589 |
case SSCR0:
|
590 |
return s->sscr[0]; |
591 |
case SSCR1:
|
592 |
return s->sscr[1]; |
593 |
case SSPSP:
|
594 |
return s->sspsp;
|
595 |
case SSTO:
|
596 |
return s->ssto;
|
597 |
case SSITR:
|
598 |
return s->ssitr;
|
599 |
case SSSR:
|
600 |
return s->sssr | s->ssitr;
|
601 |
case SSDR:
|
602 |
if (!s->enable)
|
603 |
return 0xffffffff; |
604 |
if (s->rx_level < 1) { |
605 |
printf("%s: SSP Rx Underrun\n", __FUNCTION__);
|
606 |
return 0xffffffff; |
607 |
} |
608 |
s->rx_level --; |
609 |
retval = s->rx_fifo[s->rx_start ++]; |
610 |
s->rx_start &= 0xf;
|
611 |
pxa2xx_ssp_fifo_update(s); |
612 |
return retval;
|
613 |
case SSTSA:
|
614 |
return s->sstsa;
|
615 |
case SSRSA:
|
616 |
return s->ssrsa;
|
617 |
case SSTSS:
|
618 |
return 0; |
619 |
case SSACD:
|
620 |
return s->ssacd;
|
621 |
default:
|
622 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
623 |
break;
|
624 |
} |
625 |
return 0; |
626 |
} |
627 |
|
628 |
static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr, |
629 |
uint32_t value) |
630 |
{ |
631 |
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque; |
632 |
addr -= s->base; |
633 |
|
634 |
switch (addr) {
|
635 |
case SSCR0:
|
636 |
s->sscr[0] = value & 0xc7ffffff; |
637 |
s->enable = value & SSCR0_SSE; |
638 |
if (value & SSCR0_MOD)
|
639 |
printf("%s: Attempt to use network mode\n", __FUNCTION__);
|
640 |
if (s->enable && SSCR0_DSS(value) < 4) |
641 |
printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
|
642 |
SSCR0_DSS(value)); |
643 |
if (!(value & SSCR0_SSE)) {
|
644 |
s->sssr = 0;
|
645 |
s->ssitr = 0;
|
646 |
s->rx_level = 0;
|
647 |
} |
648 |
pxa2xx_ssp_fifo_update(s); |
649 |
break;
|
650 |
|
651 |
case SSCR1:
|
652 |
s->sscr[1] = value;
|
653 |
if (value & (SSCR1_LBM | SSCR1_EFWR))
|
654 |
printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
|
655 |
pxa2xx_ssp_fifo_update(s); |
656 |
break;
|
657 |
|
658 |
case SSPSP:
|
659 |
s->sspsp = value; |
660 |
break;
|
661 |
|
662 |
case SSTO:
|
663 |
s->ssto = value; |
664 |
break;
|
665 |
|
666 |
case SSITR:
|
667 |
s->ssitr = value & SSITR_INT; |
668 |
pxa2xx_ssp_int_update(s); |
669 |
break;
|
670 |
|
671 |
case SSSR:
|
672 |
s->sssr &= ~(value & SSSR_RW); |
673 |
pxa2xx_ssp_int_update(s); |
674 |
break;
|
675 |
|
676 |
case SSDR:
|
677 |
if (SSCR0_UWIRE(s->sscr[0])) { |
678 |
if (s->sscr[1] & SSCR1_MWDS) |
679 |
value &= 0xffff;
|
680 |
else
|
681 |
value &= 0xff;
|
682 |
} else
|
683 |
/* Note how 32bits overflow does no harm here */
|
684 |
value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; |
685 |
|
686 |
/* Data goes from here to the Tx FIFO and is shifted out from
|
687 |
* there directly to the slave, no need to buffer it.
|
688 |
*/
|
689 |
if (s->enable) {
|
690 |
if (s->writefn)
|
691 |
s->writefn(s->opaque, value); |
692 |
|
693 |
if (s->rx_level < 0x10) { |
694 |
if (s->readfn)
|
695 |
s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] =
|
696 |
s->readfn(s->opaque); |
697 |
else
|
698 |
s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = 0x0; |
699 |
} else
|
700 |
s->sssr |= SSSR_ROR; |
701 |
} |
702 |
pxa2xx_ssp_fifo_update(s); |
703 |
break;
|
704 |
|
705 |
case SSTSA:
|
706 |
s->sstsa = value; |
707 |
break;
|
708 |
|
709 |
case SSRSA:
|
710 |
s->ssrsa = value; |
711 |
break;
|
712 |
|
713 |
case SSACD:
|
714 |
s->ssacd = value; |
715 |
break;
|
716 |
|
717 |
default:
|
718 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
719 |
break;
|
720 |
} |
721 |
} |
722 |
|
723 |
void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port, |
724 |
uint32_t (*readfn)(void *opaque),
|
725 |
void (*writefn)(void *opaque, uint32_t value), void *opaque) |
726 |
{ |
727 |
if (!port) {
|
728 |
printf("%s: no such SSP\n", __FUNCTION__);
|
729 |
exit(-1);
|
730 |
} |
731 |
|
732 |
port->opaque = opaque; |
733 |
port->readfn = readfn; |
734 |
port->writefn = writefn; |
735 |
} |
736 |
|
737 |
static CPUReadMemoryFunc *pxa2xx_ssp_readfn[] = {
|
738 |
pxa2xx_ssp_read, |
739 |
pxa2xx_ssp_read, |
740 |
pxa2xx_ssp_read, |
741 |
}; |
742 |
|
743 |
static CPUWriteMemoryFunc *pxa2xx_ssp_writefn[] = {
|
744 |
pxa2xx_ssp_write, |
745 |
pxa2xx_ssp_write, |
746 |
pxa2xx_ssp_write, |
747 |
}; |
748 |
|
749 |
/* Real-Time Clock */
|
750 |
#define RCNR 0x00 /* RTC Counter register */ |
751 |
#define RTAR 0x04 /* RTC Alarm register */ |
752 |
#define RTSR 0x08 /* RTC Status register */ |
753 |
#define RTTR 0x0c /* RTC Timer Trim register */ |
754 |
#define RDCR 0x10 /* RTC Day Counter register */ |
755 |
#define RYCR 0x14 /* RTC Year Counter register */ |
756 |
#define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */ |
757 |
#define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */ |
758 |
#define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */ |
759 |
#define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */ |
760 |
#define SWCR 0x28 /* RTC Stopwatch Counter register */ |
761 |
#define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */ |
762 |
#define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */ |
763 |
#define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */ |
764 |
#define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */ |
765 |
|
766 |
static inline void pxa2xx_rtc_int_update(struct pxa2xx_state_s *s) |
767 |
{ |
768 |
qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
|
769 |
} |
770 |
|
771 |
static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s *s) |
772 |
{ |
773 |
int64_t rt = qemu_get_clock(rt_clock); |
774 |
s->last_rcnr += ((rt - s->last_hz) << 15) /
|
775 |
(1000 * ((s->rttr & 0xffff) + 1)); |
776 |
s->last_rdcr += ((rt - s->last_hz) << 15) /
|
777 |
(1000 * ((s->rttr & 0xffff) + 1)); |
778 |
s->last_hz = rt; |
779 |
} |
780 |
|
781 |
static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s *s) |
782 |
{ |
783 |
int64_t rt = qemu_get_clock(rt_clock); |
784 |
if (s->rtsr & (1 << 12)) |
785 |
s->last_swcr += (rt - s->last_sw) / 10;
|
786 |
s->last_sw = rt; |
787 |
} |
788 |
|
789 |
static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s *s) |
790 |
{ |
791 |
int64_t rt = qemu_get_clock(rt_clock); |
792 |
if (s->rtsr & (1 << 15)) |
793 |
s->last_swcr += rt - s->last_pi; |
794 |
s->last_pi = rt; |
795 |
} |
796 |
|
797 |
static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s *s, |
798 |
uint32_t rtsr) |
799 |
{ |
800 |
if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0))) |
801 |
qemu_mod_timer(s->rtc_hz, s->last_hz + |
802 |
(((s->rtar - s->last_rcnr) * 1000 *
|
803 |
((s->rttr & 0xffff) + 1)) >> 15)); |
804 |
else
|
805 |
qemu_del_timer(s->rtc_hz); |
806 |
|
807 |
if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4))) |
808 |
qemu_mod_timer(s->rtc_rdal1, s->last_hz + |
809 |
(((s->rdar1 - s->last_rdcr) * 1000 *
|
810 |
((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ |
811 |
else
|
812 |
qemu_del_timer(s->rtc_rdal1); |
813 |
|
814 |
if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6))) |
815 |
qemu_mod_timer(s->rtc_rdal2, s->last_hz + |
816 |
(((s->rdar2 - s->last_rdcr) * 1000 *
|
817 |
((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */ |
818 |
else
|
819 |
qemu_del_timer(s->rtc_rdal2); |
820 |
|
821 |
if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8))) |
822 |
qemu_mod_timer(s->rtc_swal1, s->last_sw + |
823 |
(s->swar1 - s->last_swcr) * 10); /* TODO: fixup */ |
824 |
else
|
825 |
qemu_del_timer(s->rtc_swal1); |
826 |
|
827 |
if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10))) |
828 |
qemu_mod_timer(s->rtc_swal2, s->last_sw + |
829 |
(s->swar2 - s->last_swcr) * 10); /* TODO: fixup */ |
830 |
else
|
831 |
qemu_del_timer(s->rtc_swal2); |
832 |
|
833 |
if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13))) |
834 |
qemu_mod_timer(s->rtc_pi, s->last_pi + |
835 |
(s->piar & 0xffff) - s->last_rtcpicr);
|
836 |
else
|
837 |
qemu_del_timer(s->rtc_pi); |
838 |
} |
839 |
|
840 |
static inline void pxa2xx_rtc_hz_tick(void *opaque) |
841 |
{ |
842 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
843 |
s->rtsr |= (1 << 0); |
844 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
845 |
pxa2xx_rtc_int_update(s); |
846 |
} |
847 |
|
848 |
static inline void pxa2xx_rtc_rdal1_tick(void *opaque) |
849 |
{ |
850 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
851 |
s->rtsr |= (1 << 4); |
852 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
853 |
pxa2xx_rtc_int_update(s); |
854 |
} |
855 |
|
856 |
static inline void pxa2xx_rtc_rdal2_tick(void *opaque) |
857 |
{ |
858 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
859 |
s->rtsr |= (1 << 6); |
860 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
861 |
pxa2xx_rtc_int_update(s); |
862 |
} |
863 |
|
864 |
static inline void pxa2xx_rtc_swal1_tick(void *opaque) |
865 |
{ |
866 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
867 |
s->rtsr |= (1 << 8); |
868 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
869 |
pxa2xx_rtc_int_update(s); |
870 |
} |
871 |
|
872 |
static inline void pxa2xx_rtc_swal2_tick(void *opaque) |
873 |
{ |
874 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
875 |
s->rtsr |= (1 << 10); |
876 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
877 |
pxa2xx_rtc_int_update(s); |
878 |
} |
879 |
|
880 |
static inline void pxa2xx_rtc_pi_tick(void *opaque) |
881 |
{ |
882 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
883 |
s->rtsr |= (1 << 13); |
884 |
pxa2xx_rtc_piupdate(s); |
885 |
s->last_rtcpicr = 0;
|
886 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
887 |
pxa2xx_rtc_int_update(s); |
888 |
} |
889 |
|
890 |
static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr) |
891 |
{ |
892 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
893 |
addr -= s->rtc_base; |
894 |
|
895 |
switch (addr) {
|
896 |
case RTTR:
|
897 |
return s->rttr;
|
898 |
case RTSR:
|
899 |
return s->rtsr;
|
900 |
case RTAR:
|
901 |
return s->rtar;
|
902 |
case RDAR1:
|
903 |
return s->rdar1;
|
904 |
case RDAR2:
|
905 |
return s->rdar2;
|
906 |
case RYAR1:
|
907 |
return s->ryar1;
|
908 |
case RYAR2:
|
909 |
return s->ryar2;
|
910 |
case SWAR1:
|
911 |
return s->swar1;
|
912 |
case SWAR2:
|
913 |
return s->swar2;
|
914 |
case PIAR:
|
915 |
return s->piar;
|
916 |
case RCNR:
|
917 |
return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) / |
918 |
(1000 * ((s->rttr & 0xffff) + 1)); |
919 |
case RDCR:
|
920 |
return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) / |
921 |
(1000 * ((s->rttr & 0xffff) + 1)); |
922 |
case RYCR:
|
923 |
return s->last_rycr;
|
924 |
case SWCR:
|
925 |
if (s->rtsr & (1 << 12)) |
926 |
return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10; |
927 |
else
|
928 |
return s->last_swcr;
|
929 |
default:
|
930 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
931 |
break;
|
932 |
} |
933 |
return 0; |
934 |
} |
935 |
|
936 |
static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr, |
937 |
uint32_t value) |
938 |
{ |
939 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
940 |
addr -= s->rtc_base; |
941 |
|
942 |
switch (addr) {
|
943 |
case RTTR:
|
944 |
if (!(s->rttr & (1 << 31))) { |
945 |
pxa2xx_rtc_hzupdate(s); |
946 |
s->rttr = value; |
947 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
948 |
} |
949 |
break;
|
950 |
|
951 |
case RTSR:
|
952 |
if ((s->rtsr ^ value) & (1 << 15)) |
953 |
pxa2xx_rtc_piupdate(s); |
954 |
|
955 |
if ((s->rtsr ^ value) & (1 << 12)) |
956 |
pxa2xx_rtc_swupdate(s); |
957 |
|
958 |
if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac)) |
959 |
pxa2xx_rtc_alarm_update(s, value); |
960 |
|
961 |
s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac)); |
962 |
pxa2xx_rtc_int_update(s); |
963 |
break;
|
964 |
|
965 |
case RTAR:
|
966 |
s->rtar = value; |
967 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
968 |
break;
|
969 |
|
970 |
case RDAR1:
|
971 |
s->rdar1 = value; |
972 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
973 |
break;
|
974 |
|
975 |
case RDAR2:
|
976 |
s->rdar2 = value; |
977 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
978 |
break;
|
979 |
|
980 |
case RYAR1:
|
981 |
s->ryar1 = value; |
982 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
983 |
break;
|
984 |
|
985 |
case RYAR2:
|
986 |
s->ryar2 = value; |
987 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
988 |
break;
|
989 |
|
990 |
case SWAR1:
|
991 |
pxa2xx_rtc_swupdate(s); |
992 |
s->swar1 = value; |
993 |
s->last_swcr = 0;
|
994 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
995 |
break;
|
996 |
|
997 |
case SWAR2:
|
998 |
s->swar2 = value; |
999 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1000 |
break;
|
1001 |
|
1002 |
case PIAR:
|
1003 |
s->piar = value; |
1004 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1005 |
break;
|
1006 |
|
1007 |
case RCNR:
|
1008 |
pxa2xx_rtc_hzupdate(s); |
1009 |
s->last_rcnr = value; |
1010 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1011 |
break;
|
1012 |
|
1013 |
case RDCR:
|
1014 |
pxa2xx_rtc_hzupdate(s); |
1015 |
s->last_rdcr = value; |
1016 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1017 |
break;
|
1018 |
|
1019 |
case RYCR:
|
1020 |
s->last_rycr = value; |
1021 |
break;
|
1022 |
|
1023 |
case SWCR:
|
1024 |
pxa2xx_rtc_swupdate(s); |
1025 |
s->last_swcr = value; |
1026 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1027 |
break;
|
1028 |
|
1029 |
case RTCPICR:
|
1030 |
pxa2xx_rtc_piupdate(s); |
1031 |
s->last_rtcpicr = value & 0xffff;
|
1032 |
pxa2xx_rtc_alarm_update(s, s->rtsr); |
1033 |
break;
|
1034 |
|
1035 |
default:
|
1036 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1037 |
} |
1038 |
} |
1039 |
|
1040 |
static void pxa2xx_rtc_reset(struct pxa2xx_state_s *s) |
1041 |
{ |
1042 |
struct tm *tm;
|
1043 |
time_t ti; |
1044 |
int wom;
|
1045 |
|
1046 |
s->rttr = 0x7fff;
|
1047 |
s->rtsr = 0;
|
1048 |
|
1049 |
time(&ti); |
1050 |
if (rtc_utc)
|
1051 |
tm = gmtime(&ti); |
1052 |
else
|
1053 |
tm = localtime(&ti); |
1054 |
wom = ((tm->tm_mday - 1) / 7) + 1; |
1055 |
|
1056 |
s->last_rcnr = (uint32_t) ti; |
1057 |
s->last_rdcr = (wom << 20) | ((tm->tm_wday + 1) << 17) | |
1058 |
(tm->tm_hour << 12) | (tm->tm_min << 6) | tm->tm_sec; |
1059 |
s->last_rycr = ((tm->tm_year + 1900) << 9) | |
1060 |
((tm->tm_mon + 1) << 5) | tm->tm_mday; |
1061 |
s->last_swcr = (tm->tm_hour << 19) |
|
1062 |
(tm->tm_min << 13) | (tm->tm_sec << 7); |
1063 |
s->last_rtcpicr = 0;
|
1064 |
s->last_hz = s->last_sw = s->last_pi = qemu_get_clock(rt_clock); |
1065 |
|
1066 |
s->rtc_hz = qemu_new_timer(rt_clock, pxa2xx_rtc_hz_tick, s); |
1067 |
s->rtc_rdal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal1_tick, s); |
1068 |
s->rtc_rdal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal2_tick, s); |
1069 |
s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s); |
1070 |
s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s); |
1071 |
s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s); |
1072 |
} |
1073 |
|
1074 |
static CPUReadMemoryFunc *pxa2xx_rtc_readfn[] = {
|
1075 |
pxa2xx_rtc_read, |
1076 |
pxa2xx_rtc_read, |
1077 |
pxa2xx_rtc_read, |
1078 |
}; |
1079 |
|
1080 |
static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
|
1081 |
pxa2xx_rtc_write, |
1082 |
pxa2xx_rtc_write, |
1083 |
pxa2xx_rtc_write, |
1084 |
}; |
1085 |
|
1086 |
/* PXA Inter-IC Sound Controller */
|
1087 |
static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s *i2s) |
1088 |
{ |
1089 |
i2s->rx_len = 0;
|
1090 |
i2s->tx_len = 0;
|
1091 |
i2s->fifo_len = 0;
|
1092 |
i2s->clk = 0x1a;
|
1093 |
i2s->control[0] = 0x00; |
1094 |
i2s->control[1] = 0x00; |
1095 |
i2s->status = 0x00;
|
1096 |
i2s->mask = 0x00;
|
1097 |
} |
1098 |
|
1099 |
#define SACR_TFTH(val) ((val >> 8) & 0xf) |
1100 |
#define SACR_RFTH(val) ((val >> 12) & 0xf) |
1101 |
#define SACR_DREC(val) (val & (1 << 3)) |
1102 |
#define SACR_DPRL(val) (val & (1 << 4)) |
1103 |
|
1104 |
static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s *i2s) |
1105 |
{ |
1106 |
int rfs, tfs;
|
1107 |
rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
|
1108 |
!SACR_DREC(i2s->control[1]);
|
1109 |
tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
|
1110 |
i2s->enable && !SACR_DPRL(i2s->control[1]);
|
1111 |
|
1112 |
pxa2xx_dma_request(i2s->dma, PXA2XX_RX_RQ_I2S, rfs); |
1113 |
pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs); |
1114 |
|
1115 |
i2s->status &= 0xe0;
|
1116 |
if (i2s->rx_len)
|
1117 |
i2s->status |= 1 << 1; /* RNE */ |
1118 |
if (i2s->enable)
|
1119 |
i2s->status |= 1 << 2; /* BSY */ |
1120 |
if (tfs)
|
1121 |
i2s->status |= 1 << 3; /* TFS */ |
1122 |
if (rfs)
|
1123 |
i2s->status |= 1 << 4; /* RFS */ |
1124 |
if (!(i2s->tx_len && i2s->enable))
|
1125 |
i2s->status |= i2s->fifo_len << 8; /* TFL */ |
1126 |
i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */ |
1127 |
|
1128 |
qemu_set_irq(i2s->irq, i2s->status & i2s->mask); |
1129 |
} |
1130 |
|
1131 |
#define SACR0 0x00 /* Serial Audio Global Control register */ |
1132 |
#define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */ |
1133 |
#define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */ |
1134 |
#define SAIMR 0x14 /* Serial Audio Interrupt Mask register */ |
1135 |
#define SAICR 0x18 /* Serial Audio Interrupt Clear register */ |
1136 |
#define SADIV 0x60 /* Serial Audio Clock Divider register */ |
1137 |
#define SADR 0x80 /* Serial Audio Data register */ |
1138 |
|
1139 |
static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr) |
1140 |
{ |
1141 |
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; |
1142 |
addr -= s->base; |
1143 |
|
1144 |
switch (addr) {
|
1145 |
case SACR0:
|
1146 |
return s->control[0]; |
1147 |
case SACR1:
|
1148 |
return s->control[1]; |
1149 |
case SASR0:
|
1150 |
return s->status;
|
1151 |
case SAIMR:
|
1152 |
return s->mask;
|
1153 |
case SAICR:
|
1154 |
return 0; |
1155 |
case SADIV:
|
1156 |
return s->clk;
|
1157 |
case SADR:
|
1158 |
if (s->rx_len > 0) { |
1159 |
s->rx_len --; |
1160 |
pxa2xx_i2s_update(s); |
1161 |
return s->codec_in(s->opaque);
|
1162 |
} |
1163 |
return 0; |
1164 |
default:
|
1165 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1166 |
break;
|
1167 |
} |
1168 |
return 0; |
1169 |
} |
1170 |
|
1171 |
static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr, |
1172 |
uint32_t value) |
1173 |
{ |
1174 |
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; |
1175 |
uint32_t *sample; |
1176 |
addr -= s->base; |
1177 |
|
1178 |
switch (addr) {
|
1179 |
case SACR0:
|
1180 |
if (value & (1 << 3)) /* RST */ |
1181 |
pxa2xx_i2s_reset(s); |
1182 |
s->control[0] = value & 0xff3d; |
1183 |
if (!s->enable && (value & 1) && s->tx_len) { /* ENB */ |
1184 |
for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++) |
1185 |
s->codec_out(s->opaque, *sample); |
1186 |
s->status &= ~(1 << 7); /* I2SOFF */ |
1187 |
} |
1188 |
if (value & (1 << 4)) /* EFWR */ |
1189 |
printf("%s: Attempt to use special function\n", __FUNCTION__);
|
1190 |
s->enable = ((value ^ 4) & 5) == 5; /* ENB && !RST*/ |
1191 |
pxa2xx_i2s_update(s); |
1192 |
break;
|
1193 |
case SACR1:
|
1194 |
s->control[1] = value & 0x0039; |
1195 |
if (value & (1 << 5)) /* ENLBF */ |
1196 |
printf("%s: Attempt to use loopback function\n", __FUNCTION__);
|
1197 |
if (value & (1 << 4)) /* DPRL */ |
1198 |
s->fifo_len = 0;
|
1199 |
pxa2xx_i2s_update(s); |
1200 |
break;
|
1201 |
case SAIMR:
|
1202 |
s->mask = value & 0x0078;
|
1203 |
pxa2xx_i2s_update(s); |
1204 |
break;
|
1205 |
case SAICR:
|
1206 |
s->status &= ~(value & (3 << 5)); |
1207 |
pxa2xx_i2s_update(s); |
1208 |
break;
|
1209 |
case SADIV:
|
1210 |
s->clk = value & 0x007f;
|
1211 |
break;
|
1212 |
case SADR:
|
1213 |
if (s->tx_len && s->enable) {
|
1214 |
s->tx_len --; |
1215 |
pxa2xx_i2s_update(s); |
1216 |
s->codec_out(s->opaque, value); |
1217 |
} else if (s->fifo_len < 16) { |
1218 |
s->fifo[s->fifo_len ++] = value; |
1219 |
pxa2xx_i2s_update(s); |
1220 |
} |
1221 |
break;
|
1222 |
default:
|
1223 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1224 |
} |
1225 |
} |
1226 |
|
1227 |
static CPUReadMemoryFunc *pxa2xx_i2s_readfn[] = {
|
1228 |
pxa2xx_i2s_read, |
1229 |
pxa2xx_i2s_read, |
1230 |
pxa2xx_i2s_read, |
1231 |
}; |
1232 |
|
1233 |
static CPUWriteMemoryFunc *pxa2xx_i2s_writefn[] = {
|
1234 |
pxa2xx_i2s_write, |
1235 |
pxa2xx_i2s_write, |
1236 |
pxa2xx_i2s_write, |
1237 |
}; |
1238 |
|
1239 |
static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) |
1240 |
{ |
1241 |
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque; |
1242 |
uint32_t *sample; |
1243 |
|
1244 |
/* Signal FIFO errors */
|
1245 |
if (s->enable && s->tx_len)
|
1246 |
s->status |= 1 << 5; /* TUR */ |
1247 |
if (s->enable && s->rx_len)
|
1248 |
s->status |= 1 << 6; /* ROR */ |
1249 |
|
1250 |
/* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
|
1251 |
* handle the cases where it makes a difference. */
|
1252 |
s->tx_len = tx - s->fifo_len; |
1253 |
s->rx_len = rx; |
1254 |
/* Note that is s->codec_out wasn't set, we wouldn't get called. */
|
1255 |
if (s->enable)
|
1256 |
for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
|
1257 |
s->codec_out(s->opaque, *sample); |
1258 |
pxa2xx_i2s_update(s); |
1259 |
} |
1260 |
|
1261 |
static struct pxa2xx_i2s_s *pxa2xx_i2s_init(target_phys_addr_t base, |
1262 |
qemu_irq irq, struct pxa2xx_dma_state_s *dma)
|
1263 |
{ |
1264 |
int iomemtype;
|
1265 |
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) |
1266 |
qemu_mallocz(sizeof(struct pxa2xx_i2s_s)); |
1267 |
|
1268 |
s->base = base; |
1269 |
s->irq = irq; |
1270 |
s->dma = dma; |
1271 |
s->data_req = pxa2xx_i2s_data_req; |
1272 |
|
1273 |
pxa2xx_i2s_reset(s); |
1274 |
|
1275 |
iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn,
|
1276 |
pxa2xx_i2s_writefn, s); |
1277 |
cpu_register_physical_memory(s->base & 0xfff00000, 0xfffff, iomemtype); |
1278 |
|
1279 |
return s;
|
1280 |
} |
1281 |
|
1282 |
/* PXA Fast Infra-red Communications Port */
|
1283 |
struct pxa2xx_fir_s {
|
1284 |
target_phys_addr_t base; |
1285 |
qemu_irq irq; |
1286 |
struct pxa2xx_dma_state_s *dma;
|
1287 |
int enable;
|
1288 |
CharDriverState *chr; |
1289 |
|
1290 |
uint8_t control[3];
|
1291 |
uint8_t status[2];
|
1292 |
|
1293 |
int rx_len;
|
1294 |
int rx_start;
|
1295 |
uint8_t rx_fifo[64];
|
1296 |
}; |
1297 |
|
1298 |
static void pxa2xx_fir_reset(struct pxa2xx_fir_s *s) |
1299 |
{ |
1300 |
s->control[0] = 0x00; |
1301 |
s->control[1] = 0x00; |
1302 |
s->control[2] = 0x00; |
1303 |
s->status[0] = 0x00; |
1304 |
s->status[1] = 0x00; |
1305 |
s->enable = 0;
|
1306 |
} |
1307 |
|
1308 |
static inline void pxa2xx_fir_update(struct pxa2xx_fir_s *s) |
1309 |
{ |
1310 |
static const int tresh[4] = { 8, 16, 32, 0 }; |
1311 |
int intr = 0; |
1312 |
if ((s->control[0] & (1 << 4)) && /* RXE */ |
1313 |
s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */ |
1314 |
s->status[0] |= 1 << 4; /* RFS */ |
1315 |
else
|
1316 |
s->status[0] &= ~(1 << 4); /* RFS */ |
1317 |
if (s->control[0] & (1 << 3)) /* TXE */ |
1318 |
s->status[0] |= 1 << 3; /* TFS */ |
1319 |
else
|
1320 |
s->status[0] &= ~(1 << 3); /* TFS */ |
1321 |
if (s->rx_len)
|
1322 |
s->status[1] |= 1 << 2; /* RNE */ |
1323 |
else
|
1324 |
s->status[1] &= ~(1 << 2); /* RNE */ |
1325 |
if (s->control[0] & (1 << 4)) /* RXE */ |
1326 |
s->status[1] |= 1 << 0; /* RSY */ |
1327 |
else
|
1328 |
s->status[1] &= ~(1 << 0); /* RSY */ |
1329 |
|
1330 |
intr |= (s->control[0] & (1 << 5)) && /* RIE */ |
1331 |
(s->status[0] & (1 << 4)); /* RFS */ |
1332 |
intr |= (s->control[0] & (1 << 6)) && /* TIE */ |
1333 |
(s->status[0] & (1 << 3)); /* TFS */ |
1334 |
intr |= (s->control[2] & (1 << 4)) && /* TRAIL */ |
1335 |
(s->status[0] & (1 << 6)); /* EOC */ |
1336 |
intr |= (s->control[0] & (1 << 2)) && /* TUS */ |
1337 |
(s->status[0] & (1 << 1)); /* TUR */ |
1338 |
intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ |
1339 |
|
1340 |
pxa2xx_dma_request(s->dma, PXA2XX_RX_RQ_ICP, (s->status[0] >> 4) & 1); |
1341 |
pxa2xx_dma_request(s->dma, PXA2XX_TX_RQ_ICP, (s->status[0] >> 3) & 1); |
1342 |
|
1343 |
qemu_set_irq(s->irq, intr && s->enable); |
1344 |
} |
1345 |
|
1346 |
#define ICCR0 0x00 /* FICP Control register 0 */ |
1347 |
#define ICCR1 0x04 /* FICP Control register 1 */ |
1348 |
#define ICCR2 0x08 /* FICP Control register 2 */ |
1349 |
#define ICDR 0x0c /* FICP Data register */ |
1350 |
#define ICSR0 0x14 /* FICP Status register 0 */ |
1351 |
#define ICSR1 0x18 /* FICP Status register 1 */ |
1352 |
#define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ |
1353 |
|
1354 |
static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr) |
1355 |
{ |
1356 |
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; |
1357 |
uint8_t ret; |
1358 |
addr -= s->base; |
1359 |
|
1360 |
switch (addr) {
|
1361 |
case ICCR0:
|
1362 |
return s->control[0]; |
1363 |
case ICCR1:
|
1364 |
return s->control[1]; |
1365 |
case ICCR2:
|
1366 |
return s->control[2]; |
1367 |
case ICDR:
|
1368 |
s->status[0] &= ~0x01; |
1369 |
s->status[1] &= ~0x72; |
1370 |
if (s->rx_len) {
|
1371 |
s->rx_len --; |
1372 |
ret = s->rx_fifo[s->rx_start ++]; |
1373 |
s->rx_start &= 63;
|
1374 |
pxa2xx_fir_update(s); |
1375 |
return ret;
|
1376 |
} |
1377 |
printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
|
1378 |
break;
|
1379 |
case ICSR0:
|
1380 |
return s->status[0]; |
1381 |
case ICSR1:
|
1382 |
return s->status[1] | (1 << 3); /* TNF */ |
1383 |
case ICFOR:
|
1384 |
return s->rx_len;
|
1385 |
default:
|
1386 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1387 |
break;
|
1388 |
} |
1389 |
return 0; |
1390 |
} |
1391 |
|
1392 |
static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr, |
1393 |
uint32_t value) |
1394 |
{ |
1395 |
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; |
1396 |
uint8_t ch; |
1397 |
addr -= s->base; |
1398 |
|
1399 |
switch (addr) {
|
1400 |
case ICCR0:
|
1401 |
s->control[0] = value;
|
1402 |
if (!(value & (1 << 4))) /* RXE */ |
1403 |
s->rx_len = s->rx_start = 0;
|
1404 |
if (!(value & (1 << 3))) /* TXE */ |
1405 |
/* Nop */;
|
1406 |
s->enable = value & 1; /* ITR */ |
1407 |
if (!s->enable)
|
1408 |
s->status[0] = 0; |
1409 |
pxa2xx_fir_update(s); |
1410 |
break;
|
1411 |
case ICCR1:
|
1412 |
s->control[1] = value;
|
1413 |
break;
|
1414 |
case ICCR2:
|
1415 |
s->control[2] = value & 0x3f; |
1416 |
pxa2xx_fir_update(s); |
1417 |
break;
|
1418 |
case ICDR:
|
1419 |
if (s->control[2] & (1 << 2)) /* TXP */ |
1420 |
ch = value; |
1421 |
else
|
1422 |
ch = ~value; |
1423 |
if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */ |
1424 |
qemu_chr_write(s->chr, &ch, 1);
|
1425 |
break;
|
1426 |
case ICSR0:
|
1427 |
s->status[0] &= ~(value & 0x66); |
1428 |
pxa2xx_fir_update(s); |
1429 |
break;
|
1430 |
case ICFOR:
|
1431 |
break;
|
1432 |
default:
|
1433 |
printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); |
1434 |
} |
1435 |
} |
1436 |
|
1437 |
static CPUReadMemoryFunc *pxa2xx_fir_readfn[] = {
|
1438 |
pxa2xx_fir_read, |
1439 |
pxa2xx_fir_read, |
1440 |
pxa2xx_fir_read, |
1441 |
}; |
1442 |
|
1443 |
static CPUWriteMemoryFunc *pxa2xx_fir_writefn[] = {
|
1444 |
pxa2xx_fir_write, |
1445 |
pxa2xx_fir_write, |
1446 |
pxa2xx_fir_write, |
1447 |
}; |
1448 |
|
1449 |
static int pxa2xx_fir_is_empty(void *opaque) |
1450 |
{ |
1451 |
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; |
1452 |
return (s->rx_len < 64); |
1453 |
} |
1454 |
|
1455 |
static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size) |
1456 |
{ |
1457 |
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque; |
1458 |
if (!(s->control[0] & (1 << 4))) /* RXE */ |
1459 |
return;
|
1460 |
|
1461 |
while (size --) {
|
1462 |
s->status[1] |= 1 << 4; /* EOF */ |
1463 |
if (s->rx_len >= 64) { |
1464 |
s->status[1] |= 1 << 6; /* ROR */ |
1465 |
break;
|
1466 |
} |
1467 |
|
1468 |
if (s->control[2] & (1 << 3)) /* RXP */ |
1469 |
s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
|
1470 |
else
|
1471 |
s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
|
1472 |
} |
1473 |
|
1474 |
pxa2xx_fir_update(s); |
1475 |
} |
1476 |
|
1477 |
static void pxa2xx_fir_event(void *opaque, int event) |
1478 |
{ |
1479 |
} |
1480 |
|
1481 |
static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base, |
1482 |
qemu_irq irq, struct pxa2xx_dma_state_s *dma,
|
1483 |
CharDriverState *chr) |
1484 |
{ |
1485 |
int iomemtype;
|
1486 |
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) |
1487 |
qemu_mallocz(sizeof(struct pxa2xx_fir_s)); |
1488 |
|
1489 |
s->base = base; |
1490 |
s->irq = irq; |
1491 |
s->dma = dma; |
1492 |
s->chr = chr; |
1493 |
|
1494 |
pxa2xx_fir_reset(s); |
1495 |
|
1496 |
iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn,
|
1497 |
pxa2xx_fir_writefn, s); |
1498 |
cpu_register_physical_memory(s->base, 0xfff, iomemtype);
|
1499 |
|
1500 |
if (chr)
|
1501 |
qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty, |
1502 |
pxa2xx_fir_rx, pxa2xx_fir_event, s); |
1503 |
|
1504 |
return s;
|
1505 |
} |
1506 |
|
1507 |
void pxa2xx_reset(int line, int level, void *opaque) |
1508 |
{ |
1509 |
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; |
1510 |
if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ |
1511 |
cpu_reset(s->env); |
1512 |
/* TODO: reset peripherals */
|
1513 |
} |
1514 |
} |
1515 |
|
1516 |
/* Initialise a PXA270 integrated chip (ARM based core). */
|
1517 |
struct pxa2xx_state_s *pxa270_init(DisplayState *ds, const char *revision) |
1518 |
{ |
1519 |
struct pxa2xx_state_s *s;
|
1520 |
struct pxa2xx_ssp_s *ssp;
|
1521 |
char *cpu_model;
|
1522 |
int iomemtype, i;
|
1523 |
s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s)); |
1524 |
|
1525 |
s->env = cpu_init(); |
1526 |
asprintf(&cpu_model, "pxa270-%s", revision);
|
1527 |
cpu_arm_set_model(s->env, cpu_model); |
1528 |
free(cpu_model); |
1529 |
|
1530 |
s->pic = pxa2xx_pic_init(0x40d00000, s->env);
|
1531 |
|
1532 |
s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
|
1533 |
|
1534 |
pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
|
1535 |
s->pic[PXA27X_PIC_OST_4_11], s->env); |
1536 |
|
1537 |
s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121); |
1538 |
|
1539 |
s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
|
1540 |
|
1541 |
for (i = 0; pxa270_serial[i].io_base; i ++) |
1542 |
if (serial_hds[i])
|
1543 |
serial_mm_init(pxa270_serial[i].io_base, 2,
|
1544 |
s->pic[pxa270_serial[i].irqn], serial_hds[i], 1);
|
1545 |
else
|
1546 |
break;
|
1547 |
if (serial_hds[i])
|
1548 |
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
|
1549 |
s->dma, serial_hds[i]); |
1550 |
|
1551 |
if (ds)
|
1552 |
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
|
1553 |
|
1554 |
s->cm_base = 0x41300000;
|
1555 |
s->cm_regs[CCCR >> 4] = 0x02000210; /* 416.0 MHz */ |
1556 |
s->clkcfg = 0x00000009; /* Turbo mode active */ |
1557 |
iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
|
1558 |
pxa2xx_cm_writefn, s); |
1559 |
cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype);
|
1560 |
|
1561 |
cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
|
1562 |
|
1563 |
s->mm_base = 0x48000000;
|
1564 |
s->mm_regs[MDMRS >> 2] = 0x00020002; |
1565 |
s->mm_regs[MDREFR >> 2] = 0x03ca4000; |
1566 |
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ |
1567 |
iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
|
1568 |
pxa2xx_mm_writefn, s); |
1569 |
cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype);
|
1570 |
|
1571 |
for (i = 0; pxa27x_ssp[i].io_base; i ++); |
1572 |
s->ssp = (struct pxa2xx_ssp_s **)
|
1573 |
qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i); |
1574 |
ssp = (struct pxa2xx_ssp_s *)
|
1575 |
qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i); |
1576 |
for (i = 0; pxa27x_ssp[i].io_base; i ++) { |
1577 |
s->ssp[i] = &ssp[i]; |
1578 |
ssp[i].base = pxa27x_ssp[i].io_base; |
1579 |
ssp[i].irq = s->pic[pxa27x_ssp[i].irqn]; |
1580 |
|
1581 |
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
|
1582 |
pxa2xx_ssp_writefn, &ssp[i]); |
1583 |
cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype);
|
1584 |
} |
1585 |
|
1586 |
if (usb_enabled) {
|
1587 |
usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]); |
1588 |
} |
1589 |
|
1590 |
s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000); |
1591 |
s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000); |
1592 |
|
1593 |
s->rtc_base = 0x40900000;
|
1594 |
iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
|
1595 |
pxa2xx_rtc_writefn, s); |
1596 |
cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype);
|
1597 |
pxa2xx_rtc_reset(s); |
1598 |
|
1599 |
s->pm_base = 0x40f00000;
|
1600 |
iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
|
1601 |
pxa2xx_pm_writefn, s); |
1602 |
cpu_register_physical_memory(s->pm_base, 0xfff, iomemtype);
|
1603 |
|
1604 |
s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
|
1605 |
|
1606 |
/* GPIO1 resets the processor */
|
1607 |
/* The handler can be overriden by board-specific code */
|
1608 |
pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
|
1609 |
return s;
|
1610 |
} |
1611 |
|
1612 |
/* Initialise a PXA255 integrated chip (ARM based core). */
|
1613 |
struct pxa2xx_state_s *pxa255_init(DisplayState *ds)
|
1614 |
{ |
1615 |
struct pxa2xx_state_s *s;
|
1616 |
struct pxa2xx_ssp_s *ssp;
|
1617 |
int iomemtype, i;
|
1618 |
s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s)); |
1619 |
|
1620 |
s->env = cpu_init(); |
1621 |
cpu_arm_set_model(s->env, "pxa255");
|
1622 |
|
1623 |
s->pic = pxa2xx_pic_init(0x40d00000, s->env);
|
1624 |
|
1625 |
s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
|
1626 |
|
1627 |
pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0], s->env);
|
1628 |
|
1629 |
s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121); |
1630 |
|
1631 |
s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
|
1632 |
|
1633 |
for (i = 0; pxa255_serial[i].io_base; i ++) |
1634 |
if (serial_hds[i])
|
1635 |
serial_mm_init(pxa255_serial[i].io_base, 2,
|
1636 |
s->pic[pxa255_serial[i].irqn], serial_hds[i], 1);
|
1637 |
else
|
1638 |
break;
|
1639 |
if (serial_hds[i])
|
1640 |
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
|
1641 |
s->dma, serial_hds[i]); |
1642 |
|
1643 |
if (ds)
|
1644 |
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
|
1645 |
|
1646 |
s->cm_base = 0x41300000;
|
1647 |
s->cm_regs[CCCR >> 4] = 0x02000210; /* 416.0 MHz */ |
1648 |
s->clkcfg = 0x00000009; /* Turbo mode active */ |
1649 |
iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
|
1650 |
pxa2xx_cm_writefn, s); |
1651 |
cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype);
|
1652 |
|
1653 |
cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
|
1654 |
|
1655 |
s->mm_base = 0x48000000;
|
1656 |
s->mm_regs[MDMRS >> 2] = 0x00020002; |
1657 |
s->mm_regs[MDREFR >> 2] = 0x03ca4000; |
1658 |
s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ |
1659 |
iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
|
1660 |
pxa2xx_mm_writefn, s); |
1661 |
cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype);
|
1662 |
|
1663 |
for (i = 0; pxa255_ssp[i].io_base; i ++); |
1664 |
s->ssp = (struct pxa2xx_ssp_s **)
|
1665 |
qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i); |
1666 |
ssp = (struct pxa2xx_ssp_s *)
|
1667 |
qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i); |
1668 |
for (i = 0; pxa255_ssp[i].io_base; i ++) { |
1669 |
s->ssp[i] = &ssp[i]; |
1670 |
ssp[i].base = pxa255_ssp[i].io_base; |
1671 |
ssp[i].irq = s->pic[pxa255_ssp[i].irqn]; |
1672 |
|
1673 |
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
|
1674 |
pxa2xx_ssp_writefn, &ssp[i]); |
1675 |
cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype);
|
1676 |
} |
1677 |
|
1678 |
if (usb_enabled) {
|
1679 |
usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]); |
1680 |
} |
1681 |
|
1682 |
s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000); |
1683 |
s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000); |
1684 |
|
1685 |
s->rtc_base = 0x40900000;
|
1686 |
iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
|
1687 |
pxa2xx_rtc_writefn, s); |
1688 |
cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype);
|
1689 |
pxa2xx_rtc_reset(s); |
1690 |
|
1691 |
s->pm_base = 0x40f00000;
|
1692 |
iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
|
1693 |
pxa2xx_pm_writefn, s); |
1694 |
cpu_register_physical_memory(s->pm_base, 0xfff, iomemtype);
|
1695 |
|
1696 |
s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
|
1697 |
|
1698 |
/* GPIO1 resets the processor */
|
1699 |
/* The handler can be overriden by board-specific code */
|
1700 |
pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
|
1701 |
return s;
|
1702 |
} |