Archipelago » qemu

/*

 *  i386 helpers

 *

 *  Copyright (c) 2003 Fabrice Bellard

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, see <http://www.gnu.org/licenses/>.

 */

#include <math.h>

#include "exec.h"

#include "exec-all.h"

#include "host-utils.h"

#include "ioport.h"

//#define DEBUG_PCALL

#ifdef DEBUG_PCALL

#  define LOG_PCALL(...) qemu_log_mask(CPU_LOG_PCALL, ## __VA_ARGS__)

#  define LOG_PCALL_STATE(env) \

          log_cpu_state_mask(CPU_LOG_PCALL, (env), X86_DUMP_CCOP)

#else

#  define LOG_PCALL(...) do { } while (0)

#  define LOG_PCALL_STATE(env) do { } while (0)

#endif

#if 0

#define raise_exception_err(a, b)\

do {\

    qemu_log("raise_exception line=%d\n", __LINE__);\

    (raise_exception_err)(a, b);\

} while (0)

#endif

static const uint8_t parity_table[256] = {

    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,

    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,

    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,

    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,

    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,

    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,

    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,

    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,

    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,

    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,

    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,

    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,

    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,

    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,

    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,

    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,

    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,

    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,

    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,

    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,

    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,

    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,

    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,

    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,

    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,

    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,

    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,

    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,

    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,

    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,

    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,

    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,

};

/* modulo 17 table */

static const uint8_t rclw_table[32] = {

    0, 1, 2, 3, 4, 5, 6, 7,

    8, 9,10,11,12,13,14,15,

   16, 0, 1, 2, 3, 4, 5, 6,

    7, 8, 9,10,11,12,13,14,

};

/* modulo 9 table */

static const uint8_t rclb_table[32] = {

    0, 1, 2, 3, 4, 5, 6, 7,

    8, 0, 1, 2, 3, 4, 5, 6,

    7, 8, 0, 1, 2, 3, 4, 5,

    6, 7, 8, 0, 1, 2, 3, 4,

};

#if defined(CONFIG_SOFTFLOAT)

# define floatx_lg2 make_floatx80( 0x3ffd, 0x9a209a84fbcff799LL )

# define floatx_l2e make_floatx80( 0x3fff, 0xb8aa3b295c17f0bcLL )

# define floatx_l2t make_floatx80( 0x4000, 0xd49a784bcd1b8afeLL )

#else

# define floatx_lg2 (0.30102999566398119523L)

# define floatx_l2e (1.44269504088896340739L)

# define floatx_l2t (3.32192809488736234781L)

#endif

static const CPU86_LDouble f15rk[7] =

{

    floatx_zero,

    floatx_one,

    floatx_pi,

    floatx_lg2,

    floatx_ln2,

    floatx_l2e,

    floatx_l2t,

};

/* broken thread support */

static spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;

void helper_lock(void)

{

    spin_lock(&global_cpu_lock);

}

void helper_unlock(void)

{

    spin_unlock(&global_cpu_lock);

}

void helper_write_eflags(target_ulong t0, uint32_t update_mask)

{

    load_eflags(t0, update_mask);

}

target_ulong helper_read_eflags(void)

{

    uint32_t eflags;

    eflags = helper_cc_compute_all(CC_OP);

    eflags |= (DF & DF_MASK);

    eflags |= env->eflags & ~(VM_MASK | RF_MASK);

    return eflags;

}

/* return non zero if error */

static inline int load_segment(uint32_t *e1_ptr, uint32_t *e2_ptr,

                               int selector)

{

    SegmentCache *dt;

    int index;

    target_ulong ptr;

    if (selector & 0x4)

        dt = &env->ldt;

    else

        dt = &env->gdt;

    index = selector & ~7;

    if ((index + 7) > dt->limit)

        return -1;

    ptr = dt->base + index;

    *e1_ptr = ldl_kernel(ptr);

    *e2_ptr = ldl_kernel(ptr + 4);

    return 0;

}

static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)

{

    unsigned int limit;

    limit = (e1 & 0xffff) | (e2 & 0x000f0000);

    if (e2 & DESC_G_MASK)

        limit = (limit << 12) | 0xfff;

    return limit;

}

static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)

{

    return ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));

}

static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, uint32_t e2)

{

    sc->base = get_seg_base(e1, e2);

    sc->limit = get_seg_limit(e1, e2);

    sc->flags = e2;

}

/* init the segment cache in vm86 mode. */

static inline void load_seg_vm(int seg, int selector)

{

    selector &= 0xffff;

    cpu_x86_load_seg_cache(env, seg, selector,

                           (selector << 4), 0xffff, 0);

}

static inline void get_ss_esp_from_tss(uint32_t *ss_ptr,

                                       uint32_t *esp_ptr, int dpl)

{

    int type, index, shift;

#if 0

    {

        int i;

        printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);

        for(i=0;i<env->tr.limit;i++) {

            printf("%02x ", env->tr.base[i]);

            if ((i & 7) == 7) printf("\n");

        }

        printf("\n");

    }

#endif

    if (!(env->tr.flags & DESC_P_MASK))

        cpu_abort(env, "invalid tss");

    type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;

    if ((type & 7) != 1)

        cpu_abort(env, "invalid tss type");

    shift = type >> 3;

    index = (dpl * 4 + 2) << shift;

    if (index + (4 << shift) - 1 > env->tr.limit)

        raise_exception_err(EXCP0A_TSS, env->tr.selector & 0xfffc);

    if (shift == 0) {

        *esp_ptr = lduw_kernel(env->tr.base + index);

        *ss_ptr = lduw_kernel(env->tr.base + index + 2);

    } else {

        *esp_ptr = ldl_kernel(env->tr.base + index);

        *ss_ptr = lduw_kernel(env->tr.base + index + 4);

    }

}

/* XXX: merge with load_seg() */

static void tss_load_seg(int seg_reg, int selector)

{

    uint32_t e1, e2;

    int rpl, dpl, cpl;

    if ((selector & 0xfffc) != 0) {

        if (load_segment(&e1, &e2, selector) != 0)

            raise_exception_err(EXCP0A_TSS, selector & 0xfffc);

        if (!(e2 & DESC_S_MASK))

            raise_exception_err(EXCP0A_TSS, selector & 0xfffc);

        rpl = selector & 3;

        dpl = (e2 >> DESC_DPL_SHIFT) & 3;

        cpl = env->hflags & HF_CPL_MASK;

        if (seg_reg == R_CS) {

            if (!(e2 & DESC_CS_MASK))

                raise_exception_err(EXCP0A_TSS, selector & 0xfffc);

            /* XXX: is it correct ? */

            if (dpl != rpl)

                raise_exception_err(EXCP0A_TSS, selector & 0xfffc);

            if ((e2 & DESC_C_MASK) && dpl > rpl)

                raise_exception_err(EXCP0A_TSS, selector & 0xfffc);

        } else if (seg_reg == R_SS) {

            /* SS must be writable data */

            if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK))

                raise_exception_err(EXCP0A_TSS, selector & 0xfffc);

            if (dpl != cpl || dpl != rpl)

                raise_exception_err(EXCP0A_TSS, selector & 0xfffc);

        } else {

            /* not readable code */

            if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK))

                raise_exception_err(EXCP0A_TSS, selector & 0xfffc);

            /* if data or non conforming code, checks the rights */

            if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {

                if (dpl < cpl || dpl < rpl)

                    raise_exception_err(EXCP0A_TSS, selector & 0xfffc);

            }

        }

        if (!(e2 & DESC_P_MASK))

            raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);

        cpu_x86_load_seg_cache(env, seg_reg, selector,

                       get_seg_base(e1, e2),

                       get_seg_limit(e1, e2),

                       e2);

    } else {

        if (seg_reg == R_SS || seg_reg == R_CS)

            raise_exception_err(EXCP0A_TSS, selector & 0xfffc);

    }

}

#define SWITCH_TSS_JMP  0

#define SWITCH_TSS_IRET 1

#define SWITCH_TSS_CALL 2

/* XXX: restore CPU state in registers (PowerPC case) */

static void switch_tss(int tss_selector,

                       uint32_t e1, uint32_t e2, int source,

                       uint32_t next_eip)

{

    int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;

    target_ulong tss_base;

    uint32_t new_regs[8], new_segs[6];

    uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;

    uint32_t old_eflags, eflags_mask;

    SegmentCache *dt;

    int index;

    target_ulong ptr;

    type = (e2 >> DESC_TYPE_SHIFT) & 0xf;

    LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);

    /* if task gate, we read the TSS segment and we load it */

    if (type == 5) {

        if (!(e2 & DESC_P_MASK))

            raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);

        tss_selector = e1 >> 16;

        if (tss_selector & 4)

            raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);

        if (load_segment(&e1, &e2, tss_selector) != 0)

            raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);

        if (e2 & DESC_S_MASK)

            raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);

        type = (e2 >> DESC_TYPE_SHIFT) & 0xf;

        if ((type & 7) != 1)

            raise_exception_err(EXCP0D_GPF, tss_selector & 0xfffc);

    }

    if (!(e2 & DESC_P_MASK))

        raise_exception_err(EXCP0B_NOSEG, tss_selector & 0xfffc);

    if (type & 8)

        tss_limit_max = 103;

    else

        tss_limit_max = 43;

    tss_limit = get_seg_limit(e1, e2);

    tss_base = get_seg_base(e1, e2);

    if ((tss_selector & 4) != 0 ||

        tss_limit < tss_limit_max)

        raise_exception_err(EXCP0A_TSS, tss_selector & 0xfffc);

    old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;

    if (old_type & 8)

        old_tss_limit_max = 103;

    else

        old_tss_limit_max = 43;

    /* read all the registers from the new TSS */

    if (type & 8) {

        /* 32 bit */

        new_cr3 = ldl_kernel(tss_base + 0x1c);

        new_eip = ldl_kernel(tss_base + 0x20);

        new_eflags = ldl_kernel(tss_base + 0x24);

        for(i = 0; i < 8; i++)

            new_regs[i] = ldl_kernel(tss_base + (0x28 + i * 4));

        for(i = 0; i < 6; i++)

            new_segs[i] = lduw_kernel(tss_base + (0x48 + i * 4));

        new_ldt = lduw_kernel(tss_base + 0x60);

        new_trap = ldl_kernel(tss_base + 0x64);

    } else {

        /* 16 bit */

        new_cr3 = 0;

        new_eip = lduw_kernel(tss_base + 0x0e);

        new_eflags = lduw_kernel(tss_base + 0x10);

        for(i = 0; i < 8; i++)

            new_regs[i] = lduw_kernel(tss_base + (0x12 + i * 2)) | 0xffff0000;

        for(i = 0; i < 4; i++)

            new_segs[i] = lduw_kernel(tss_base + (0x22 + i * 4));

        new_ldt = lduw_kernel(tss_base + 0x2a);

        new_segs[R_FS] = 0;

        new_segs[R_GS] = 0;

        new_trap = 0;

    }

    /* XXX: avoid a compiler warning, see

     http://support.amd.com/us/Processor_TechDocs/24593.pdf

     chapters 12.2.5 and 13.2.4 on how to implement TSS Trap bit */

    (void)new_trap;

    /* NOTE: we must avoid memory exceptions during the task switch,

       so we make dummy accesses before */

    /* XXX: it can still fail in some cases, so a bigger hack is

       necessary to valid the TLB after having done the accesses */

    v1 = ldub_kernel(env->tr.base);

    v2 = ldub_kernel(env->tr.base + old_tss_limit_max);

    stb_kernel(env->tr.base, v1);

    stb_kernel(env->tr.base + old_tss_limit_max, v2);

    /* clear busy bit (it is restartable) */

    if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {

        target_ulong ptr;

        uint32_t e2;

        ptr = env->gdt.base + (env->tr.selector & ~7);

        e2 = ldl_kernel(ptr + 4);

        e2 &= ~DESC_TSS_BUSY_MASK;

        stl_kernel(ptr + 4, e2);

    }

    old_eflags = compute_eflags();

    if (source == SWITCH_TSS_IRET)

        old_eflags &= ~NT_MASK;

    /* save the current state in the old TSS */

    if (type & 8) {

        /* 32 bit */

        stl_kernel(env->tr.base + 0x20, next_eip);

        stl_kernel(env->tr.base + 0x24, old_eflags);

        stl_kernel(env->tr.base + (0x28 + 0 * 4), EAX);

        stl_kernel(env->tr.base + (0x28 + 1 * 4), ECX);

        stl_kernel(env->tr.base + (0x28 + 2 * 4), EDX);

        stl_kernel(env->tr.base + (0x28 + 3 * 4), EBX);

        stl_kernel(env->tr.base + (0x28 + 4 * 4), ESP);

        stl_kernel(env->tr.base + (0x28 + 5 * 4), EBP);

        stl_kernel(env->tr.base + (0x28 + 6 * 4), ESI);

        stl_kernel(env->tr.base + (0x28 + 7 * 4), EDI);

        for(i = 0; i < 6; i++)

            stw_kernel(env->tr.base + (0x48 + i * 4), env->segs[i].selector);

    } else {

        /* 16 bit */

        stw_kernel(env->tr.base + 0x0e, next_eip);

        stw_kernel(env->tr.base + 0x10, old_eflags);

        stw_kernel(env->tr.base + (0x12 + 0 * 2), EAX);

        stw_kernel(env->tr.base + (0x12 + 1 * 2), ECX);

        stw_kernel(env->tr.base + (0x12 + 2 * 2), EDX);

        stw_kernel(env->tr.base + (0x12 + 3 * 2), EBX);

        stw_kernel(env->tr.base + (0x12 + 4 * 2), ESP);

        stw_kernel(env->tr.base + (0x12 + 5 * 2), EBP);

        stw_kernel(env->tr.base + (0x12 + 6 * 2), ESI);

        stw_kernel(env->tr.base + (0x12 + 7 * 2), EDI);

        for(i = 0; i < 4; i++)

            stw_kernel(env->tr.base + (0x22 + i * 4), env->segs[i].selector);

    }

    /* now if an exception occurs, it will occurs in the next task

       context */

    if (source == SWITCH_TSS_CALL) {

        stw_kernel(tss_base, env->tr.selector);

        new_eflags |= NT_MASK;

    }

    /* set busy bit */

    if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {

        target_ulong ptr;

        uint32_t e2;

        ptr = env->gdt.base + (tss_selector & ~7);

        e2 = ldl_kernel(ptr + 4);

        e2 |= DESC_TSS_BUSY_MASK;

        stl_kernel(ptr + 4, e2);

    }

    /* set the new CPU state */

    /* from this point, any exception which occurs can give problems */

    env->cr[0] |= CR0_TS_MASK;

    env->hflags |= HF_TS_MASK;

    env->tr.selector = tss_selector;

    env->tr.base = tss_base;

    env->tr.limit = tss_limit;

    env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;

    if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {

        cpu_x86_update_cr3(env, new_cr3);

    }

    /* load all registers without an exception, then reload them with

       possible exception */

    env->eip = new_eip;

    eflags_mask = TF_MASK | AC_MASK | ID_MASK |

        IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;

    if (!(type & 8))

        eflags_mask &= 0xffff;

    load_eflags(new_eflags, eflags_mask);

    /* XXX: what to do in 16 bit case ? */

    EAX = new_regs[0];

    ECX = new_regs[1];

    EDX = new_regs[2];

    EBX = new_regs[3];

    ESP = new_regs[4];

    EBP = new_regs[5];

    ESI = new_regs[6];

    EDI = new_regs[7];

    if (new_eflags & VM_MASK) {

        for(i = 0; i < 6; i++)

            load_seg_vm(i, new_segs[i]);

        /* in vm86, CPL is always 3 */

        cpu_x86_set_cpl(env, 3);

    } else {

        /* CPL is set the RPL of CS */

        cpu_x86_set_cpl(env, new_segs[R_CS] & 3);

        /* first just selectors as the rest may trigger exceptions */

        for(i = 0; i < 6; i++)

            cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);

    }

    env->ldt.selector = new_ldt & ~4;

    env->ldt.base = 0;

    env->ldt.limit = 0;

    env->ldt.flags = 0;

    /* load the LDT */

    if (new_ldt & 4)

        raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);

    if ((new_ldt & 0xfffc) != 0) {

        dt = &env->gdt;

        index = new_ldt & ~7;

        if ((index + 7) > dt->limit)

            raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);

        ptr = dt->base + index;

        e1 = ldl_kernel(ptr);

        e2 = ldl_kernel(ptr + 4);

        if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2)

            raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);

        if (!(e2 & DESC_P_MASK))

            raise_exception_err(EXCP0A_TSS, new_ldt & 0xfffc);

        load_seg_cache_raw_dt(&env->ldt, e1, e2);

    }

    /* load the segments */

    if (!(new_eflags & VM_MASK)) {

        tss_load_seg(R_CS, new_segs[R_CS]);

        tss_load_seg(R_SS, new_segs[R_SS]);

        tss_load_seg(R_ES, new_segs[R_ES]);

        tss_load_seg(R_DS, new_segs[R_DS]);

        tss_load_seg(R_FS, new_segs[R_FS]);

        tss_load_seg(R_GS, new_segs[R_GS]);

    }

    /* check that EIP is in the CS segment limits */

    if (new_eip > env->segs[R_CS].limit) {

        /* XXX: different exception if CALL ? */

        raise_exception_err(EXCP0D_GPF, 0);

    }

#ifndef CONFIG_USER_ONLY

    /* reset local breakpoints */

    if (env->dr[7] & 0x55) {

        for (i = 0; i < 4; i++) {

            if (hw_breakpoint_enabled(env->dr[7], i) == 0x1)

                hw_breakpoint_remove(env, i);

        }

        env->dr[7] &= ~0x55;

    }

#endif

}

/* check if Port I/O is allowed in TSS */

static inline void check_io(int addr, int size)

{

    int io_offset, val, mask;

    /* TSS must be a valid 32 bit one */

    if (!(env->tr.flags & DESC_P_MASK) ||

        ((env->tr.flags >> DESC_TYPE_SHIFT) & 0xf) != 9 ||

        env->tr.limit < 103)

        goto fail;

    io_offset = lduw_kernel(env->tr.base + 0x66);

    io_offset += (addr >> 3);

    /* Note: the check needs two bytes */

    if ((io_offset + 1) > env->tr.limit)

        goto fail;

    val = lduw_kernel(env->tr.base + io_offset);

    val >>= (addr & 7);

    mask = (1 << size) - 1;

    /* all bits must be zero to allow the I/O */

    if ((val & mask) != 0) {

    fail:

        raise_exception_err(EXCP0D_GPF, 0);

    }

}

void helper_check_iob(uint32_t t0)

{

    check_io(t0, 1);

}

void helper_check_iow(uint32_t t0)

{

    check_io(t0, 2);

}

void helper_check_iol(uint32_t t0)

{

    check_io(t0, 4);

}

void helper_outb(uint32_t port, uint32_t data)

{

    cpu_outb(port, data & 0xff);

}

target_ulong helper_inb(uint32_t port)

{

    return cpu_inb(port);

}

void helper_outw(uint32_t port, uint32_t data)

{

    cpu_outw(port, data & 0xffff);

}

target_ulong helper_inw(uint32_t port)

{

    return cpu_inw(port);

}

void helper_outl(uint32_t port, uint32_t data)

{

    cpu_outl(port, data);

}

target_ulong helper_inl(uint32_t port)

{

    return cpu_inl(port);

}

static inline unsigned int get_sp_mask(unsigned int e2)

{

    if (e2 & DESC_B_MASK)

        return 0xffffffff;

    else

        return 0xffff;

}

static int exeption_has_error_code(int intno)

{

        switch(intno) {

        case 8:

        case 10:

        case 11:

        case 12:

        case 13:

        case 14:

        case 17:

            return 1;

        }

        return 0;

}

#ifdef TARGET_X86_64

#define SET_ESP(val, sp_mask)\

do {\

    if ((sp_mask) == 0xffff)\

        ESP = (ESP & ~0xffff) | ((val) & 0xffff);\

    else if ((sp_mask) == 0xffffffffLL)\

        ESP = (uint32_t)(val);\

    else\

        ESP = (val);\

} while (0)

#else

#define SET_ESP(val, sp_mask) ESP = (ESP & ~(sp_mask)) | ((val) & (sp_mask))

#endif

/* in 64-bit machines, this can overflow. So this segment addition macro

 * can be used to trim the value to 32-bit whenever needed */

#define SEG_ADDL(ssp, sp, sp_mask) ((uint32_t)((ssp) + (sp & (sp_mask))))

/* XXX: add a is_user flag to have proper security support */

#define PUSHW(ssp, sp, sp_mask, val)\

{\

    sp -= 2;\

    stw_kernel((ssp) + (sp & (sp_mask)), (val));\

}

#define PUSHL(ssp, sp, sp_mask, val)\

{\

    sp -= 4;\

    stl_kernel(SEG_ADDL(ssp, sp, sp_mask), (uint32_t)(val));\

}

#define POPW(ssp, sp, sp_mask, val)\

{\

    val = lduw_kernel((ssp) + (sp & (sp_mask)));\

    sp += 2;\

}

#define POPL(ssp, sp, sp_mask, val)\

{\

    val = (uint32_t)ldl_kernel(SEG_ADDL(ssp, sp, sp_mask));\

    sp += 4;\

}

/* protected mode interrupt */

static void do_interrupt_protected(int intno, int is_int, int error_code,

                                   unsigned int next_eip, int is_hw)

{

    SegmentCache *dt;

    target_ulong ptr, ssp;

    int type, dpl, selector, ss_dpl, cpl;

    int has_error_code, new_stack, shift;

    uint32_t e1, e2, offset, ss = 0, esp, ss_e1 = 0, ss_e2 = 0;

    uint32_t old_eip, sp_mask;

    has_error_code = 0;

    if (!is_int && !is_hw)

        has_error_code = exeption_has_error_code(intno);

    if (is_int)

        old_eip = next_eip;

    else

        old_eip = env->eip;

    dt = &env->idt;

    if (intno * 8 + 7 > dt->limit)

        raise_exception_err(EXCP0D_GPF, intno * 8 + 2);

    ptr = dt->base + intno * 8;

    e1 = ldl_kernel(ptr);

    e2 = ldl_kernel(ptr + 4);

    /* check gate type */

    type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;

    switch(type) {

    case 5: /* task gate */

        /* must do that check here to return the correct error code */

        if (!(e2 & DESC_P_MASK))

            raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);

        switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);

        if (has_error_code) {

            int type;

            uint32_t mask;

            /* push the error code */

            type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;

            shift = type >> 3;

            if (env->segs[R_SS].flags & DESC_B_MASK)

                mask = 0xffffffff;

            else

                mask = 0xffff;

            esp = (ESP - (2 << shift)) & mask;

            ssp = env->segs[R_SS].base + esp;

            if (shift)

                stl_kernel(ssp, error_code);

            else

                stw_kernel(ssp, error_code);

            SET_ESP(esp, mask);

        }

        return;

    case 6: /* 286 interrupt gate */

    case 7: /* 286 trap gate */

    case 14: /* 386 interrupt gate */

    case 15: /* 386 trap gate */

        break;

    default:

        raise_exception_err(EXCP0D_GPF, intno * 8 + 2);

        break;

    }

    dpl = (e2 >> DESC_DPL_SHIFT) & 3;

    cpl = env->hflags & HF_CPL_MASK;

    /* check privilege if software int */

    if (is_int && dpl < cpl)

        raise_exception_err(EXCP0D_GPF, intno * 8 + 2);

    /* check valid bit */

    if (!(e2 & DESC_P_MASK))

        raise_exception_err(EXCP0B_NOSEG, intno * 8 + 2);

    selector = e1 >> 16;

    offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);

    if ((selector & 0xfffc) == 0)

        raise_exception_err(EXCP0D_GPF, 0);

    if (load_segment(&e1, &e2, selector) != 0)

        raise_exception_err(EXCP0D_GPF, selector & 0xfffc);

    if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK)))

        raise_exception_err(EXCP0D_GPF, selector & 0xfffc);

    dpl = (e2 >> DESC_DPL_SHIFT) & 3;

    if (dpl > cpl)

        raise_exception_err(EXCP0D_GPF, selector & 0xfffc);

    if (!(e2 & DESC_P_MASK))

        raise_exception_err(EXCP0B_NOSEG, selector & 0xfffc);

    if (!(e2 & DESC_C_MASK) && dpl < cpl) {

        /* to inner privilege */

        get_ss_esp_from_tss(&ss, &esp, dpl);

        if ((ss & 0xfffc) == 0)

            raise_exception_err(EXCP0A_TSS, ss & 0xfffc);

        if ((ss & 3) != dpl)

            raise_exception_err(EXCP0A_TSS, ss & 0xfffc);

        if (load_segment(&ss_e1, &ss_e2, ss) != 0)

            raise_exception_err(EXCP0A_TSS, ss & 0xfffc);

        ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;

        if (ss_dpl != dpl)

            raise_exception_err(EXCP0A_TSS, ss & 0xfffc);

        if (!(ss_e2 & DESC_S_MASK) ||

            (ss_e2 & DESC_CS_MASK) ||

            !(ss_e2 & DESC_W_MASK))

            raise_exception_err(EXCP0A_TSS, ss & 0xfffc);

        if (!(ss_e2 & DESC_P_MASK))

            raise_exception_err(EXCP0A_TSS, ss & 0xfffc);

        new_stack = 1;

        sp_mask = get_sp_mask(ss_e2);

        ssp = get_seg_base(ss_e1, ss_e2);

    } else if ((e2 & DESC_C_MASK) || dpl == cpl) {

        /* to same privilege */

        if (env->eflags & VM_MASK)

            raise_exception_err(EXCP0D_GPF, selector & 0xfffc);

        new_stack = 0;

        sp_mask = get_sp_mask(env->segs[R_SS].flags);

        ssp = env->segs[R_SS].base;

        esp = ESP;

        dpl = cpl;

    } else {

        raise_exception_err(EXCP0D_GPF, selector & 0xfffc);

        new_stack = 0; /* avoid warning */

        sp_mask = 0; /* avoid warning */

        ssp = 0; /* avoid warning */

        esp = 0; /* avoid warning */

    }

    shift = type >> 3;

#if 0

    /* XXX: check that enough room is available */

    push_size = 6 + (new_stack << 2) + (has_error_code << 1);

    if (env->eflags & VM_MASK)

        push_size += 8;

    push_size <<= shift;

#endif

    if (shift == 1) {

        if (new_stack) {

            if (env->eflags & VM_MASK) {

                PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);

                PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);

                PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);

                PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);

            }

            PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);

            PUSHL(ssp, esp, sp_mask, ESP);

        }

        PUSHL(ssp, esp, sp_mask, compute_eflags());

        PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);

        PUSHL(ssp, esp, sp_mask, old_eip);

        if (has_error_code) {

            PUSHL(ssp, esp, sp_mask, error_code);

        }

    } else {

        if (new_stack) {

            if (env->eflags & VM_MASK) {

                PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);

                PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);

                PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);

                PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);

            }

            PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);

            PUSHW(ssp, esp, sp_mask, ESP);

        }

        PUSHW(ssp, esp, sp_mask, compute_eflags());

        PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);

        PUSHW(ssp, esp, sp_mask, old_eip);

        if (has_error_code) {

            PUSHW(ssp, esp, sp_mask, error_code);

        }

    }

    if (new_stack) {

        if (env->eflags & VM_MASK) {

            cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);

            cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);

            cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);

            cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);

        }

        ss = (ss & ~3) | dpl;

        cpu_x86_load_seg_cache(env, R_SS, ss,

                               ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);

    }

    SET_ESP(esp, sp_mask);

    selector = (selector & ~3) | dpl;

    cpu_x86_load_seg_cache(env, R_CS, selector,

                   get_seg_base(e1, e2),

                   get_seg_limit(e1, e2),

                   e2);

    cpu_x86_set_cpl(env, dpl);

    env->eip = offset;

    /* interrupt gate clear IF mask */

    if ((type & 1) == 0) {

        env->eflags &= ~IF_MASK;

    }

    env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);

}

#ifdef TARGET_X86_64

#define PUSHQ(sp, val)\

{\

    sp -= 8;\

    stq_kernel(sp, (val));\

}