Revision a1daafd8

b/target-mips/translate_init.c
317 317
        .CP0_Config2 = MIPS_CONFIG2,
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        .CP0_Config3 = MIPS_CONFIG3,
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        .SYNCI_Step = 32,
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        .CCRes = 2,
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        .CCRes = 1,
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        .CP0_Status_rw_bitmask = 0x36FBFFFF,
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	/* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
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        .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |

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