Revision a1daafd8
b/target-mips/translate_init.c | ||
---|---|---|
317 | 317 |
.CP0_Config2 = MIPS_CONFIG2, |
318 | 318 |
.CP0_Config3 = MIPS_CONFIG3, |
319 | 319 |
.SYNCI_Step = 32, |
320 |
.CCRes = 2,
|
|
320 |
.CCRes = 1,
|
|
321 | 321 |
.CP0_Status_rw_bitmask = 0x36FBFFFF, |
322 | 322 |
/* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ |
323 | 323 |
.CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | |
Also available in: Unified diff