Revision a212ea75 tcg/sparc/tcg-target.c

b/tcg/sparc/tcg-target.c
348 348
{
349 349
    if (!check_fit_tl(arg, 10))
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        tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
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#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
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    tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
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              INSN_IMM13(arg & 0x3ff));
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#else
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    tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
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              INSN_IMM13(arg & 0x3ff));
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#endif
351
    if (TCG_TARGET_REG_BITS == 64) {
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        tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
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                  INSN_IMM13(arg & 0x3ff));
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    } else {
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        tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
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                  INSN_IMM13(arg & 0x3ff));
357
    }
358 358
}
359 359

  
360 360
static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
......
447 447
    }
448 448
}
449 449

  
450
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
450
#if TCG_TARGET_REG_BITS == 64
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static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index)
452 452
{
453 453
    int32_t val;
......
493 493
    tcg_out_nop(s);
494 494
}
495 495

  
496
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
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#if TCG_TARGET_REG_BITS == 64
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static void tcg_out_brcond_i64(TCGContext *s, int cond,
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                               TCGArg arg1, TCGArg arg2, int const_arg2,
499 499
                               int label_index)
......
989 989
        tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
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        break;
991 991

  
992
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
992
#if TCG_TARGET_REG_BITS == 64
993 993
#define OP_32_64(x)                             \
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        glue(glue(case INDEX_op_, x), _i32:)    \
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        glue(glue(case INDEX_op_, x), _i64:)
......
1010 1010
        tcg_out_ldst(s, args[0], args[1], args[2], LDSH);
1011 1011
        break;
1012 1012
    case INDEX_op_ld_i32:
1013
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1013
#if TCG_TARGET_REG_BITS == 64
1014 1014
    case INDEX_op_ld32u_i64:
1015 1015
#endif
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        tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
......
1022 1022
        tcg_out_ldst(s, args[0], args[1], args[2], STH);
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        break;
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    case INDEX_op_st_i32:
1025
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1025
#if TCG_TARGET_REG_BITS == 64
1026 1026
    case INDEX_op_st32_i64:
1027 1027
#endif
1028 1028
        tcg_out_ldst(s, args[0], args[1], args[2], STW);
......
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        tcg_out_qemu_st(s, args, 2);
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        break;
1108 1108

  
1109
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1109
#if TCG_TARGET_REG_BITS == 64
1110 1110
    case INDEX_op_movi_i64:
1111 1111
        tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
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        break;
......
1208 1208
    { INDEX_op_qemu_st16, { "L", "L" } },
1209 1209
    { INDEX_op_qemu_st32, { "L", "L" } },
1210 1210

  
1211
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1211
#if TCG_TARGET_REG_BITS == 64
1212 1212
    { INDEX_op_mov_i64, { "r", "r" } },
1213 1213
    { INDEX_op_movi_i64, { "r" } },
1214 1214
    { INDEX_op_ld8u_i64, { "r", "r" } },
......
1246 1246
void tcg_target_init(TCGContext *s)
1247 1247
{
1248 1248
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1249
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1249
#if TCG_TARGET_REG_BITS == 64
1250 1250
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1251 1251
#endif
1252 1252
    tcg_regset_set32(tcg_target_call_clobber_regs, 0,
......
1267 1267

  
1268 1268
    tcg_regset_clear(s->reserved_regs);
1269 1269
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
1270
#if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
1270
#if TCG_TARGET_REG_BITS == 64
1271 1271
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
1272 1272
#endif
1273 1273
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use

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