Revision a316d335

b/cpu-defs.h
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#define MAX_BREAKPOINTS 32
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#define TB_JMP_CACHE_BITS 12
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#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
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#define CPU_TLB_SIZE 256
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typedef struct CPUTLBEntry {
......
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    target_phys_addr_t addend; 
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} CPUTLBEntry;
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#define CPU_COMMON                                                      \
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    struct TranslationBlock *current_tb; /* currently executing TB  */  \
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    /* soft mmu support */                                              \
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    /* in order to avoid passing too many arguments to the memory       \
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       write helpers, we store some rarely used information in the CPU  \
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       context) */                                                      \
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    unsigned long mem_write_pc; /* host pc at which the memory was      \
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                                   written */                           \
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    target_ulong mem_write_vaddr; /* target virtual addr at which the   \
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                                     memory was written */              \
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    /* 0 = kernel, 1 = user */                                          \
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    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];                              \
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    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];                             \
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    struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \
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                                                                        \
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    /* from this point: preserved by CPU reset */                       \
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    /* ice debug support */                                             \
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    target_ulong breakpoints[MAX_BREAKPOINTS];                          \
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    int nb_breakpoints;                                                 \
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    int singlestep_enabled;                                             \
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                                                                        \
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    /* user data */                                                     \
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    void *opaque;
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#endif
b/target-arm/cpu.h
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    jmp_buf jmp_env;
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    int exception_index;
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    int interrupt_request;
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    struct TranslationBlock *current_tb;
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    int user_mode_only;
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    uint32_t address;
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    /* ICE debug support.  */
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    target_ulong breakpoints[MAX_BREAKPOINTS];
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    int nb_breakpoints;
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    int singlestep_enabled;
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    /* in order to avoid passing too many arguments to the memory
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       write helpers, we store some rarely used information in the CPU
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       context) */
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    unsigned long mem_write_pc; /* host pc at which the memory was
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                                   written */
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    unsigned long mem_write_vaddr; /* target virtual addr at which the
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                                      memory was written */
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    /* VFP coprocessor state.  */
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    struct {
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        float64 regs[16];
......
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        float_status fp_status;
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    } vfp;
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    /* user data */
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    void *opaque;
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    CPU_COMMON
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} CPUARMState;
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CPUARMState *cpu_arm_init(void);
b/target-i386/cpu.h
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    int error_code;
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    int exception_is_int;
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    target_ulong exception_next_eip;
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    struct TranslationBlock *current_tb; /* currently executing TB */
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    target_ulong dr[8]; /* debug registers */
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    int interrupt_request; 
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    int user_mode_only; /* user mode only simulation */
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    /* soft mmu support */
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    /* in order to avoid passing too many arguments to the memory
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       write helpers, we store some rarely used information in the CPU
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       context) */
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    unsigned long mem_write_pc; /* host pc at which the memory was
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                                   written */
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    target_ulong mem_write_vaddr; /* target virtual addr at which the
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                                     memory was written */
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    /* 0 = kernel, 1 = user */
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    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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    /* from this point: preserved by CPU reset */
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    /* ice debug support */
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    target_ulong breakpoints[MAX_BREAKPOINTS];
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    int nb_breakpoints;
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    int singlestep_enabled;
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    CPU_COMMON
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    /* processor features (e.g. for CPUID insn) */
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    uint32_t cpuid_level;
......
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    /* in order to simplify APIC support, we leave this pointer to the
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       user */
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    struct APICState *apic_state;
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    /* user data */
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    void *opaque;
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} CPUX86State;
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CPUX86State *cpu_x86_init(void);
b/target-mips/cpu.h
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#define MIPS_HFLAG_BR     0x0800 /* branch to register (can't link TB) */
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    target_ulong btarget;        /* Jump / branch target               */
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    int bcond;                   /* Branch condition (if needed)       */
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    struct TranslationBlock *current_tb; /* currently executing TB  */
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    /* soft mmu support */
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    /* in order to avoid passing too many arguments to the memory
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       write helpers, we store some rarely used information in the CPU
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       context) */
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    target_ulong mem_write_pc; /* host pc at which the memory was
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                                   written */
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    unsigned long mem_write_vaddr; /* target virtual addr at which the
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                                      memory was written */
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    /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
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    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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    /* ice debug support */
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    target_ulong breakpoints[MAX_BREAKPOINTS];
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    int nb_breakpoints;
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    int singlestep_enabled; /* XXX: should use CPU single step mode instead */
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    /* user data */
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    void *opaque;
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    CPU_COMMON
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};
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#include "cpu-all.h"
b/target-ppc/cpu.h
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    /* floating point status and control register */
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    uint8_t fpscr[8];
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    /* soft mmu support */
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    /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
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    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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    CPU_COMMON
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    int access_type; /* when a memory exception occurs, the access
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                        type is stored here */
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    /* in order to avoid passing too many arguments to the memory
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       write helpers, we store some rarely used information in the CPU
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       context) */
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    unsigned long mem_write_pc; /* host pc at which the memory was
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                                   written */
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    unsigned long mem_write_vaddr; /* target virtual addr at which the
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                                      memory was written */
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    /* MMU context */
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    /* Address space register */
......
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    /* Those resources are used only in Qemu core */
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    jmp_buf jmp_env;
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    int user_mode_only; /* user mode only simulation */
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    struct TranslationBlock *current_tb; /* currently executing TB */
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    uint32_t hflags;
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    /* ice debug support */
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    target_ulong breakpoints[MAX_BREAKPOINTS];
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    int nb_breakpoints;
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    int singlestep_enabled; /* XXX: should use CPU single step mode instead */
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    /* Power management */
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    int power_mode;
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    /* temporary hack to handle OSI calls (only used if non NULL) */
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    int (*osi_call)(struct CPUPPCState *env);
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    /* user data */
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    void *opaque;
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};
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/*****************************************************************************/
b/target-sparc/cpu.h
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    int exception_index;
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    int interrupt_index;
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    int interrupt_request;
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    struct TranslationBlock *current_tb;
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    void *opaque;
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    /* NOTE: we allow 8 more registers to handle wrapping */
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    target_ulong regbase[NWINDOWS * 16 + 8];
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    /* in order to avoid passing too many arguments to the memory
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       write helpers, we store some rarely used information in the CPU
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       context) */
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    unsigned long mem_write_pc; /* host pc at which the memory was
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                                   written */
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    target_ulong mem_write_vaddr; /* target virtual addr at which the
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                                      memory was written */
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    /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
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    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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    CPU_COMMON
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    /* MMU regs */
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#if defined(TARGET_SPARC64)
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    uint64_t lsu;
......
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#if !defined(TARGET_SPARC64) && !defined(reg_T2)
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    target_ulong t2;
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#endif
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    /* ice debug support */
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    target_ulong breakpoints[MAX_BREAKPOINTS];
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    int nb_breakpoints;
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    int singlestep_enabled; /* XXX: should use CPU single step mode instead */
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} CPUSPARCState;
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#if defined(TARGET_SPARC64)
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#define GET_FSR32(env) (env->fsr & 0xcfc1ffff)

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