Revision a316d335 target-mips/cpu.h
b/target-mips/cpu.h | ||
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#define MIPS_HFLAG_BR 0x0800 /* branch to register (can't link TB) */ |
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target_ulong btarget; /* Jump / branch target */ |
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int bcond; /* Branch condition (if needed) */ |
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struct TranslationBlock *current_tb; /* currently executing TB */ |
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/* soft mmu support */ |
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/* in order to avoid passing too many arguments to the memory |
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write helpers, we store some rarely used information in the CPU |
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context) */ |
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target_ulong mem_write_pc; /* host pc at which the memory was |
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written */ |
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unsigned long mem_write_vaddr; /* target virtual addr at which the |
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memory was written */ |
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/* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */ |
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CPUTLBEntry tlb_read[2][CPU_TLB_SIZE]; |
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CPUTLBEntry tlb_write[2][CPU_TLB_SIZE]; |
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/* ice debug support */ |
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target_ulong breakpoints[MAX_BREAKPOINTS]; |
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int nb_breakpoints; |
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int singlestep_enabled; /* XXX: should use CPU single step mode instead */ |
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/* user data */ |
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void *opaque; |
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CPU_COMMON |
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}; |
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#include "cpu-all.h" |
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