Revision a316d335 target-ppc/cpu.h

b/target-ppc/cpu.h
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    /* floating point status and control register */
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    uint8_t fpscr[8];
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    /* soft mmu support */
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    /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
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    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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    CPU_COMMON
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    int access_type; /* when a memory exception occurs, the access
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                        type is stored here */
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    /* in order to avoid passing too many arguments to the memory
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       write helpers, we store some rarely used information in the CPU
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       context) */
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    unsigned long mem_write_pc; /* host pc at which the memory was
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                                   written */
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    unsigned long mem_write_vaddr; /* target virtual addr at which the
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                                      memory was written */
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    /* MMU context */
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    /* Address space register */
......
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    /* Those resources are used only in Qemu core */
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    jmp_buf jmp_env;
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    int user_mode_only; /* user mode only simulation */
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    struct TranslationBlock *current_tb; /* currently executing TB */
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    uint32_t hflags;
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    /* ice debug support */
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    target_ulong breakpoints[MAX_BREAKPOINTS];
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    int nb_breakpoints;
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    int singlestep_enabled; /* XXX: should use CPU single step mode instead */
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    /* Power management */
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    int power_mode;
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    /* temporary hack to handle OSI calls (only used if non NULL) */
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    int (*osi_call)(struct CPUPPCState *env);
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    /* user data */
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    void *opaque;
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};
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/*****************************************************************************/

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