Revision a42bd6cc target-ppc/op_helper.c
| b/target-ppc/op_helper.c | ||
|---|---|---|
| 881 | 881 |
#if !defined (CONFIG_USER_ONLY) |
| 882 | 882 |
void do_rfi (void) |
| 883 | 883 |
{
|
| 884 |
env->nip = (target_ulong)(env->spr[SPR_SRR0] & ~0x00000003); |
|
| 885 |
T0 = (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL); |
|
| 886 | 884 |
#if defined(TARGET_PPC64) |
| 887 |
ppc_store_msr_32(env, T0); |
|
| 885 |
if (env->spr[SPR_SRR1] & (1ULL << MSR_SF)) {
|
|
| 886 |
env->nip = (uint64_t)(env->spr[SPR_SRR0] & ~0x00000003); |
|
| 887 |
do_store_msr(env, (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL)); |
|
| 888 |
} else {
|
|
| 889 |
env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003); |
|
| 890 |
ppc_store_msr_32(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL)); |
|
| 891 |
} |
|
| 888 | 892 |
#else |
| 889 |
do_store_msr(env, T0); |
|
| 893 |
env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003); |
|
| 894 |
do_store_msr(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL)); |
|
| 890 | 895 |
#endif |
| 891 | 896 |
#if defined (DEBUG_OP) |
| 892 | 897 |
dump_rfi(); |
| ... | ... | |
| 895 | 900 |
} |
| 896 | 901 |
|
| 897 | 902 |
#if defined(TARGET_PPC64) |
| 898 |
void do_rfi_32 (void) |
|
| 899 |
{
|
|
| 900 |
env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003); |
|
| 901 |
T0 = (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL); |
|
| 902 |
ppc_store_msr_32(env, T0); |
|
| 903 |
#if defined (DEBUG_OP) |
|
| 904 |
dump_rfi(); |
|
| 905 |
#endif |
|
| 906 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
|
| 907 |
} |
|
| 908 |
|
|
| 909 | 903 |
void do_rfid (void) |
| 910 | 904 |
{
|
| 911 |
env->nip = (target_ulong)(env->spr[SPR_SRR0] & ~0x00000003); |
|
| 912 |
T0 = (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL); |
|
| 913 |
do_store_msr(env, T0); |
|
| 914 |
#if defined (DEBUG_OP) |
|
| 915 |
dump_rfi(); |
|
| 916 |
#endif |
|
| 917 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
|
| 918 |
} |
|
| 919 |
|
|
| 920 |
void do_rfid_32 (void) |
|
| 921 |
{
|
|
| 922 |
env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003); |
|
| 923 |
T0 = (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL); |
|
| 924 |
do_store_msr(env, T0); |
|
| 905 |
if (env->spr[SPR_SRR1] & (1ULL << MSR_SF)) {
|
|
| 906 |
env->nip = (uint64_t)(env->spr[SPR_SRR0] & ~0x00000003); |
|
| 907 |
do_store_msr(env, (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL)); |
|
| 908 |
} else {
|
|
| 909 |
env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003); |
|
| 910 |
do_store_msr(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL)); |
|
| 911 |
} |
|
| 925 | 912 |
#if defined (DEBUG_OP) |
| 926 | 913 |
dump_rfi(); |
| 927 | 914 |
#endif |
| ... | ... | |
| 936 | 923 |
((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) || |
| 937 | 924 |
((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) || |
| 938 | 925 |
((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) || |
| 939 |
((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) |
|
| 926 |
((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
|
|
| 940 | 927 |
do_raise_exception_err(EXCP_PROGRAM, EXCP_TRAP); |
| 928 |
} |
|
| 941 | 929 |
} |
| 942 | 930 |
|
| 943 | 931 |
#if defined(TARGET_PPC64) |
| ... | ... | |
| 1196 | 1184 |
} |
| 1197 | 1185 |
|
| 1198 | 1186 |
#if !defined(CONFIG_USER_ONLY) |
| 1199 |
void do_4xx_rfci (void)
|
|
| 1187 |
void do_40x_rfci (void)
|
|
| 1200 | 1188 |
{
|
| 1201 | 1189 |
env->nip = env->spr[SPR_40x_SRR2]; |
| 1202 |
T0 = env->spr[SPR_40x_SRR3] & ~0xFFFF0000; |
|
| 1203 |
do_store_msr(env, T0); |
|
| 1190 |
do_store_msr(env, env->spr[SPR_40x_SRR3] & ~0xFFFF0000); |
|
| 1191 |
#if defined (DEBUG_OP) |
|
| 1192 |
dump_rfi(); |
|
| 1193 |
#endif |
|
| 1194 |
env->interrupt_request = CPU_INTERRUPT_EXITTB; |
|
| 1195 |
} |
|
| 1196 |
|
|
| 1197 |
void do_rfci (void) |
|
| 1198 |
{
|
|
| 1199 |
#if defined(TARGET_PPC64) |
|
| 1200 |
if (env->spr[SPR_BOOKE_CSRR1] & (1 << MSR_CM)) {
|
|
| 1201 |
env->nip = (uint64_t)env->spr[SPR_BOOKE_CSRR0]; |
|
| 1202 |
} else |
|
| 1203 |
#endif |
|
| 1204 |
{
|
|
| 1205 |
env->nip = (uint32_t)env->spr[SPR_BOOKE_CSRR0]; |
|
| 1206 |
} |
|
| 1207 |
do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_CSRR1] & ~0x3FFF0000); |
|
| 1208 |
#if defined (DEBUG_OP) |
|
| 1209 |
dump_rfi(); |
|
| 1210 |
#endif |
|
| 1211 |
env->interrupt_request = CPU_INTERRUPT_EXITTB; |
|
| 1212 |
} |
|
| 1213 |
|
|
| 1214 |
void do_rfdi (void) |
|
| 1215 |
{
|
|
| 1216 |
#if defined(TARGET_PPC64) |
|
| 1217 |
if (env->spr[SPR_BOOKE_DSRR1] & (1 << MSR_CM)) {
|
|
| 1218 |
env->nip = (uint64_t)env->spr[SPR_BOOKE_DSRR0]; |
|
| 1219 |
} else |
|
| 1220 |
#endif |
|
| 1221 |
{
|
|
| 1222 |
env->nip = (uint32_t)env->spr[SPR_BOOKE_DSRR0]; |
|
| 1223 |
} |
|
| 1224 |
do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_DSRR1] & ~0x3FFF0000); |
|
| 1225 |
#if defined (DEBUG_OP) |
|
| 1226 |
dump_rfi(); |
|
| 1227 |
#endif |
|
| 1228 |
env->interrupt_request = CPU_INTERRUPT_EXITTB; |
|
| 1229 |
} |
|
| 1230 |
|
|
| 1231 |
void do_rfmci (void) |
|
| 1232 |
{
|
|
| 1233 |
#if defined(TARGET_PPC64) |
|
| 1234 |
if (env->spr[SPR_BOOKE_MCSRR1] & (1 << MSR_CM)) {
|
|
| 1235 |
env->nip = (uint64_t)env->spr[SPR_BOOKE_MCSRR0]; |
|
| 1236 |
} else |
|
| 1237 |
#endif |
|
| 1238 |
{
|
|
| 1239 |
env->nip = (uint32_t)env->spr[SPR_BOOKE_MCSRR0]; |
|
| 1240 |
} |
|
| 1241 |
do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_MCSRR1] & ~0x3FFF0000); |
|
| 1204 | 1242 |
#if defined (DEBUG_OP) |
| 1205 | 1243 |
dump_rfi(); |
| 1206 | 1244 |
#endif |
| 1207 | 1245 |
env->interrupt_request = CPU_INTERRUPT_EXITTB; |
| 1208 | 1246 |
} |
| 1209 | 1247 |
|
| 1210 |
void do_4xx_load_dcr (int dcrn)
|
|
| 1248 |
void do_load_dcr (void)
|
|
| 1211 | 1249 |
{
|
| 1212 | 1250 |
target_ulong val; |
| 1213 | 1251 |
|
| 1214 | 1252 |
if (unlikely(env->dcr_read == NULL)) |
| 1215 | 1253 |
do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL); |
| 1216 |
else if (unlikely((*env->dcr_read)(env->dcr_env, dcrn, &val) != 0))
|
|
| 1254 |
else if (unlikely((*env->dcr_read)(env->dcr_env, T0, &val) != 0))
|
|
| 1217 | 1255 |
do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG); |
| 1218 | 1256 |
else |
| 1219 | 1257 |
T0 = val; |
| 1220 | 1258 |
} |
| 1221 | 1259 |
|
| 1222 |
void do_4xx_store_dcr (int dcrn)
|
|
| 1260 |
void do_store_dcr (void)
|
|
| 1223 | 1261 |
{
|
| 1224 | 1262 |
if (unlikely(env->dcr_write == NULL)) |
| 1225 | 1263 |
do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL); |
| 1226 |
else if (unlikely((*env->dcr_write)(env->dcr_env, dcrn, T0) != 0))
|
|
| 1264 |
else if (unlikely((*env->dcr_write)(env->dcr_env, T0, T1) != 0))
|
|
| 1227 | 1265 |
do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG); |
| 1228 | 1266 |
} |
| 1229 | 1267 |
|
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